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FT32F0xxx8 RM V1.30 en

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FT32F0xxx8 RM V1.30 en

Uploaded by

eng hanif
Copyright
© © All Rights Reserved
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Fremont Micro Devices FT32F0xxx8 RM

Fremont Micro Devices

FT32F0xxx8
Reference manual
Introduction
This reference manual targets application developers. It provides complete information on how to use the
FT32F030x8/FT32F032x8/FT32F072x8 microcontroller memory and peripherals.

It applies to the FT32F030R8A, FT32F030C8x, FT32F030K8A, FT32F030K8B, FT32F030G8B,


FT32F030F8A, FT32F030K6x, FT32F030F6A, FT32F030F6C, FT32F032K8B, FT32F032G8B,
FT32F032G8C, FT32F072R8AT7, FT32F072R8BT7, FT32F072C8BT7, FT32F072C8AT7 and
FT32F072K6BT7 devices.

For the purpose of this manual, FT32F030xxx8/FT32F032xxx8/FT32F072xxx8 microcontrollers are referred


to as “FT32F0xxx8”.

The FT32F0xxx8 is a family of microcontrollers with different memory sizes, packages and peripherals.

For ordering information, mechanical and electrical device characteristics, please refer to the corresponding
datasheet.

® ® ®
For information on the ARM Cortex -M0 core, please refer to the Cortex -M0 technical reference manual.

Related documents

®
Cortex -M0 technical reference manual, available from: http://infocenter.arm.com.
 FT32F0xxx8 datasheets available from Fremont Micro Devices website: www.fremontmicro.com.

Rev1.3 1 2024-03-22
Fremont Micro Devices FT32F0xxx8 RM

Contents
1. Documentation conventions ................................................................................................................... 17
1.1. List of abbreviations for registers .................................................................................................. 17
1.2. Glossary ........................................................................................................................................ 17
1.3. Peripheral availability .................................................................................................................... 17
2. System and memory overview ............................................................................................................... 18
2.1. System architecture ...................................................................................................................... 18
2.2. Memory organization ..................................................................................................................... 20
2.2.1. Introduction ....................................................................................................................... 20
2.2.2. Memory map and register boundary addresses ............................................................... 21
2.3. Embedded SRAM ......................................................................................................................... 22
2.4. Flash memory overview ................................................................................................................ 23
2.5. Boot configuration ......................................................................................................................... 23
3. Embedded Flash memory ...................................................................................................................... 25
3.1. Flash main features ....................................................................................................................... 25
3.2. Flash memory functional description ............................................................................................ 25
3.2.1. Flash memory organization .............................................................................................. 25
3.2.2. Read operations ............................................................................................................... 26
3.2.3. Flash program and erase operations ............................................................................... 27
3.2.4. Memory protection ............................................................................................................ 31
3.2.5. Flash interrupts ................................................................................................................. 34
3.3. Flash register map ........................................................................................................................ 34
3.3.1. FLASH_ACR .................................................................................................................... 35
3.3.2. FLASH_KEYR .................................................................................................................. 36
3.3.3. FLASH_OPTKEYR ........................................................................................................... 36
3.3.4. FLASH_SR ....................................................................................................................... 37
3.3.5. FLASH_CR ....................................................................................................................... 38
3.3.6. FLASH_AR ....................................................................................................................... 39
3.3.7. FLASH_OBR .................................................................................................................... 39
3.3.8. FLASH_WRPR ................................................................................................................. 41
4. Option Byte............................................................................................................................................. 42
4.1. Option Byte Introduction ................................................................................................................ 42
4.2. Option Byte register map .............................................................................................................. 42
4.2.1. User and read protection option byte ............................................................................... 43
4.2.2. User data option byte........................................................................................................ 44
4.2.3. Write protection option byte1 ............................................................................................ 45
4.2.4. Write protection option byte2 ............................................................................................ 45
5. Cyclic redundancy check calculation unit (CRC) ................................................................................... 46
5.1. CRC main features ........................................................................................................................ 46
5.2. CRC functional description............................................................................................................ 46
5.3. CRC register map ......................................................................................................................... 48
5.3.1. CRC_DR ........................................................................................................................... 49
5.3.2. CRC_IDR .......................................................................................................................... 49
5.3.3. CRC_CR ........................................................................................................................... 49
5.3.4. CRC_INIT ......................................................................................................................... 50

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6. Power control (PWR) ............................................................................................................................. 51


6.1. Power supplies .............................................................................................................................. 51
6.1.1. Voltage regulator ............................................................................................................... 51
6.1.2. Power on reset (POR) / power down reset (PDR) ............................................................ 52
6.1.3. Programmable voltage detector (PVD) ............................................................................ 53
6.2. Low-power modes ......................................................................................................................... 53
6.2.1. Slowing down system clocks ............................................................................................ 54
6.2.2. Peripheral clock gating ..................................................................................................... 54
6.2.3. Sleep mode ...................................................................................................................... 55
6.2.4. Stop mode ........................................................................................................................ 56
6.2.5. Standby mode ................................................................................................................... 57
6.2.6. RTC wakeup from low-power mode ................................................................................. 58
6.3. PWR register map ......................................................................................................................... 59
6.3.1. PWR_CR .......................................................................................................................... 59
6.3.2. PWR_CSR ........................................................................................................................ 60
7. Reset and clock control (RCC)............................................................................................................... 62
7.1. Reset ............................................................................................................................................. 62
7.1.1. Power reset ...................................................................................................................... 62
7.1.2. System reset ..................................................................................................................... 62
7.1.3. RTC ___domain reset ............................................................................................................ 63
7.2. Clocks............................................................................................................................................ 63
7.2.1. HSE clock ......................................................................................................................... 65
7.2.2. HSI clock .......................................................................................................................... 66
7.2.3. PLL clock .......................................................................................................................... 66
7.2.4. LSE clock .......................................................................................................................... 67
7.2.5. LSI clock ........................................................................................................................... 68
7.2.6. HSI14 clock ...................................................................................................................... 68
7.2.7. HSI48 clock ...................................................................................................................... 68
7.2.8. Clock Calibration .............................................................................................................. 68
7.2.9. System clock selection ..................................................................................................... 69
7.2.10. Clock security system(CSS) ............................................................................................. 69
7.2.11. RTC clock ......................................................................................................................... 70
7.2.12. Independent watchdog clock ............................................................................................ 70
7.2.13. Clock-out capability(MCO) ............................................................................................... 70
7.2.14. Internal/external clock measurement ............................................................................... 70
7.2.15. Low-power modes ............................................................................................................ 70
7.3. RCC register map ......................................................................................................................... 72
7.3.1. RCC_CR ........................................................................................................................... 73
7.3.2. RCC_CFGR ...................................................................................................................... 75
7.3.3. RCC_CIR .......................................................................................................................... 77
7.3.4. RCC_APB2RSTR ............................................................................................................. 80
7.3.5. RCC_APB1RSTR ............................................................................................................. 81
7.3.6. RCC_AHBENR ................................................................................................................. 82
7.3.7. RCC_APB2ENR ............................................................................................................... 84
7.3.8. RCC_APB1ENR ............................................................................................................... 85
7.3.9. RCC_BDCR ...................................................................................................................... 86

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7.3.10. RCC_CSR ........................................................................................................................ 88


7.3.11. RCC_AHBRSTR............................................................................................................... 90
7.3.12. RCC_CFGR2 .................................................................................................................... 91
7.3.13. RCC_CFGR3 .................................................................................................................... 92
7.3.14. RCC_CR2 ......................................................................................................................... 92
7.3.15. RCC_HSECFG ................................................................................................................. 94
7.3.16. RCC_CFGR4 .................................................................................................................... 95
7.3.17. RCC_TRIM ....................................................................................................................... 95
8. Clock recovery system (CRS) ................................................................................................................ 96
8.1. Introduction.................................................................................................................................... 96
8.2. CRS main features ........................................................................................................................ 96
8.3. CRS functional description ............................................................................................................ 97
8.3.1. CRS block diagram........................................................................................................... 97
8.3.2. Synchronization input ....................................................................................................... 97
8.3.3. Frequency error evaluation .............................................................................................. 98
8.3.4. Frequency error evaluation and automatic trimming ........................................................ 99
8.3.5. CRS initialization and configuration .................................................................................. 99
8.4. CRS low-power modes ............................................................................................................... 101
8.5. CRS interrupts ............................................................................................................................. 101
8.6. CRS register map ........................................................................................................................ 101
8.6.1. CRS_CR ......................................................................................................................... 102
8.6.2. CRS_CFGR .................................................................................................................... 103
8.6.3. CRS_ISR ........................................................................................................................ 104
8.6.4. CRS_ICR ........................................................................................................................ 107
9. General-purpose I/Os (GPIO) .............................................................................................................. 108
9.1. Introduction.................................................................................................................................. 108
9.2. GPIO main features .................................................................................................................... 108
9.3. GPIO functional description ........................................................................................................ 108
9.3.1. General-purpose I/O (GPIO) .......................................................................................... 110
9.3.2. I/O pin alternate function multiplexer and mapping ........................................................ 110
9.3.3. I/O port control registers .................................................................................................. 111
9.3.4. I/O port data registers ...................................................................................................... 111
9.3.5. I/O data bitwise handling ................................................................................................. 111
9.3.6. GPIO locking mechanism ............................................................................................... 112
9.3.7. I/O alternate function input/output .................................................................................. 112
9.3.8. External interrupt/wakeup lines ...................................................................................... 112
9.3.9. Input configuration .......................................................................................................... 112
9.3.10. Output configuration ....................................................................................................... 113
9.3.11. Alternate function configuration ...................................................................................... 114
9.3.12. Analog configuration ....................................................................................................... 114
9.3.13. LED driver mode configuration ....................................................................................... 115
9.3.14. Using the HSE or LSE oscillator pins as GPIOs ............................................................ 115
9.3.15. Using the OPx analog input pin as GPIO pins ............................................................... 115
9.3.16. Using the I2C1 fast-mode as GPIO pins ........................................................................ 115
9.3.17. Using the TOUCH as GPIO pins .................................................................................... 116
9.3.18. Alternate function of additional function ......................................................................... 116

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Fremont Micro Devices FT32F0xxx8 RM

9.4. GPIO register map ...................................................................................................................... 117


9.4.1. GPIOx_MODER ............................................................................................................. 118
9.4.2. GPIOx_OTYPER ............................................................................................................ 119
9.4.3. GPIOx_OSPEEDR ......................................................................................................... 119
9.4.4. GPIOx_PUPDR .............................................................................................................. 120
9.4.5. GPIOx_IDR ..................................................................................................................... 120
9.4.6. GPIOx_ODR ................................................................................................................... 121
9.4.7. GPIOx_BSRR ................................................................................................................. 121
9.4.8. GPIOx_LCKR ................................................................................................................. 122
9.4.9. GPIOx_AFRL .................................................................................................................. 123
9.4.10. GPIOx_AFRH ................................................................................................................. 124
9.4.11. GPIOx_BRR ................................................................................................................... 124
9.4.12. GPIOA_LEDM ................................................................................................................ 125
9.4.13. GPIOB_LEDM ................................................................................................................ 126
10. System configuration controller (SYSCFG) ......................................................................................... 127
10.1. SYSCFG register map ................................................................................................................ 127
10.1.1. SYSCFG_CFGR1........................................................................................................... 128
10.1.2. SYSCFG_EXTICR1........................................................................................................ 129
10.1.3. SYSCFG_EXTICR2........................................................................................................ 130
10.1.4. SYSCFG_EXTICR3........................................................................................................ 131
10.1.5. SYSCFG_EXTICR4........................................................................................................ 133
10.1.6. SYSCFG_CFGR2........................................................................................................... 134
11. Direct memory access controller(DMA) ............................................................................................... 135
11.1. Introduction.................................................................................................................................. 135
11.2. DMA main features ...................................................................................................................... 135
11.3. DMA functional description.......................................................................................................... 136
11.3.1. DMA transactions ........................................................................................................... 136
11.3.2. Arbiter ............................................................................................................................. 137
11.3.3. DMA channels ................................................................................................................ 137
11.3.4. Programmable data width, data alignment and endians ................................................ 139
11.3.5. Error management.......................................................................................................... 141
11.3.6. DMA interrupts ................................................................................................................ 141
11.4. DMA register map ....................................................................................................................... 144
11.4.1. DMA_ISR ........................................................................................................................ 146
11.4.2. DMA_IFCR ..................................................................................................................... 147
11.4.3. DMA_CCRx(x=1..5) ........................................................................................................ 148
11.4.4. DMA_CNDTRx(x=1..5) ................................................................................................... 149
11.4.5. DMA_CPARx(x=1..5) ...................................................................................................... 150
11.4.6. DMA_CMARx(x=1..5) ..................................................................................................... 151
12. Interrupts and events ........................................................................................................................... 152
12.1. Nested vectored interrupt controller(NVIC) ................................................................................. 152
12.1.1. Main features .................................................................................................................. 152
12.1.2. Interrupt and exception vectors ...................................................................................... 152
12.2. Extended interrupts and events controller(EXTI) ........................................................................ 153
12.2.1. Main features .................................................................................................................. 154
12.2.2. Event management ........................................................................................................ 154

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Fremont Micro Devices FT32F0xxx8 RM

12.2.3. Functional description..................................................................................................... 154


12.2.4. External and internal interrupt/event line mapping ......................................................... 155
12.3. EXTI register map ....................................................................................................................... 157
12.3.1. EXTI_IMR ....................................................................................................................... 157
12.3.2. EXTI_EMR ...................................................................................................................... 158
12.3.3. EXTI_RTSR .................................................................................................................... 158
12.3.4. EXTI_FTSR .................................................................................................................... 159
12.3.5. EXTI_SWIER .................................................................................................................. 160
12.3.6. EXTI_PR ......................................................................................................................... 161
13. Analog-to-digital converter(ADC) ......................................................................................................... 163
13.1. Introduction.................................................................................................................................. 163
13.2. ADC main features ...................................................................................................................... 163
13.3. ADC pins and internal signals ..................................................................................................... 164
13.4. ADC functional description .......................................................................................................... 165
13.4.1. Calibration(ADCAL) ........................................................................................................ 165
13.4.2. ADC on-off control(ADEN,ADDIS,ADRDY) .................................................................... 166
13.4.3. ADC clock(CKMODE)..................................................................................................... 167
13.4.4. Configuring the ADC ....................................................................................................... 168
13.4.5. Channel selection(CHSEL,SCANDIR) ........................................................................... 169
13.4.6. Programmable sampling time(SMP) .............................................................................. 169
13.4.7. Single conversion mode(CONT=0) ................................................................................ 170
13.4.8. Continuous conversion mode(CONT=1) ........................................................................ 170
13.4.9. Starting conversions(ADSTART) .................................................................................... 171
13.4.10. Timing ........................................................................................................................... 172
13.4.11. Stopping an ongoing conversion(ADSTP) .................................................................... 172
13.4.12. I/O Sample and hold circuits(IOSHx_SMPEN,IOSHx_AMPEN) .................................. 174
13.5. Conversion on external trigger and trigger polarity (EXTEN, EXTSEL) ..................................... 176
13.5.1. Discontinuous mode(DISCEN) ....................................................................................... 177
13.5.2. Programmable resolution(RES)- fast conversion mode ................................................. 177
13.5.3. End of conversion, end of sampling phase(EOC,EOSMP flags) ................................... 178
13.5.4. End of conversion sequence(EOSEQ flag) .................................................................... 178
13.5.5. Example timing diagrams (single/continuous modes hardware/software triggers)......... 178
13.6. Data management ....................................................................................................................... 180
13.6.1. Data register and data alignment(ADC_DR, ALIGN, ADC_IOSHxDR) .......................... 180
13.6.2. ADC overrun(OVR,OVRMOD) ....................................................................................... 180
13.6.3. Managing a sequence of data converted without using the DMA .................................. 181
13.6.4. Managing converted data without using the DMA without overrun ................................ 181
13.6.5. Managing converted data using the DMA ...................................................................... 182
13.7. Low-power features ..................................................................................................................... 183
13.7.1. Wait mode conversion .................................................................................................... 183
13.7.2. Auto-off mode(AUTOFF) ................................................................................................ 183
13.8. Analog window watchdog (AWDEN,AWDSGL,AWDCH,AWD_HTR/LTR,AWD) ........................ 184
13.9. Temperature sensor and internal reference voltage ................................................................... 185
13.10. ADC internal reference voltage ............................................................................................... 188
13.11. ADC interrupts ......................................................................................................................... 188
13.12. ADC register map .................................................................................................................... 189

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Fremont Micro Devices FT32F0xxx8 RM

13.12.1. ADC_ISR ...................................................................................................................... 190


13.12.2. ADC_IER ...................................................................................................................... 191
13.12.3. ADC_CR ....................................................................................................................... 193
13.12.4. ADC_CFGR1 ................................................................................................................ 194
13.12.5. ADC_CFGR2 ................................................................................................................ 198
13.12.6. ADC_SMPR .................................................................................................................. 198
13.12.7. ADC_TR ....................................................................................................................... 199
13.12.8. ADC_CHSELR .............................................................................................................. 200
13.12.9. ADC_DR ....................................................................................................................... 200
13.12.10. ADC_CCR ................................................................................................................... 201
13.12.11. ADC_CR2 ................................................................................................................... 202
14. Comparator .......................................................................................................................................... 204
14.1. Introduction.................................................................................................................................. 204
14.2. Main features .............................................................................................................................. 204
14.3. COMP functional description ....................................................................................................... 204
14.3.1. Introduction ..................................................................................................................... 204
14.3.2. COMP pins and internal signals ..................................................................................... 206
14.3.3. COMP reset and clocks .................................................................................................. 206
14.3.4. Comparator LOCK mechanism ...................................................................................... 206
14.3.5. COMP interrupts ............................................................................................................. 206
14.3.6. DAC output ..................................................................................................................... 207
14.4. Comparator register map ............................................................................................................ 207
14.4.1. COMPCSR ..................................................................................................................... 208
14.4.2. DACCTRL ....................................................................................................................... 210
14.4.3. DAC1DATA ..................................................................................................................... 211
14.4.4. DAC2DATA ..................................................................................................................... 211
15. Operational amplifier ............................................................................................................................ 212
15.1. Operational amplifier 1/2 description .......................................................................................... 212
15.1.1. Calibrate input offset voltage .......................................................................................... 212
15.2. Operational amplifier register map .............................................................................................. 214
15.2.1. OP_CR ........................................................................................................................... 214
16. Advanced-control timers(TIM1) ............................................................................................................ 216
16.1. TIM1 introduction ........................................................................................................................ 216
16.2. TIM1 main features ..................................................................................................................... 216
16.3. TIM1 functional description ......................................................................................................... 217
16.3.1. Time-base unit ................................................................................................................ 217
16.3.2. Counter modes ............................................................................................................... 219
16.3.3. Repetition counter .......................................................................................................... 225
16.3.4. Clock sources ................................................................................................................. 226
16.3.5. Capture/compare channels ............................................................................................ 229
16.3.6. Input capture mode......................................................................................................... 231
16.3.7. PWM input mode ............................................................................................................ 232
16.3.8. Forced output mode ....................................................................................................... 233
16.3.9. Output compare mode .................................................................................................... 234
16.3.10. PWM mode ................................................................................................................... 235
16.3.11. Complementary outputs and dead-time insertion ......................................................... 237

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16.3.12. Using the break function ............................................................................................... 239


16.3.13. Clearing the OCxREF signal on an external event ....................................................... 241
16.3.14. 6-step PWM generation ................................................................................................ 242
16.3.15. One-pulse mode ........................................................................................................... 243
16.3.16. Encoder interface mode ............................................................................................... 245
16.3.17. Timer input XOR function ............................................................................................. 247
16.3.18. Interfacing with Hall sensors ......................................................................................... 247
16.3.19. TIMx and external trigger synchronization.................................................................... 248
16.3.20. Timer synchronization ................................................................................................... 251
16.3.21. Debug mode ................................................................................................................. 252
16.4. TIM1 register map ....................................................................................................................... 252
16.4.1. TIM1 control register 1(TIM1_CR1) ................................................................................ 254
16.4.2. TIM1 control register 2(TIM1_CR2) ................................................................................ 255
16.4.3. TIM1 slave mode control register(TIM1_SMCR) ............................................................ 257
16.4.4. TIM1 DMA/interrupt enable register(TIM1_DIER) .......................................................... 259
16.4.5. TIM1 status register(TIM1_SR) ...................................................................................... 261
16.4.6. TIM1 event generation register(TIM1_EGR) .................................................................. 262
16.4.7. TIM1 capture/compare mode register 1(TIM1_CCMR1) ................................................ 264
16.4.8. TIM1 capture/compare mode register 2(TIM1_CCMR2) ................................................ 268
16.4.9. TIM1 capture/compare enable register(TIM1_CCER) ................................................... 270
16.4.10. TIM1 counter(TIM1_CNT) ............................................................................................ 274
16.4.11. TIM1 prescaler(TIM1_PSC) .......................................................................................... 274
16.4.12. TIM1 auto-reload register(TIM1_ARR) ......................................................................... 275
16.4.13. TIM1 repetition counter register(TIM1_RCR) ............................................................... 275
16.4.14. TIM1 capture/compare register 1(TIM1_CCR1) ........................................................... 276
16.4.15. TIM1 capture/compare register 2(TIM1_CCR2) ........................................................... 277
16.4.16. TIM1 capture/compare register 3(TIM1_CCR3) ........................................................... 277
16.4.17. TIM1 capture/compare register 4(TIM1_CCR4) ........................................................... 278
16.4.18. TIM1 break and dead-time register(TIM1_BDTR) ........................................................ 278
16.4.19. TIM1 DMA control register(TIM1_DCR) ....................................................................... 280
16.4.20. TIM1 DMA address for full transfer(TIM1_DMAR) ....................................................... 281
17. General-purpose timers(TIM3) ............................................................................................................. 283
17.1. TIM3 introduction ........................................................................................................................ 283
17.2. TIM3 main features ..................................................................................................................... 283
17.3. TIM3 functional description ......................................................................................................... 284
17.3.1. Time-base unit ................................................................................................................ 284
17.3.2. Counter modes ............................................................................................................... 286
17.3.3. Clock sources ................................................................................................................. 292
17.3.4. Capture/compare channels ............................................................................................ 296
17.3.5. Input capture mode......................................................................................................... 298
17.3.6. PWM input mode ............................................................................................................ 298
17.3.7. Forced output mode ....................................................................................................... 299
17.3.8. Output compare mode .................................................................................................... 300
17.3.9. PWM mode ..................................................................................................................... 301
17.3.10. One-pulse mode ........................................................................................................... 303
17.3.11. Clearing the OCxREF signal on an external event ....................................................... 305

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Fremont Micro Devices FT32F0xxx8 RM

17.3.12. Encoder interface mode ............................................................................................... 306


17.3.13. Timer input XOR function ............................................................................................. 308
17.3.14. Timers and external trigger synchronization ................................................................. 308
17.3.15. Timer synchronization ................................................................................................... 311
17.3.16. Debug mode ................................................................................................................. 315
17.4. TIM3 register map ....................................................................................................................... 316
17.4.1. TIM3 control register 1(TIM3_CR1) ................................................................................ 317
17.4.2. TIM3 control register 2(TIM3_CR2) ................................................................................ 319
17.4.3. TIM3 slave mode control register(TIM3_SMCR) ............................................................ 320
17.4.4. TIM3 DMA/Interrupt enable register(TIM3_DIER) .......................................................... 323
17.4.5. TIM3 status register(TIM3_SR) ...................................................................................... 324
17.4.6. TIM3 event generation register(TIM3_EGR) .................................................................. 325
17.4.7. TIM3 capture/compare mode register 1(TIM3_CCMR1) ................................................ 326
17.4.8. TIM3 capture/compare mode register 2(TIM3_CCMR2) ................................................ 330
17.4.9. TIM3 capture/compare enable register(TIM3_CCER) ................................................... 332
17.4.10. TIM3 counter(TIM3_CNT) ............................................................................................ 334
17.4.11. TIM3 prescaler(TIM3_PSC) .......................................................................................... 334
17.4.12. TIM3 auto-reload register(TIM3_ARR) ......................................................................... 335
17.4.13. TIM3 capture /compare register 1(TIM3_CCR1) .......................................................... 335
17.4.14. TIM3 capture/compare register 2(TIM3_CCR2) ........................................................... 336
17.4.15. TIM3 capture/compare register 3(TIM3_CCR3) ........................................................... 336
17.4.16. TIM3 capture/compare register 4(TIM3_CCR4) ........................................................... 337
17.4.17. TIM3 DMA control register(TIM3_DCR) ....................................................................... 338
17.4.18. TIM3 address for full transfer(TIM3_DMAR) ................................................................ 339
18. Basic timer(TIM6) ................................................................................................................................. 341
18.1. TIM6 introduction ........................................................................................................................ 341
18.2. TIM6 main features ..................................................................................................................... 341
18.3. TIM6 functional description ......................................................................................................... 342
18.3.1. Time-base unit ................................................................................................................ 342
18.3.2. Counter modes ............................................................................................................... 343
18.3.3. Clock source ................................................................................................................... 345
18.3.4. Debug mode ................................................................................................................... 345
18.4. TIM6 register map ....................................................................................................................... 346
18.4.1. TIM6 control register 1(TIM6_CR1) ................................................................................ 347
18.4.2. TIM6 DMA/Interrupt enable register(TIM6_DIER) .......................................................... 348
18.4.3. TIM6 status register(TIM6_SR) ...................................................................................... 348
18.4.4. TIM6 event generation register(TIM6_EGR) .................................................................. 349
18.4.5. TIM6 counter(TIM6_CNT) .............................................................................................. 349
18.4.6. TIM6 prescaler(TIM6_PSC) ........................................................................................... 350
18.4.7. TIM6 auto-reload register(TIM6_ARR) ........................................................................... 351
19. General-purpose timer(TIM14)............................................................................................................. 352
19.1. TIM14 introduction ...................................................................................................................... 352
19.2. TIM14 main features ................................................................................................................... 352
19.3. TIM14 functional description ....................................................................................................... 353
19.3.1. Time-base unit ................................................................................................................ 353
19.3.2. Counter modes ............................................................................................................... 354

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Fremont Micro Devices FT32F0xxx8 RM

19.3.3. Clock source ................................................................................................................... 356


19.3.4. Capture/compare channels ............................................................................................ 357
19.3.5. Input capture mode......................................................................................................... 358
19.3.6. Forced output mode ....................................................................................................... 359
19.3.7. Output compare mode .................................................................................................... 359
19.3.8. PWM mode ..................................................................................................................... 360
19.3.9. Debug mode ................................................................................................................... 361
19.4. TIM14 register map ..................................................................................................................... 362
19.4.1. TIM14 control register 1(TIM14_CR1)............................................................................ 362
19.4.2. TIM14 DMA/ interrupt enable register(TIM14_DIER) ..................................................... 364
19.4.3. TIM14 status register(TIM14_SR) .................................................................................. 364
19.4.4. TIM14 event generation register(TIM14_EGR) .............................................................. 365
19.4.5. TIM14 capture/compare mode register (TIM14_CCMR1) .............................................. 366
19.4.6. TIM14 capture/compare enable register (TIM14_CCER) .............................................. 369
19.4.7. TIM14 counter(TIM14_CNT) .......................................................................................... 371
19.4.8. TIM14 prescaler(TIM14_PSC) ....................................................................................... 371
19.4.9. TIM14 auto-reload register(TIM14_ARR) ....................................................................... 372
19.4.10. TIM14 capture/compare register 1(TIM14_CCR1) ....................................................... 372
19.4.11. TIM14 option register(TIM14_OR) ................................................................................ 373
20. General-purpose timers(TIM15/16/17) ................................................................................................. 374
20.1. TIM15/16/17 introduction ............................................................................................................ 374
20.2. TIM15 main features ................................................................................................................... 374
20.3. TIM16 and TIM17 main features ................................................................................................. 375
20.4. TIM15/16/17 functional description ............................................................................................. 376
20.4.1. Time-base unit ................................................................................................................ 376
20.4.2. Counter modes ............................................................................................................... 377
20.4.3. Repetition counter .......................................................................................................... 380
20.4.4. Clock sources ................................................................................................................. 381
20.4.5. Capture/compare channels ............................................................................................ 383
20.4.6. Input capture mode......................................................................................................... 385
20.4.7. PWM input mode (only for TIM15) ................................................................................. 385
20.4.8. Forced output mode ....................................................................................................... 386
20.4.9. Output compare mode .................................................................................................... 387
20.4.10. PWM mode ................................................................................................................... 388
20.4.11. Complementary outputs and dead-time insertion ......................................................... 389
20.4.12. Using the break function ............................................................................................... 391
20.4.13. One-pulse mode ........................................................................................................... 393
20.4.14. TIM15 external trigger synchronization ........................................................................ 395
20.4.15. Timer synchronization ................................................................................................... 398
20.4.16. Debug mode ................................................................................................................. 398
20.5. TIM15 register map ..................................................................................................................... 398
20.5.1. TIM15 control register 1(TIM15_CR1)............................................................................ 400
20.5.2. TIM15 control register 2(TIM15_CR2)............................................................................ 401
20.5.3. TIM15 slave mode control register(TIM15_SMCR) ........................................................ 402
20.5.4. TIM15 DMA/interrupt enable register(TIM15_DIER) ...................................................... 404
20.5.5. TIM15 status register(TIM15_SR) .................................................................................. 405

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20.5.6. TIM15 event generation register(TIM15_EGR) .............................................................. 406


20.5.7. TIM15 capture/compare mode register1 (TIM15_CCMR1)............................................ 408
20.5.8. TIM15 capture/compare enable register(TIM15_CCER) ............................................... 412
20.5.9. TIM15 counter(TIM15_CNT) .......................................................................................... 415
20.5.10. TIM15 prescaler(TIM15_PSC) ...................................................................................... 415
20.5.11. TIM15 auto-reload register(TIM15_ARR) ..................................................................... 416
20.5.12. TIM15 repetition counter register(TIM15_RCR) ........................................................... 416
20.5.13. TIM15 capture/compare register 1(TIM15_CCR1) ....................................................... 417
20.5.14. TIM15 capture/compare register 2 (TIM15_CCR2) ...................................................... 417
20.5.15. TIM15 break and dead-time register(TIM15_BDTR) .................................................... 418
20.5.16. TIM15 DMA control register(TIM15_DCR) ................................................................... 420
20.5.17. TIM15 address for full transfer(TIM15_DMAR) ............................................................ 421
20.6. TIM16 and TIM17 register map ................................................................................................... 423
20.6.1. TIM16 and TIM17 control register 1(TIM16_CR1 and TIM17_CR1) .............................. 424
20.6.2. TIM16 and TIM17control register 2(TIM16_CR2 and TIM17_CR2) ............................... 425
20.6.3. TIM16 and TIM17 DMA/ interrupt enable register(TIM16_DIER and TIM17_DIER) ...... 426
20.6.4. TIM16 and TIM17 status register(TIM16_SR and TIM17_SR) ...................................... 427
20.6.5. TIM16 and TIM17 event generation register(TIM16_EGR and TIM17_EGR) ............... 428
20.6.6. TIM16 and TIM17 capture/compare mode register 1(TIM16_CCMR1 and TIM17_CCMR1)
430
20.6.7. TIM16 and TIM17 capture/compare enable register(TIM16_CCER and TIM17_CCER)
433
20.6.8. TIM16 and TIM17 counter(TIM16_CNT and TIM17_CNT) ............................................ 437
20.6.9. TIM16 and TIM17 prescaler(TIM16_PSC and TIM17_PSC) ......................................... 437
20.6.10. TIM16 and TIM17 auto-reload register(TIM16_ARR and TIM17_ARR) ....................... 438
20.6.11. TIM16 and TIM17 repetition counter register(TIM16_RCR and TIM17_RCR) ............. 438
20.6.12. TIM16 and TIM17 capture/compare register 1(TIM16_CCR1 and TIM17_CCR1) ...... 439
20.6.13. TIM16 and TIM17 break and dead-time register(TIM16_BDTR and TIM17_BDTR) ... 440
20.6.14. TIM16 and TIM17 DMA control register(TIM16_DCR and TIM17_DCR) ..................... 442
20.6.15. TIM16 and TIM17 address for full transfer(TIM16_DMAR and TIM17_DMAR) ........... 443
21. Infrared interface(IRTIM) ...................................................................................................................... 445
22. Independent watchdog(IWDG)............................................................................................................. 446
22.1. Introduction.................................................................................................................................. 446
22.2. IWDG main features .................................................................................................................... 446
22.3. IWDG functional description........................................................................................................ 446
22.3.1. IWDG block diagram ...................................................................................................... 446
22.3.2. Window option ................................................................................................................ 447
22.3.3. Hardware watchdog........................................................................................................ 447
22.3.4. Stop/Standby mode behavior ......................................................................................... 448
22.3.5. Register access protection ............................................................................................. 448
22.3.6. Debug mode ................................................................................................................... 448
22.4. IWDG register map ..................................................................................................................... 448
22.4.1. IWDG_KR ....................................................................................................................... 449
22.4.2. IWDG_PR ....................................................................................................................... 449
22.4.3. IWDG_RLR..................................................................................................................... 450
22.4.4. IWDG_SR ....................................................................................................................... 451

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22.4.5. IWDG_WINR .................................................................................................................. 452


23. System window watchdog(WWDG) ..................................................................................................... 453
23.1. Introduction.................................................................................................................................. 453
23.2. WWDG main features ................................................................................................................. 453
23.3. WWDG functional description ..................................................................................................... 453
23.3.1. Enabling the watchdog ................................................................................................... 454
23.3.2. Controlling the downcounter ........................................................................................... 454
23.3.3. Advanced watchdog interrupt feature ............................................................................. 454
23.3.4. How to program the watchdog timeout........................................................................... 455
23.3.5. Debug mode ................................................................................................................... 456
23.4. WWDG register map ................................................................................................................... 456
23.4.1. WWDG_CR .................................................................................................................... 456
23.4.2. WWDG_CFR .................................................................................................................. 457
23.4.3. WWDG_SR .................................................................................................................... 458
24. Real-time clock(RTC) ........................................................................................................................... 459
24.1. Introduction.................................................................................................................................. 459
24.2. RTC main features ...................................................................................................................... 459
24.3. RTC functional description .......................................................................................................... 460
24.3.1. RTC block diagram ......................................................................................................... 460
24.3.2. GPIOs controlled by the RTC ......................................................................................... 461
24.3.3. Clock and prescalers ...................................................................................................... 462
24.3.4. Real-time clock and calendar ......................................................................................... 463
24.3.5. Programmable alarm ...................................................................................................... 463
24.3.6. RTC initialization and configuration ................................................................................ 463
24.3.7. Reading the calendar ..................................................................................................... 465
24.3.8. Resetting the RTC .......................................................................................................... 466
24.3.9. RTC synchronization ...................................................................................................... 466
24.3.10. RTC reference clock detection ..................................................................................... 467
24.3.11. RTC smooth digital calibration ...................................................................................... 467
24.3.12. Time-stamp function ..................................................................................................... 469
24.3.13. Tamper detection ........................................................................................................... 470
24.3.14. Calibration clock output ................................................................................................ 471
24.3.15. Alarm output ................................................................................................................. 471
24.4. RTC low-power modes ................................................................................................................ 472
24.5. RTC interrupts ............................................................................................................................. 472
24.6. RTC register map ........................................................................................................................ 473
24.6.1. RTC_TR.......................................................................................................................... 473
24.6.2. RTC_DR ......................................................................................................................... 474
24.6.3. RTC_CR ......................................................................................................................... 475
24.6.4. RTC_ISR ........................................................................................................................ 477
24.6.5. RTC_PRER .................................................................................................................... 479
24.6.6. RTC_ALRMAR ............................................................................................................... 480
24.6.7. RTC_WPR ...................................................................................................................... 481
24.6.8. RTC_SSR ....................................................................................................................... 482
24.6.9. RTC_SHIFTR ................................................................................................................. 482
24.6.10. RTC_TSTR ................................................................................................................... 483

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Fremont Micro Devices FT32F0xxx8 RM

24.6.11. RTC_TSDR ................................................................................................................... 484


24.6.12. RTC_TSSSR ................................................................................................................ 485
24.6.13. RTC_CALR ................................................................................................................... 485
24.6.14. RTC_TAFCR ................................................................................................................. 486
24.6.15. RTC_ALRMASSR ......................................................................................................... 489
25. Inter-integrated circuit (I2C) interface .................................................................................................. 491
25.1. main features .............................................................................................................................. 491
25.2. functional description .................................................................................................................. 491
25.2.1. I2C implementation......................................................................................................... 491
25.2.2. block diagram ................................................................................................................. 492
25.2.3. clock requirements ......................................................................................................... 493
25.2.4. Mode selection ............................................................................................................... 493
25.2.5. I2C initialization .............................................................................................................. 494
25.2.6. Software reset ................................................................................................................ 497
25.2.7. Data transfer ................................................................................................................... 497
25.2.8. I2C slave mode............................................................................................................... 499
25.2.9. I2C master mode ............................................................................................................ 506
25.2.10. I2Cx_TIMINGR register configuration examples .......................................................... 517
25.2.11. SMBus specific features ............................................................................................... 518
25.2.12. SMBus initialization....................................................................................................... 521
25.2.13. I2C_TIMEOUTR register configuration examples ........................................................ 523
25.2.14. SMBus slave mode ....................................................................................................... 523
25.2.15. Error conditions ............................................................................................................. 530
25.2.16. DMA requests ............................................................................................................... 531
25.2.17. Debug mode ................................................................................................................. 532
25.2.18. Low-power modes ........................................................................................................ 532
25.2.19. Interrupts ....................................................................................................................... 533
25.3. I2C register map .......................................................................................................................... 535
25.3.1. Control register 1 (I2Cx_CR1) ........................................................................................ 536
25.3.2. Control register 2 (I2Cx_CR2) ........................................................................................ 537
25.3.3. Own address 1 register (I2Cx_OAR1)............................................................................ 539
25.3.4. Own address 2 register(I2Cx_OAR2)............................................................................. 540
25.3.5. Timing register(I2Cx_TIMINGR) ..................................................................................... 540
25.3.6. Timeout register(I2Cx_TIMEOUTR) ............................................................................... 541
25.3.7. Interrupt and status register(I2Cx_ISR).......................................................................... 542
25.3.8. Interrupt clear register(I2Cx_ICR) .................................................................................. 544
25.3.9. PEC register(I2Cx_PECR) ............................................................................................. 545
25.3.10. Receive data register(I2Cx_RXDR) .............................................................................. 546
25.3.11. Transmit data register(I2Cx_TXDR) ............................................................................. 546
26. Universal synchronous asynchronous receiver transmitter(USART) ................................................... 547
26.1. USART main features ................................................................................................................. 547
26.2. USART functional description ..................................................................................................... 547
26.2.1. USART implementation .................................................................................................. 547
26.2.2. Functional description .................................................................................................... 548
26.2.3. USART character description ......................................................................................... 550
26.2.4. Transmitter...................................................................................................................... 551

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Fremont Micro Devices FT32F0xxx8 RM

26.2.5. Receiver ......................................................................................................................... 554


26.2.6. Baud rate generation ...................................................................................................... 558
26.2.7. Tolerance of the USART receiver to clock deviation ...................................................... 559
26.2.8. Auto baud rate detection ................................................................................................ 560
26.2.9. Multiprocessor communication ....................................................................................... 561
26.2.10. Parity control ................................................................................................................. 562
26.2.11. USART synchronous mode .......................................................................................... 563
26.2.12. Single-wire half-duplex communication ........................................................................ 566
26.2.13. Continuous communication using DMA........................................................................ 566
26.2.14. Hardware flow control and RS485 Driver Enable ......................................................... 568
26.2.15. Low-power modes ........................................................................................................ 570
26.2.16. Interrupts ....................................................................................................................... 570
26.3. USART register map ................................................................................................................... 572
26.3.1. Control register 1 (USARTx_CR1) ................................................................................. 573
26.3.2. Control register 2 (USARTx_CR2) ................................................................................. 575
26.3.3. Control register 3 (USARTx_CR3) ................................................................................. 576
26.3.4. Baud rate register (USARTx_BRR) ................................................................................ 578
26.3.5. Receiver timeout register (USARTx_RTOR) .................................................................. 578
26.3.6. Request register (USARTx_RQR) .................................................................................. 578
26.3.7. Interrupt and status register (USARTx_ISR) .................................................................. 579
26.3.8. Interrupt flag clear register (USARTx_ICR) .................................................................... 581
26.3.9. Receive data register (USARTx_RDR) .......................................................................... 582
26.3.10. Transmit data register (USARTx_TDR) ........................................................................ 583
27. Serial peripheral interface(SPI) ............................................................................................................ 584
27.1. Introduction.................................................................................................................................. 584
27.2. SPI main features ........................................................................................................................ 584
27.3. SPI functional description ............................................................................................................ 585
27.3.1. SPI functional description ............................................................................................... 585
27.3.2. Communications between one master and one slave ................................................... 586
27.3.3. Standard multi-slave communication ............................................................................. 588
27.3.4. Slave select (NSS) pin management ............................................................................. 589
27.3.5. Communication formats ................................................................................................. 590
27.3.6. Configuration of SPI ....................................................................................................... 592
27.3.7. Procedure for enabling SPI ............................................................................................ 593
27.3.8. Data transmission and reception procedures ................................................................. 593
27.3.9. SPI status flags ............................................................................................................... 601
27.3.10. SPI error flags ............................................................................................................... 602
27.3.11. NSS pulse mode ........................................................................................................... 603
27.3.12. TI mode ......................................................................................................................... 604
27.3.13. CRC calculation ............................................................................................................ 605
27.4. SPI interrupts .............................................................................................................................. 606
27.5. SPI register map ......................................................................................................................... 607
27.5.1. SPI control register 1(SPIx_CR1) ................................................................................... 608
27.5.2. SPI control register 2(SPIx_CR2) ................................................................................... 610
27.5.3. SPI status register(SPIx_SR) ......................................................................................... 612
27.5.4. SPI data register(SPIx_DR) ........................................................................................... 614

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Fremont Micro Devices FT32F0xxx8 RM

27.5.5. SPI CRC polynomial register(SPIx_CRCPR) ................................................................. 614


27.5.6. SPI Rx CRC register(SPIx_RXCRCR) ........................................................................... 615
27.5.7. SPI Tx CRC register(SPIx_TXCRCR) ............................................................................ 616
27.5.8. SPI slave speed register (SPIx_SSPR).......................................................................... 617
28. Universal serial bus full-speed device interface(USB) ......................................................................... 618
28.1. Main features .............................................................................................................................. 618
28.2. Functional description ................................................................................................................. 618
28.2.1. Block diagram ................................................................................................................. 618
28.2.2. USB RAM ....................................................................................................................... 619
28.2.2.1 Using USB RAM ......................................................................................... 619
28.2.2.2 AHB access USB RAM ............................................................................... 620
28.2.3. Transfer description ........................................................................................................ 620
28.2.4. Suspend mode ............................................................................................................... 626
28.3. USB register map ........................................................................................................................ 627
28.3.1. USB_FADDR .................................................................................................................. 631
28.3.2. USB_POWER................................................................................................................. 631
28.3.3. USB_INTRIN .................................................................................................................. 632
28.3.4. USB_INTROUT .............................................................................................................. 633
28.3.5. USB_INTRUSB .............................................................................................................. 633
28.3.6. USB_INTRINE ................................................................................................................ 634
28.3.7. USB_INTROUTE ............................................................................................................ 635
28.3.8. USB_INTRUSBE ............................................................................................................ 635
28.3.9. USB_FRAM1 .................................................................................................................. 636
28.3.10. USB_FRAM2 ................................................................................................................ 636
28.3.11. USB_INDEX ................................................................................................................. 636
28.3.12. USB_PDCTRL .............................................................................................................. 636
28.3.13. USB_CSR0 ................................................................................................................... 637
28.3.14. USB_OUTCOUNTER ................................................................................................... 638
28.3.15. USB_INMAXP ............................................................................................................... 638
28.3.16. USB_INCSR1 ............................................................................................................... 638
28.3.17. USB_INCSR2 ............................................................................................................... 639
28.3.18. USB_OUTMAXP........................................................................................................... 640
28.3.19. USB_OUTCSR1 ........................................................................................................... 640
28.3.20. USB_OUTCSR2 ........................................................................................................... 641
28.3.21. USB_FIFO0 .................................................................................................................. 641
28.3.22. USB_FIFO1 .................................................................................................................. 641
28.3.23. USB_FIFO2 .................................................................................................................. 641
28.3.24. USB_FIFO3 .................................................................................................................. 642
28.3.25. USB_FIFO4 .................................................................................................................. 642
28.3.26. USB_FIFO5 .................................................................................................................. 643
28.3.27. USB_FIFO6 .................................................................................................................. 643
28.3.28. USB_FIFO7 .................................................................................................................. 643
29. Touch sensing controller(TSC) ............................................................................................................. 644
29.1. Introduction.................................................................................................................................. 644
29.2. TSC main features ...................................................................................................................... 644
29.3. TSC functional description .......................................................................................................... 644

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Fremont Micro Devices FT32F0xxx8 RM

29.3.1. Surface charge transfer acquisition overview................................................................. 644


29.3.2. Charge transfer acquisition sequence ............................................................................ 645
29.3.3. Frequency hopping ......................................................................................................... 647
29.3.4. TSC operating mode ...................................................................................................... 647
29.3.5. Capacitive sensing GPIOs ............................................................................................. 648
29.3.6. TSC low power mode ..................................................................................................... 650
29.4. TSC register map ........................................................................................................................ 650
29.4.1. TSC_CR ......................................................................................................................... 650
29.4.2. TSC_CFGR .................................................................................................................... 651
30. Debug support(Debug) ......................................................................................................................... 653
30.1. Overview ..................................................................................................................................... 653
30.1.1. Reference ARM documentation ..................................................................................... 654
30.2. Function description .................................................................................................................... 654
30.2.1. Pinout and debug port pins ............................................................................................ 654
30.2.2. SWD port pins ................................................................................................................ 654
30.2.3. Internal pull-up & pull-down on SWD pins ...................................................................... 654
30.2.4. ID codes and locking mechanism ................................................................................... 654
30.2.5. MCU device ID code....................................................................................................... 655
30.2.6. SWD protocol introduction .............................................................................................. 655
30.2.7. SWD protocol sequence ................................................................................................. 655
30.2.8. SW-DP state machine (reset, idle states, ID code) ........................................................ 656
30.2.9. DP and AP read/write accesses ..................................................................................... 656
30.2.10. SW-DP registers ........................................................................................................... 657
30.2.11. SW-AP registers ........................................................................................................... 657
30.2.12. Core Debug registers.................................................................................................... 658
30.2.13. MCU debug component (DBGMCU) ............................................................................ 659
30.2.14. Debug support for low-power modes............................................................................ 659
30.2.14.1 Debug support for timers, watchdog .......................................................... 659
30.2.14.2 Debug MCU configuration register (DBGMCU_CR) .................................. 659
30.3. Core Debug register map ............................................................................................................ 660
30.3.1. DFSR .............................................................................................................................. 660
30.3.2. DHCSR ........................................................................................................................... 661
30.3.3. DCRSR ........................................................................................................................... 662
30.3.4. DCRDR ........................................................................................................................... 663
30.3.5. DEMCR .......................................................................................................................... 663
30.4. MCU Debug register map ........................................................................................................... 664
30.4.1. DBGMCU_IDCODE........................................................................................................ 664
30.4.2. Debug MCU configuration register (DBGMCU_CR) ...................................................... 665
30.4.3. Debug MCU APB1 freeze register(DBGMCU_APB1_FZ) ............................................. 666
30.4.4. Debug MCU APB2 freeze register (DBGMCU_APB2_FZ) ............................................ 668
31. Device electronic signature .................................................................................................................. 669
31.1. Overview ..................................................................................................................................... 669
31.2. Unique device ID register (96 bits) .............................................................................................. 669
31.3. Flash size register map ............................................................................................................... 671
31.3.1. FLASH_SIZE .................................................................................................................. 671
Revision History........................................................................................................................................... 672

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1. Documentation conventions

1.1. List of abbreviations for registers

The following abbreviations are used in register descriptions:


read/write(rw) Software can read and write to these bits.
read-only(r) Software can only read these bits.
write-only(w) Software can only write to this bit. Reading the bit returns the reset value.
read/clear(rc_w1) Software can read as well as clear this bit by writing 1. Writing ‘0’ has no effect on
the bit value.
read/clear(rc_w0) Software can read as well as clear this bit by writing 0. Writing ‘1’ has no effect on
the bit value.
read/clear by read(rc_r) Software can read this bit. Reading this bit automatically clears it to ‘0’. Writing ‘0’
has no effect on the bit value.
read/set(rs) Software can read as well as set this bit. Writing ‘0’ has no effect on the bit value.
Reserved(Res) Reserved bit, must be kept at reset value.

1.2. Glossary

This section gives a brief definition of acronyms and abbreviations used in this document:
 Word: data of 32-bit length.
 Half-word: data of 16-bit length.
 Byte: data of 8-bit length.
 SWD-DP(SWD DEBUG PORT): SWD-DP provides a 2-pin (clock and data) interface based on the
Serial Wire Debug (SWD) protocol. Please refer to the Cortex®-M0 technical reference manual.
 IAP(in application programming): IAP is the ability to re-program the Flash memory of a microcontroller
while the user program is running.
 ICP(in circuit programming): ICP is the ability to program the Flash memory of a microcontroller using
the JTAG protocol, the SWD protocol or the bootloader while the device is mounted on the user
application board.
 Option bytes: product configuration bits stored in the Flash memory.
 OBL_LAUNCH: option byte loader.
 AHB: advanced high-performance bus.
 APB: advanced peripheral bus.

1.3. Peripheral availability

For peripheral availability and number across all sales types, please refer to the particular device datasheet.

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2. System and memory overview

2.1. System architecture

The main system consists of:


 Up to two masters:
- ARM Cotex-M0 core
- General-purpose DMA
 Three slaves:
- Internal SRAM
- Internal Flash memory
- AHB to APB bridge which connects all the APB peripherals

FLASH I/F FLASH


CORTEXM0

SRAM

2m3s
busMatrix GPIO PWR
I2C1/I2C2
UART1/UART2
CRC SPI1/SPI2
IWDG
DMAC WWDG
RTC
USB TIM1/3/6/14/15/16/17
AHB

LEB
EXTI
RCC ADC
IOSH1/IOSH2
COMP
TOUCH DAC
OP1/OP2
AHB2APB
CRS
APB1 DBGMCU
bridge
DIV

Figure 2-1 System architecture

 System bus
This bus connects the system bus of the Cortex ®-M0 core (peripherals bus) to a BusMatrix which manages
the arbitration between the core and the DMA.

 DMA bus

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Fremont Micro Devices FT32F0xxx8 RM

This bus connects the AHB master interface of the DMA to the BusMatrix which manages the access of CPU
and DMA to SRAM, Flash memory and peripherals.
 BusMatrix
The BusMatrix manages the access arbitration between the core system bus and the DMA master bus. The
arbitration uses a Round Robin algorithm.

 AHB to APB bridge (APB)


The AHB to APB bridge provides full synchronous connections between the AHB and the APB bus.
Refer to Section 2.2.2: Memory map and register boundary addresses for the address mapping of the
peripherals connected to this bridge.
After each device reset, all peripheral clocks are disabled (except for the SRAM and Flash). Before using a
peripheral you have to enable its clock in the RCC_AHBENR, RCC_APB2ENR or RCC_APB1ENR register.

Note: When a 16- or 8-bit access is performed on an APB register, the access is transformed into a 32-bit
access: the bridge duplicates the 16- or 8-bit data to feed the 32-bit vector.

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2.2. Memory organization

2.2.1. Introduction

Program memory, data memory, registers and I/O ports are organized within the same linear 4-Gbyte
address space.The bytes are coded in memory in Little Endian format. The lowest numbered byte in a
word is considered the word’s least significant byte and the highest numbered byte the most significant.
The addressable memory space is divided into 8 main blocks, of 512 Mbyte each.
0x4800 17FF
AHB

0x4800 0000

0xFFFF FFFF
7
Reserved
0xE010 0000
0xE000 0000 M0 peripherals

6 0x4002 4400
Reserved

0xC000 0000 AHB

5 0x4002 0000
Reserved

0xA000 0000 Reserved

4 0x4001 8000
Reserved
0x1FFF FFFF
0x8000 0000 Reserved
APB
0x1FFF FA00
3 Option Bytes 0x4001 0000
Reserved 0x1FFFF800

0x6000 0000 System memory Reserved


0x1FFF C800
2 Reserved 0x4000 8000
0x4000 6000 APB
0x4000 0000 Peripherals Reserved
0x4000 5C00 AHB

1 Reserved 0x4000 0000 APB


0x0802 0000
Flash main
0x2000 0000 SRAM
memory
0x0800 0000
0
CODE
Reserved
0x0000 0000 0x0002 0000
main mem.,
system mem. or
SRAM depending
on boot
0x0000 0000 configuration

Figure 2-2 Memory map

All the memory areas that are not allocated to on-chip memories and peripherals are considered “Reserved”.
For the detailed mapping of available memory and register areas, please refer to the Memory map and
register boundary addresses chapter and peripheral chapters.

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2.2.2. Memory map and register boundary addresses

See the datasheet corresponding to your device for a comprehensive diagram of the memory map.
The following table gives the boundary addresses of the peripherals available in the devices.
Table 2-1 Peripheral register boundary addresses
Bus Boundary address Size Peripheral
0x4800 1800 - 0x5FFF FFFF ~384 MB Reserved
0x4800 1400 - 0x4800 17FF 1 kB GPIOF
0x4800 1000 - 0x4800 13FF 1 kB Reserved
0x4800 0C00 - 0x4800 0FFF 1 kB GPIOD
0x4800 0800 - 0x4800 0BFF 1 kB GPIOC
0x4800 0400 - 0x4800 07FF 1 kB GPIOB
0x4800 0000 - 0x4800 03FF 1 kB GPIOA
0x4002 4400 - 0x47FF FFFF ~128 MB Reserved
AHB 0x4002 4000 - 0x4002 43FF 1 kB TSC
0x4002 3400 - 0x4002 3FFF 3 kB Reserved
0x4002 3000 - 0x4002 33FF 1 kB CRC
0x4002 2400 - 0x4002 2FFF 3 kB Reserved
0x4002 2000 - 0x4002 23FF 1 kB Flash Interface
0x4002 1400 - 0x4002 1FFF 3 kB Reserved
0x4002 1000 - 0x4002 13FF 1 kB RCC
0x4002 0400 - 0x4002 0FFF 3 kB Reserved
0x4002 0000 - 0x4002 03FF 1 kB DMA
APB 0x4001 8000 - 0x4001 FFFF 32 kB Reserved
0x4001 5C00 - 0x4001 7FFF 9 kB Reserved
0x4001 5800 - 0x4001 5BFF 1 kB DBGMCU
0x4001 4C00 - 0x4001 57FF 3 kB Reserved
0x4001 4800 - 0x4001 4BFF 1 kB TIM17
0x4001 4400 - 0x4001 47FF 1 kB TIM16
0x4001 4000 - 0x4001 43FF 1 kB TIM15
0x4001 3C00 - 0x4001 3FFF 1 kB Reserved
0x4001 3800 - 0x4001 3BFF 1 kB USART1
0x4001 3400 - 0x4001 37FF 1 kB Reserved
0x4001 3000 - 0x4001 33FF 1 kB SPI1
0x4001 2C00 - 0x4001 2FFF 1 kB TIM1
0x4001 2800 - 0x4001 2BFF 1 kB Reserved
0x4001 2400 - 0x4001 27FF 1 kB ADC
0x4001 0800 - 0x4001 23FF 7 kB Reserved
0x4001 0400 - 0x4001 07FF 1 kB EXTI
0x4001 0000 - 0x4001 03FF 1 kB SYSCFG+COMP+OP0+DAC
0x4000 7400 - 0x4000 FFFF 35 kB Reserved

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0x4000 7000 - 0x4000 73FF 1 kB PWR


0x4000 6C00 - 0x4000 6FFF 1 kB CRS
0x4000 6000 - 0x4000 6BFF 3 kB Reserved
AHB 0x4000 5C00 - 0x4000 5FFF 1 kB USB
0x4000 5800 - 0x4000 5BFF 1 kB I2C2
0x4000 5400 - 0x4000 57FF 1 kB I2C1
0x4000 4800 - 0x4000 53FF 3 kB Reserved
0x4000 4400 - 0x4000 47FF 1 kB USART2
0x4000 3C00 - 0x4000 43FF 2 kB Reserved
0x4000 3800 - 0x4000 3BFF 1 kB SPI2
0x4000 3400 - 0x4000 37FF 1 kB Reserved
0x4000 3000 - 0x4000 33FF 1 kB IWDG
APB 0x4000 2C00 - 0x4000 2FFF 1 kB WWDG
0x4000 2800 - 0x4000 2BFF 1 kB RTC
0x4000 2400 - 0x4000 27FF 1 kB Reserved
0x4000 2000 - 0x4000 23FF 1 kB TIM14
0x4000 1400 - 0x4000 1FFF 3 kB Reserved
0x4000 1000 - 0x4000 13FF 1 kB TIM6
0x4000 0800 - 0x4000 0FFF 2 kB Reserved
0x4000 0400 - 0x4000 07FF 1 kB TIM3
0x4000 0000 - 0x4000 03FF 1 kB Reserved
SRAM 0x2000 2000 - 0x3FFF FFFF ~ 512 MB Reserved
0x2000 0000 - 0x2000 1FFF 8 kB SRAM
Flash 0x1FFF FA00 - 0x1FFF FFFF 1.5 kB Reserved
0x1FFF F800 - 0x1FFF F9FF 0.5 kB Option bytes
0x1FFF E800 - 0x1FFF F7FF 4 kB Sysem memory
0x0801 0000 - 0x1FFF E7FF ~ 384 MB Reserved
0x0800 0000 - 0x0800 FFFF 64 kB Main Flash memory
0x0001 0000 - 0x07FF FFFF ~ 128 MB Reserved
0x0000 0000 - 0x0000 FFFF 64 kB Main Flash memory
system memory or SRAM depending
on BOOT configuration

2.3. Embedded SRAM

FT32F0xxx8 devices feature 8 Kbytes of static SRAM. This RAM can be accessed as bytes, half-words (16
bits) or full words (32 bits). This memory can be addressed at maximum system clock frequency without wait
state and thus by both CPU and DMA.

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2.4. Flash memory overview

The Flash memory is composed of two distinct physical areas:


 The main Flash memory block. It contains the application program and user data if necessary.
 The information block. It is composed of two parts:
- Option bytes for hardware and memory protection user configuration.
- System memory which contains the proprietary boot loader code. Please, refer to section3 for more
details.

2.5. Boot configuration

In the FT32F0xxx8, three different boot modes can be selected through the BOOT0 pin and boot
configuration bits nBOOT1 in the User option byte, as shown in the following table.
Table 2-2 Boot modes
Boot mode configuration
Mode
nBOOT1 BOOT0 pin
x 0 Main Flash memory is selected as boot area
1 1 System memory is selected as boot area
0 1 Embedded SRAM is selected as boot area

The boot mode configuration is latched on the 4th rising edge of SYSCLK after a reset. It is up to the user to
set boot mode configuration related to the required boot mode.

The boot mode configuration is also re-sampled when exiting from Standby mode. Consequently they must
be kept in the required Boot mode configuration in Standby mode. After this startup delay has elapsed, the
CPU fetches the top-of-stack value from address 0x0000 0000, then starts code execution from the boot
memory at 0x0000 0004.

Depending on the selected boot mode, main Flash memory, system memory or SRAM is accessible as
follows:

 Boot from main Flash memory: the main Flash memory is aliased in the boot memory space (0x0000
0000), but still accessible from its original memory space (0x0800 0000). In other words, the Flash
memory contents can be accessed starting from address 0x0000 0000 or 0x0800 0000.
 Boot from system memory: the system memory is aliased in the boot memory space (0x0000 0000), but
still accessible from its original memory space (0x1FFF E800)
 Boot from the embedded SRAM: the SRAM is aliased in the boot memory space (0x0000 0000), but it
is still accessible from its original memory space (0x2000 0000).

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Physical remap

Once the boot mode is selected, the application software can modify the memory accessible in the code area.
This modification is performed by programming the MEM_MODE bits in SYSCFG1 register. Unlike Cortex®
M3 and M4, the M0 CPU does not support the vector table relocation. For application code which is located
in a different address than 0x0800 0000, some additional code must be added in order to be able to serve the
application interrupts. A solution will be to relocate by software the vector table to the internal SRAM:

 Copy the vector table from the Flash (mapped at the base of the application load address) to the base
address of the SRAM at 0x2000 0000.

 Remap SRAM at address 0x0000 0000, using SYSCFG configuration register 1.


 Then once an interrupt occurs, the Cortex®-M0 processor will fetch the interrupt handler start address
from the relocated vector table in SRAM, then it will jump to execute the interrupt handler located in the
Flash.

This operation should be done at the initialization phase of the application.

Embedded boot loader


The embedded boot loader is located in the System memory, programmed by FMD during production. It is
used to reprogram the Flash memory using UART.

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3. Embedded Flash memory

3.1. Flash main features

 Up to 68 Kbyte of Flash memory


 Memory organization:
- Main Flash memory block: Up to 16 Kword (16 K × 32 bits)
- Information block: Up to 4 Kword (4 K × 8 bits) for the system memory
- Up to 0.5k byte (0.5kx8 bit) for the option byte
Flash memory interface features:
 Read interface with prefetch buffer
 Option byte Loader
 Flash Program / Erase operation
 Read / Write protection
 Low-power mode

3.2. Flash memory functional description

3.2.1. Flash memory organization

The Flash memory is organized as 64-bit wide memory cells that can be used for storing both code and data
constants. The memory organization of FT32F0xxx8 devices is based on a main Flash memory block
containing up to 128 pages of 0.5 Kbyte or up to 16 sectors of 4 Kbytes (2 pages).
Table 3-1 Flash memory organization
Flash area Address Size(kB) Name Description
Main area 0x8000000~0x80001FF 0.5 Page0 Sector0
0x8000200~0x80003FF 0.5 Page1
0x8000400~0x80005FF 0.5 Page2
0x8000600~0x80007FF 0.5 Page3
0x8000800~0x80009FF 0.5 Page4
0x8000A00~0x8000BFF 0.5 Page5
0x8000C00~0x8000DFF 0.5 Page6
0x8000E00~0x8000FFF 0.5 Page7
… … … …
0x800F000~0x800F1FF 0.5 Page120 Sector15
0x800F200~0x800F3FF 0.5 Page121
0x800F400~0x800F5FF 0.5 Page122
0x800F600~0x800F7FF 0.5 Page123
0x800F800~0x800F9FF 0.5 Page124

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0x800FA00~0x800FBFF 0.5 Page125


0x800FC00~0x800FDFF 0.5 Page126
0x800FE00~0x800FFFF 0.5 Page127
Information area 0x1FFFE800~0x1FFFF7FF 4 - System memory, MAIN
0x1FFFF800~0x1FFFF9FF 0.5 - UserOption
Note:
1. Main area can use page erase and sector erase ,other areas can only use page erase.
2. Mass erase will not affect system memory

IAP code(boot loader)store in System memory.

3.2.2. Read operations

The embedded Flash module can be addressed directly, as a common memory space. Any data read
operation accesses the content of the Flash module through dedicated read senses and provides the
requested data.The instruction fetch and the data access are both done through the same AHB bus. Read
accesses can be performed with the following options managed through the Flash access control register
(FLASH_ACR):
 Instruction fetch: Prefetch buffer enabled for a faster CPU execution
 Latency: number of wait states for a correct read operation (from 0 to 1)

Instruction fetch
The Cortex®-M0 fetches the instruction over the AHB bus. The prefetch block aims at increasing the
efficiency of instruction fetching.

Prefetch buffer
The prefetch buffer is 4 blocks wide where each block consists of 4 byte. The prefetch blocks are
direct-mapped. A block can be completely replaced on a single read to the Flash memory as the size of the
block matches the bandwidth of the Flash memory. The implementation of this prefetch buffer makes a
faster CPU execution possible as the CPU fetches one word at a time with the next word readily available in
the prefetch buffer.

Prefetch controller
The prefetch controller decides to access the Flash memory depending on the available space in the
prefetch buffer. The Controller initiates a read request when there is at least two block free in the prefetch
buffer.After reset, the state of the prefetch buffer is on .Only when SYSCLK is lower than 24 MHz and the
AHB clock not divided , the prefetch buffer can be switched on/off and it is usually switched on/off during
the initialization routine, while the microcontroller is running on the internal 8 MHz RC (HSI) oscillator.

Access latency
In order to maintain the control signals to read the Flash memory, the ratio of the prefetch controller clock
period to the access time of the Flash memory has to be programmed in the Flash access control register
with the LATENCY[2:0] bits. This value gives the number of cycles needed to maintain the control signals of
the Flash memory and correctly read the required data. After reset, the value is zero and only one cycle
without additional wait states is required to access the Flash memory.

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3.2.3. Flash program and erase operations

The FT32F0xxx8 embedded Flash memory can be programmed using in-circuit programming or
in-application programming.
The in-circuit programming (ICP) method is used to update the entire contents of the Flash memory, using
the SWD protocol or the boot loader to load the user application into the microcontroller. ICP offers quick
and efficient design iterations and eliminates unnecessary package handling or socketing of devices.
In contrast to the ICP method, in-application programming (IAP) can use any communication interface
supported by the microcontroller (I/Os, USB, USART, I2C, SPI, etc.) to download programming data into
memory. IAP allows the user to re-program the Flash memory while the application is running. Nevertheless,
part of the application has to have been previously programmed in the Flash memory using ICP.
The program and erase operations can be performed over the whole product voltage range. They are
managed through the following seven Flash registers:
 Key register (FLASH_KEYR)
 Option byte key register (FLASH_OPTKEYR)
 Flash control register (FLASH_CR)
 Flash status register (FLASH_SR)
 Flash address register (FLASH_AR)
 Option byte register (FLASH_OBR)
 Write protection register (FLASH_WRPR)
An ongoing Flash memory operation will not block the CPU as long as the CPU does not access the Flash
memory. On the contrary, during a program/erase operation to the Flash memory, any attempt to read the
Flash memory will stall the bus. The read operation will proceed correctly once the program/erase operation
has completed. This means that code or data fetches cannot be made while a program/erase operation is
ongoing.
Unlocking the Flash memory
After reset, the Flash memory is protected against unwanted write or erase operations. The FLASH_CR
register is not accessible in write mode, except for the OBL_LAUNCH bit, used to reload the option bits. An
unlocking sequence should be written to the FLASH_KEYR register to open the access to the FLASH_CR
register. This sequence consists of two write operations:
 Write KEY1 = 0x45670123
 Write KEY2 = 0xCDEF89AB
Any wrong sequence locks up the FLASH_CR register until the next reset.
In the case of a wrong key sequence, a bus error is detected and a Hard Fault interrupt is generated. This is
done after the first write cycle if KEY1 does not match, or during the second write cycle if KEY1 has been
correctly written but KEY2 does not match. The FLASH_CR register can be locked again by user software by
writing the LOCK bit in the FLASH_CR register to 1.
Main Flash memory programming
The main Flash memory can be programmed 16 bits at a time. The program operation is started when the
CPU writes a half-word into a main Flash memory address with the PG bit of the FLASH_CR register set.
Any attempt to write data that are not half-word long will result in a bus error generating a Hard Fault
interrupt.

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Read LOCK bit

Perform unlock
LOCK=1? Y
sequency

Write MAPG to 1

Perform word
write at the
desired address
Y

BUSY=1?

Check the
programmed value

Figure 3-1 Programming procedure


The Flash memory interface preliminarily reads the value at the addressed main Flash memory ___location and
checks that it has been erased. If not, the program operation is skipped and a warning is issued by the
PGERR bit in FLASH_SR register.
If the addressed main Flash memory ___location is write-protected by the FLASH_WRPR register, the program
operation is skipped and a warning is issued. The end of the program operation is indicated by the EOP bit in
the FLASH_SR register.

The main Flash memory programming sequence in standard mode is as follows:


1. Check that no main Flash memory operation is ongoing by checking the BSY bit in the FLASH_SR
register.
2. Set the PG bit in the FLASH_CR register
3. Perform the data write (half-word) at the desired address.
4. Wait until the BSY bit is reset in the FLASH_SR register.
5. Check the EOP flag in the FLASH_SR register (it is set when the programming operation has
succeeded), and then clear it by software.
Note: The registers are not accessible in write mode when the BSY bit of the FLASH_SR register is set.
Flash memory erase
The Flash memory can be erased page by page or completely (Mass Erase).
Page Erase
To erase a page, the procedure below should be followed:
1. Check that no Flash memory operation is ongoing by checking the BSY bit in the FLASH_CR
register;
2. Set the PER bit in the FLASH_CR register;

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3. Program the FLASH_AR register to select a page to erase;


4. Set the STRT bit in the FLASH_CR register;
5. Wait for the BSY bit to be reset;
6. Check the EOP flag in the FLASH_SR register

Read LOCK bit

Perform unlock
LOCK=1? Y
sequence

Write PER bit in


FLASH_CR

Write into
FLASH_AR an
address within the
page to erase

Write STRT bit to1

BUSY=1?

Check the page is


erased by reading
all the addresses
in the page

Figure 3-2 Flash memory Page erase prosedure


Mass Erase
The Mass Erase command can be used to completely erase the pages of the Main Flash memory. The
information block is unaffected by this procedure. The following sequence is recommended:
1. Check that no Flash memory operation is ongoing by checking the BSY bit in the FLASH_SR register.
2. Set the MER bit in the FLASH_CR register.
3. Set the STRT bit in the FLASH_CR register.
4. Wait until the BSY bit is reset in the FLASH_SR register.
5. Check the EOP flag in the FLASH_SR register

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Read LOCK bit

Perform unlock
LOCK=1? Y
sequence

Write MER bit in


FLASH_CR

Write STRT bit to1

BUSY=1?

Check the page is


erased by reading
all the addresses
in the user
memory

Figure 3-3 Flash memory Mass erase prosedure


Option byte programming
The option byte are programmed differently from normal user addresses. The number of option byte is
limited to 4 (2 for write protection, 1 for read protection, 1 for hardware). After unlocking the Flash access,
the user has to authorize the programming of the option byte by writing the same set of KEYS (KEY1 and
KEY2) to the FLASH_OPTKEYR register to set the OPTWRE bit in the FLASH_CR register . Then the user
has to set the OPTPG bit in the FLASH_CR register and perform a half-word write operation at the desired
Flash address.The value of the addressed option byte is first read to check it is really erased. If not, the
program operation is skipped and a warning is issued by the WRPRTERR bit in the FLASH_SR register.
The end of the program operation is indicated by the EOP bit in the FLASH_SR register.
The option byte is automatically complemented into the next flash memory address before the programming
operation starts. This guarantees that the option byte and its complement are always correct.
The sequence is as follows:
1. Check that no Flash memory operation is ongoing by checking the BSY bit in the FLASH_SR register.
2. Unlock the OPTWRE bit in the FLASH_CR register.
3. Set the OPTPG bit in the FLASH_CR register.
4. Write the data (half-word) to the desired address.
5. Wait for the BSY bit to be reset.
6. Read the programmed value and verify.
When the Flash memory read protection option is changed from protected to unprotected, a Mass Erase of
the main Flash memory is performed before reprogramming the read protection option. If the user wants to
change an option other than the read protection option, then the mass erase is not performed. The erased

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state of the read protection option byte protects the Flash memory.
Erase procedure
The option byte erase sequence is as follows:
1. Check that no Flash memory operation is ongoing by reading the BSY bit in the FLASH_SR register
2. Unlock the OPTWRE bit in the FLASH_CR register
3. Set the OPTER bit in the FLASH_CR register
4. Set the STRT bit in the FLASH_CR register
5. Wait for the BSY bit to be reset
6. Read the erased option byte and verify

3.2.4. Memory protection

The user area of the Flash memory can be protected against read by untrusted code. The pages of the
Flash memory can also be protected against unwanted write due to loss of program counter contexts. The
write-protection granularity is one sector (eight pages).
1)Read protection
The read protection is activated by setting the RDP option byte and then, by applying a system reset to
reload the new RDP option byte.
Note: If the read protection is set while the debugger is still connected through JTAG/SWD, apply a POR
(power-on reset) instead of a system reset.
There are three levels of read protection from no protection (level 0) to maximum protection or no debug
(level 2). The Flash memory is protected when the RDP option byte and its complement contain the pair of
values.
Table 3-2 Flash memory read protection status
RDP nRDP Read protection level
Level 0 (FMD production
0xAA 0x55
configuration)
Any value (not necessarily
Any value except 0xAA or 0xCC complementary) except 0x55 and Level 1
0x33
0xCC 0x33 Level 2
The System memory area is read accessible whatever the protection level. It is never accessible for
program/erase operation
Level 0: no protection
Read, program and erase operations into the main Flash memory area are possible. The option byte are as
well accessible by all operations.
Level 1: read protection
This is the default protection level when RDP option byte is erased. It is defined as well when RDP value is
0xFF, or even if the complement is not correct.
 User mode: Code executing in user mode can access main Flash memory and option byte with all
operations.
 Debug, boot RAM and boot loader modes: In debug mode or when code is running from boot

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RAM or boot loader, the main Flash memory is totally inaccessible.


In these modes, even a simple read access generates a bus error and a Hard Fault interrupt. The
main Flash memory is program/erase protected to prevent malicious or unauthorized users from
reprogramming any of the user code with a dump routine. Any attempted program/erase operation
sets the PGERR flag of Flash status register (FLASH_SR).When the RPD is reprogrammed to the
value 0xAA to move back to Level 0, a mass erase of the main Flash memory is performed.
Level 2: no debug
In this level, the protection level 1 is guaranteed. In addition, the CortexM0 debug capabilities are disabled.
Moreover, the RDP byte cannot be programmed. Thus, the level 2 cannot be removed at all FMD is not able
to perform analysis on defective parts on which the level 2 protection has been set.

Table 3-3 Access status versus protection level and execution modes
Debug / Boot From RAM / Boot
Protection User execution
Flash From System memory
level
Read Write Erase Read Write Erase
4
1 Yes Yes Yes No No No
Main area 1 1 1
2 Yes Yes Yes N/A N/A N/A
2
1 Yes No No Yes No No
System area 1 1 1
2 Yes No No N/A N/A N/A
3 4 3,4
1 Yes Yes Yes Yes Yes Yes
UserOption 5 1 1 1
2 Yes Yes No N/A N/A N/A
Note:
1. When the protection level 2 is active, the Debug port, the boot from RAM and the boot from System
memory are disabled.
2. The system memory is only read-accessible, whatever the protection level (0, 1 or 2) and execution
mode.
3. The main Flash memory is erased when the RDP option byte is changed from level 1 to level 0
(0xAA).
4. When the RDP level 1 is active, the embedded boot loader don’t allow to read or write the Option byte,
except to remove the RDP protection (move from level 1 to level 0).
5. All option byte can be programmed, except the RDP byte.
2)Write protection
The write protection is implemented with a granularity of one sector. It is activated by configuring the WRPx
option byte, and then by reloading them by setting the OBL_LAUNCH bit in the FLASH_CR register. If a
program or an erase operation is performed on a protected sector, the Flash memory returns a WRPRTERR
protection error flag in the Flash memory Status Register (FLASH_SR).
Write unprotection
To disable the write protection, two application cases are provided:
 Case 1: Read protection disabled after the write unprotection:
- Erase the entire option byte area by using the OPTER bit in the Flash memory control register
(FLASH_CR).
- Program the code 0xA5 in the RDP byte to unprotect the memory. This operation forces a Mass
Erase of the main Flash memory.

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- Set the OBL_LAUNCH bit in the Flash control register (FLASH_CR) to reload the option byte (and
the new WRP[1:0] byte), and to disable the write protection.
 Case 2: Read protection maintained active after the write unprotection, useful for in- application
programming with a user boot loader:
- Erase the entire option byte area by using the OPTER bit in the Flash memory control register
(FLASH_CR).
- Set the OBL_LAUNCH bit in the Flash control register (FLASH_CR) to reload the option byte
(and the new WRP[1:0] byte), and to disable the write protection.
Option byte write protection
The option byte are always read-accessible and write-protected by default. To gain write access
(Program/Erase) to the option byte, a sequence of keys (same as for lock) has to be written into the
OPTKEYR. A correct sequence of keys gives write access to the option byte and this is indicated by
OPTWRE in the FLASH_CR register being set. Write access can be disabled by resetting the bit through
software.

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3.2.5. Flash interrupts

Table 3-4 Flash interrupt request


Interrupt event Event flag Enable control bit
End of operation EOP EOPIE
Write protection error WRPRTERR ERRIE
Programming error PGERR ERRIE

3.3. Flash register map

Base address is 0x40022000.


31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
Offset Register

9
8
7
6
5
4
3
LATENCY 2
1
0
PRFTBS
PRFTBE

[3:0]
FLASH_ACR
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
0x00

Reset x x x x x x x x x x x x x x x x x x x x x x x x x x 0 1 0 0 0 1

FLASH_KEYR FKEY[31:0]
0x04
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FLASH_
OPTKEY[31:0]
0x08 OPTKEYR
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

WRPRTERR

PGERR

BUSY
EOP

FLASH_SR
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_

_
0x0C

Reset x x x x x x x x x x x x x x x x x x x x x x x x x x 0 0 x 0 x 0
OBL_LAUNCH

OPTWRE

OPTPG
OPTER
EOPIE

ERRIE

LOCK
STRT

MER
PER
PG

FLASH_CR
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_

0x10

Reset x x x x x x x x x x x x x x x x x x 0 0 x 0 0 x 1 0 0 0 x 0 0 0

FLASH_AR FAR[31:0]
0x14
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VDDA_MONITOR

nRST_STDBY
nRST_STOP

RDPRT[1:0]
WDG_SW

OPTERR
nBOOT1

FLASH_OBR DATA1[7:0] DATA0[7:0]


_
_

_
_
_
_
_

0x1C

Reset x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x

FLASH_WRPR WRP[31:0]
0x20
Reset x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x

Rev1.3 34 2024-03-22
Fremont Micro Devices FT32F0xxx8 RM

3.3.1. FLASH_ACR

Address Offset:0x00
Reset value:0x0000 0010

Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0


31:24 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
7:0 — PRFTBS PRFTBE LATENCY
Type RO-0 RO-0 RO RW RW RW RW RW

Bit Name Function


31:6 NA Reserved
5 PRFTBS This bit provides the status of the prefetch buffer
0: Prefetch buffer is disabled
1: Prefetch buffer is enabled(The prefetch status is set to 1 as soon a first
fetch request is done)
4 PRFTBE Prefetch buffer enable
0: Prefetch is disabled
1: Prefetch is enabled
Note:
Boot from System memory or SRAM, PRFTBE cleared automatically
Boot from main area switch to System memoryor SRAM, PRFTBE must be
cleared by software;
If address 0 is mapped to system memory or SRAM, PRFTBE wiil be locked at
0 and cannot be writed
3:0 LATENCY These bits represent the ratio of the SYSCLK (system clock) period to the
Flash access time
0: HCLK ≤ 24MHz
1: 24MHz < HCLK ≤ 48MHz
2: 48MHz < HCLK ≤ 72MHz

Rev1.3 35 2024-03-22
Fremont Micro Devices FT32F0xxx8 RM

3.3.2. FLASH_KEYR

Address Offset:0x04
Reset value:0x0000 0000

Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0


31:24 FKEY[31:24]
Type WO WO WO WO WO WO WO WO
23:16 FKEY[23:16]
Type WO WO WO WO WO WO WO WO
15:8 FKEY[15:8]
Type WO WO WO WO WO WO WO WO
7:0 FKEY[7:0]
Type WO WO WO WO WO WO WO WO

Bit Name Function


31:0 FKEY Main Flash area unlock sequence:
0x45670123
0xCDEF89AB
Bit[1:0] returns internal status in read operation
Bit[1:0] Description
00 Idle
01 KEY1 has been correctly written
10 KEY1 and KEY2 have been correctly written
11 Error

3.3.3. FLASH_OPTKEYR

Address Offset:0x08
Reset value:0x0000 0000

Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0


31:24 OPTKEY[31:24]
Type WO WO WO WO WO WO WO WO
23:16 OPTKEY[23:16]
Type WO WO WO WO WO WO WO WO
15:8 OPTKEY[15:8]
Type WO WO WO WO WO WO WO WO
7:0 OPTKEY[7:0]
Type WO WO WO WO WO WO WO WO

Rev1.3 36 2024-03-22
Fremont Micro Devices FT32F0xxx8 RM

Bit Name Function


31:0 OPTKEY UserOption unlock sequence:
0x45670123
0xCDEF89AB
Bit[1:0] returns internal status in read operation
Bit[1:0] Description
00 Idle
01 KEY1 has been correctly written
10 KEY1 and KEY2 have been correctly written
11 Error

3.3.4. FLASH_SR

Address Offset:0x0C
Reset value:0x0000 0000

Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0


31:24 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
7:0 — EOP WRPRTERR — PGERR — BSY
Type RO-0 RO-0 RW RW RO-0 RW RO-0 RW

Bit Name Function


31:6,3,1 NA Reserved
5 EOP End of operation
1:Set by hardware when a Flash operation (programming / erase) is
completed. Reset by writing 1.
4 WRPRTERR Write protection error
1:Set by hardware when programming a write-protected address of the
Flash memory. Reset by writing 1.
2 PGERR Programming error
1:Set by hardware when an address to be programmed contains a value
different from '0xFFFF' before programming. Reset by writing 1.
0 BSY Busy
1:This indicates that a Flash operation is in progress. This is set on the
beginning of a Flash operation and reset when the operation finishes or
when an error occurs.

Rev1.3 37 2024-03-22
Fremont Micro Devices FT32F0xxx8 RM

3.3.5. FLASH_CR

Address Offset:0x10
Reset value:0x0000 0080

Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0


31:24 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 — OBL_LAUNCH EOPIE — ERRIE OPTWRE —
Type RO-0 RO-0 RW RW RO-0 RW RW RO-0
7:0 LOCK STRT OPTER OPTPG — MER PER PG
Type RW1 RW RW RW RW RW RW RW

Bit Name Function


31:14,11,8,3 NA Reserved
13 OBL_LAUNC Force option byte loading
H When set to 1, this bit forces the option byte reloading. This operation
generates a system reset.
0: Inactive 1: Active
12 EOPIE End of operation interrupt enable, active-high
10 ERRIE Error interrupt enable
This bit enables the interrupt generation on an error when PGERR /
WRPRTERR are set in the FLASH_SR register.
0: Interrupt generation disabled
1: Interrupt generation enabled
9 OPTWRE Option byte write enable
When set, the option byte can be programmed. This bit is set on writing the
correct key sequence to the FLASH_OPTKEYR register.
7 LOCK FLASH lock state
1:When it is set, it indicates that the Flash is locked. This bit is reset by
hardware after detecting the unlock sequence. In the event of unsuccessful
unlock operation, this bit remains set until the next reset.F
0:Flash is unlocked
6 STRT This bit triggers an ERASE operation when set. This bit is set only by
software and reset when the BSY bit is reset.
5 OPTER UserOption erase chosen.
4 OPTPG UserOption programming chosen
2 MER Erase of all user pages chosen.
1 PER Page Erase chosen.
0 PG Flash programming chosen.

Rev1.3 38 2024-03-22
Fremont Micro Devices FT32F0xxx8 RM

3.3.6. FLASH_AR

Address Offset:0x14
Reset value:0x0000 0000

Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0


31:24 FAR[31:24]
Type RW RW RW RW RW RW RW RW
23:16 FAR[23:16]
Type RW RW RW RW RW RW RW RW
15:8 FAR[15:8]
Type RW RW RW RW RW RW RW RW
7:0 FAR[7:0]
Type RW RW RW RW RW RW RW RW

Bit Name Function


31:0 FAR Flash Address
Chooses the address to program when programming is selected, or a page to
erase when Page Erase is selected.
Note: Write access to this register is blocked when the BSY bit in the
FLASH_SR register is set.

3.3.7. FLASH_OBR

Address Offset:0x1C
Reset value:0xXXXX XXXX,read only

Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0


31:24 DATA1
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 DATA0
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 — VDDA_MONITOR nBOOT1 — nRST_STDBY nRST_STOP WDG_SW
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
7:0 — RDPRT[1:0] OPTERR
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0

Bit Name Function


15:14,11,7:3 NA Reserved

Rev1.3 39 2024-03-22
Fremont Micro Devices FT32F0xxx8 RM

31:24 DATA1 When OPT1[31:24] is complementary to OPT1[23:16], DATA1 is


OPT1[23:16],otherwise is 0xFFFF
23:16 DATA0 When OPT1[15:8] is complementary to OPT1[7:0], DATA1 is
OPT1[7:0],otherwise is 0xFFFF
13 VDDA_MONIT VDDA MONITOR
OR 0: Disabled
1:Enabled
12 nBOOT1 BOOT mode configured bit
10 nRST_STDBY 0:Reset generated when entering Standby mode.
1:No reset generated
9 nRST_STOP 0: Reset generated when entering Stop mode.
1: No reset generated
8 WDG_SW 1: Software watchdog
0: Hardware watchdog
2:1 RDPRT Read protection level status
00:Read protection level 0 is enabled, OPT0.RDP=0xAA,
OPT0.nRDP=0x55
01:Read protection level 1 is enabled, OPT0.RDP is not equal to 0xAA or
0xCC (OPT0.nRDP not effected)
11:Read protection level 2 is enabled, OPT0.RDP=0xCC and
OPT0.nRDP=0x33
0 OPTERR Option byte error
When set, this indicates that the loaded option byte and its complement do
not match. The corresponding byte and its complement are read as 0xFF in
the FLASH_OBR or FLASH_WRPR register.
bit[15:8] decided by OPT0[31:16]
When OPT0.USER = OPT0.nUSER,FLASH_OBR[15:8] = OPT0.USER,otherwise is 0xFF;

Rev1.3 40 2024-03-22
Fremont Micro Devices FT32F0xxx8 RM

3.3.8. FLASH_WRPR

Address Offset:0x20
Reset value:0xXXXX XXXX

Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0


31:0 WRP[31:0]
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0

Bit Name Function


31:0 WRP Flash Write protect, active low
Bitx= 0:Sectorx write protection active
Bitx= 1:Sectorx write protection not active
When OPT2[15:8] is complementary to OPT2[7:0], WRP[7:0] = OPT2 [7:0],
otherwise is 0xFF;
When OPT2[31:24] is complementary to OPT2[23:16], WRP[15:8] =
OPT2[23:16], otherwise is 0xFF;
When OPT3[15:8] is complementary to OPT3[7:0],WRP[23:16] = OPT3 [7:0],
otherwise is 0xFF;
When OPT3[31:24] is complementary to OPT3, WRP[31:24] = OPT3[23:16],
otherwise is 0xFF.

Rev1.3 41 2024-03-22
Fremont Micro Devices FT32F0xxx8 RM

4. Option Byte

4.1. Option Byte Introduction

There are up to 8 option byte. They are configured by the end user depending on the application
requirements. As a configuration example, the watchdog may be selected in hardware or software mode.

A 32-bit word is split up as follows in the option byte.


31~24 23~16 15~8 7~0
Complemented option Option byte 1 Complemented option Option byte 0
byte 1 byte 0

The organization of these byte inside the information block is as shown in Table 4-1.

The option byte can be read from the memory locations listed in Table 4-1 or from the Option byte register
(FLASH_OBR).
Note: The new programmed option byte (user, read/write protection) are loaded after a system reset.
Table 4-1 Option byte organization
Address [31:24] [23:16] [15:8] [7:0]
0x1FFFF800 nUSER USER nRDP RDP
0x1FFFF804 nDATA1 DATA1 nDATA0 DATA0
0x1FFFF808 nWRP1 WRP1 nWRP0 WRP0
0x1FFFF80C nWRP3 WRP3 nWRP2 WRP2
0x1FFFF810 nUDMY1 UDMY1 nUDMY0 UDMY0

On every system reset, the option byte loader (OBL) reads the information block and stores the data into the
Option byte register (FLASH_OBR) and the Write protection register (FLASH_WRPR). Each option byte
also has its complement in the information block. During option loading, by verifying the option bit and its
complement, it is possible to check that the loading has correctly taken place. If this is not the case, an
option byte error (OPTERR) is generated. When a comparison error occurs, the corresponding option byte
is forced to 0xFF. The comparator is disabled when the option byte and its complement are both equal to
0xFF (Electrical Erase state).

4.2. Option Byte register map

Base address is 0x1FFFF800

Rev1.3 42 2024-03-22
Fremont Micro Devices FT32F0xxx8 RM

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
Offset Register

9
8
7
6
5
4
3
2
1
0
USER

VDDA_MONITOR

nRST_STDBY
nRST_STOP
WDG_SW
nBOOT1
User and
nUSER nRDP RDP
read protection

_
_

_
0x00

production
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0
value

User data nData1 Data1 nData0 Data0


0x04
production
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
value
write
nWRP1 WRP1 nWRP0 WPR0
protection
0x08
production
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
value
write
nWPR3 WRP3 nWRP2 WPR2
protection
0x0C
production
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
value

4.2.1. User and read protection option byte

Address Offset:0x00
Reset value:0x00FF 55AA
Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 nUSER
Type RW RW RW RW RW RW RW RW
23:16 — — VDDA_ nBOOT1 — nRST_ nRST_ WDG_
MONITOR STDBY STOP SW
Type RW RW RW RW RW RW RW RW
15:8 nRDP
Type RW RW RW RW RW RW RW RW
7:0 RDP
Type RW RW RW RW RW RW RW RW

Bit Name Function


31:24 nUSER User option byte complement
23 NA Reserved
22 NA Reserved
21 VDDA_MONITOR 0:Disabled VDDA monitor
1:Enabled VDDA monitor
20 nBOOT1 Together with the BOOT0 signal, it selects the device boot mode.

Rev1.3 43 2024-03-22
Fremont Micro Devices FT32F0xxx8 RM

Boot mode configuration


nBOOT1 BOOT0 pin
x 0 Main Flash memory
1 1 System memory
0 1 Embedd SRAM
19 NA Reserved
18 nRST_STDBY 0: Reset generated when entering Standby mode.
1: No reset generated.
17 nRST_STOP 0: Reset generated when entering Stop mode
1: No reset generated
16 WDG_SW 0: Software watchdog
1: Hardware watchdog
15:8 nRDP Read protection option byte complement
7:0 RDP Read protection option byte, The value of this byte defines the Flash
memory protection level
0xAA: 0 level 0
0xXX((except 0xAA & 0xCC): Level 1
0xCC: Level 2
Note: Read protection level status is stored in bits RDPRT[1:0] of the
FLASH_OBR

4.2.2. User data option byte

Address Offset:0x04
Reset value:0x00FF 00FF
Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 nData1
Type RW RW RW RW RW RW RW RW
23:16 Data1
Type RW RW RW RW RW RW RW RW
15:8 nData0
Type RW RW RW RW RW RW RW RW
7:0 Data0
Type RW RW RW RW RW RW RW RW

Bit Name Function


31:24 nData1 User data byte 1 complement
23:16 Data1 User data byte 1 value
15:8 nData0 User data byte 0 complement
7:0 Data0 User data byte 0 value

Rev1.3 44 2024-03-22
Fremont Micro Devices FT32F0xxx8 RM

4.2.3. Write protection option byte1

Address Offset:0x08
Reset value:0x00FF 00FF
Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 nWRP1
Type RW RW RW RW RW RW RW RW
23:16 WRP1
Type RW RW RW RW RW RW RW RW
15:8 nWRP0
Type RW RW RW RW RW RW RW RW
7:0 WRP0
Type RW RW RW RW RW RW RW RW

Bit Name Function


31:24 nWRP1 Flash memory write protection option byte 1 complement
23:16 WRP1 Flash memory write protection option byte 1 value
15:8 nWRP0 Flash memory write protection option byte 0 complement
7:0 WRP0 Flash memory write protection option byte 0 value

4.2.4. Write protection option byte2

Address Offset:0x0C
Reset value:0x00FF 00FF
Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 nWRP3
Type RW RW RW RW RW RW RW RW
23:16 WRP3
Type RW RW RW RW RW RW RW RW
15:8 nWRP2
Type RW RW RW RW RW RW RW RW
7:0 WRP2
Type RW RW RW RW RW RW RW RW

Bit Name Function


31:24 nWRP3 Flash memory write protection option byte 3 complement
23:16 WRP3 Flash memory write protection option byte 3 value
15:8 nWRP2 Flash memory write protection option byte 2 complement
7:0 WRP2 Flash memory write protection option byte 2 value

Rev1.3 45 2024-03-22
Fremont Micro Devices FT32F0xxx8 RM

5. Cyclic redundancy check calculation unit


(CRC)

5.1. CRC main features

 0x4C11DB7 Uses CRC-32 (Ethernet) polynomial: 0x4C11DB7


𝑋 32 + 𝑋 26 + 𝑋 23 + 𝑋 22 + 𝑋16 + 𝑋12 + 𝑋11 + 𝑋10 + 𝑋 8 + 𝑋 7 + 𝑋 5 + 𝑋 4 + 𝑋 2 + 𝑋 + 1
 Handles 8-,16-, 32-bit data size
 Programmable CRC initial value
 Single input/output 32-bit data register
 Input buffer to avoid bus stall during calculation
 CRC computation done in 4 AHB clock cycles (HCLK) for the 32-bit data size
 General-purpose 8-bit register (can be used for temporary storage)
 Reversibility option on I/O data

5.2. CRC functional description

AHB Bus

Data register (output)

CRC computation

Data register (output)

Figure 5-1 CRC calculation unit block diagram


The CRC calculation unit has a single 32-bit read/write data register (CRC_DR). It is used to input new data
(write access), and holds the result of the previous CRC calculation (read access). Each write operation to
the data register creates a combination of the previous CRC value (stored in CRC_DR) and the new one.
CRC computation is done on the whole 32-bit data word or byte by byte depending on the format of the data
being written. The CRC_DR register can be accessed by word, right-aligned half-word and right-aligned byte.

Rev1.3 46 2024-03-22
Fremont Micro Devices FT32F0xxx8 RM

For the other registers only 32-bit access is allowed. The duration of the computation depends on data width:
4 AHB clock cycles for 32-bit, 2 AHB clock cycles for 16-bit, 1 AHB clock cycles for 8-bit.
The data size can be dynamically adjusted to minimize the number of write accesses for a given number of
bytes. For instance, a CRC for 5 bytes can be computed with a word write followed by a byte write.
An input buffer allows to immediately write a second data without waiting for any wait states due to the
previous CRC calculation.
The input data can be reversed, to manage the various endianness schemes. The reversing operation can be
performed on 8 bits, 16 bits and 32 bits depending on the REV_IN[1:0] bits in the CRC_CR register.
 0x58D43CB2 with bit-reversal done by byte
 0xD458B23C with bit-reversal done by half-word
 0xB23CD458 with bit-reversal done on the full word
The output data can also be reversed by setting the REV_OUT bit in the CRC_CR register. The operation is
done at bit level: for example, output data 0x11223344 is converted into 0x22CC4488.

The CRC calculator can be initialized to a programmable value using the RESET control bit in the CRC_CR
register (the default value is 0xFFFFFFFF).
The initial CRC value can be programmed with the CRC_INIT register. The CRC_DR register is
automatically initialized upon CRC_INIT register write access.

The CRC_IDR register can be used to hold a temporary value related to CRC calculation. It is not affected
by the RESET bit in the CRC_CR register.

Rev1.3 47 2024-03-22
Fremont Micro Devices FT32F0xxx8 RM

5.3. CRC register map


31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
Offset Register

9
8
7
6
5
4
3
2
1
0
CRC_DR DR[31:0]
0x00

Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

IDR[7:0]
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
CRC_IDR
0x04

Reset x x x x x x x x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0

REV_IN[1:0]

RESET
REV_OUT
CRC_CR
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–

–
–
–
–
0x08

Reset x x x x x x x x x x x x x x x x x x x x x x x x 0 0 0x x x x 0

CRC_INIT CRC_INIT[31:0]
0x10

Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Rev1.3 48 2024-03-22
Fremont Micro Devices FT32F0xxx8 RM

5.3.1. CRC_DR

Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0


31:24 DR[31:24]
Type RW RW RW RW RW RW RW RW
23:16 DR[23:16]
Type RW RW RW RW RW RW RW RW
15:8 DR[15:8]
Type RW RW RW RW RW RW RW RW
7:0 DR[7:0]
Type RW RW RW RW RW RW RW RW

Bit Name Function


31:0 DR Data register bits
This register is used to write new data to the CRC calculator.
It holds the previous CRC calculation result when it is read.

5.3.2. CRC_IDR

Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0


31:24 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
7:0 IDR[7:0]
Type RW RW RW RW RW RW RW RW

Bit Name Function


31:8 NA Reserved
7:0 IDR General-purpose 8-bit data register bits

5.3.3. CRC_CR

Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0


31:24 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —

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Fremont Micro Devices FT32F0xxx8 RM

Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0


15:8 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
7:0 REV_OUT REV_IN — RESET
Type RW RW RO-0 RO-0 RO-0 RO-0 RW

Bit Name Function


31:8 NA Reserved
7 REV_OUT Reverse output data
6:5 REV_IN These bits control the reversal of the bit order of the input data
00: Bit order not affected
01: Bit reversal done by byte
10: Bit reversal done by half-word
11: Bit reversal done by word
4:1 NA Reserved
0 RESET This bit is set by software to reset the CRC calculation unit and set the data
register to the value stored in the CRC_INIT register. This bit can only be set,
it is automatically cleared by hardware
1: reset the CRC calculation unit
0: Do not reset the CRC calculation unit

5.3.4. CRC_INIT

Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0


31:24 INIT[31:0]
Type RW RW RW RW RW RW RW RW
23:16 INIT[23:16]
Type RW RW RW RW RW RW RW RW
15:8 INIT[15:8]
Type RW RW RW RW RW RW RW RW
7:0 INIT[7:0]
Type RW RW RW RW RW RW RW RW

Bit Name Function


31:0 INIT Programmable initial CRC value

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6. Power control (PWR)

6.1. Power supplies

FT32F0xxx8 devices require a 5.0 V operating supply voltage, and embeds two voltage regulators in order
to supply the internal 1.6 V, 1.5V digital power ___domain.

A/D
VSSA
converter
Reset block
VDDA PLL

1.6V Domain
VSS I/O
IWDG Core
PMU Memories
VDD Voltage regulator 1.6V
Digital
Peripherals

1.5V

RTC

RTC Domain

Figure 6-1 Power supply overview

6.1.1. Voltage regulator

FT32F0xxx8 embeds two voltage regulators, one of them is 1.6V, supply for core, memories and digital
peripherals, the other is 1.5V, supply for RTC.

The 1.6V voltage regulator is always enabled after Reset. It works in three different modes depending on the
application modes.

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 In Run mode, the regulator supplies full power to the 1.6 V ___domain (core, memories and digital
peripherals).
 In Stop mode the regulator supplies low-power to the 1.6 V ___domain, preserving contents of registers
and SRAM
 In Standby Mode, the regulator is powered off. The contents of the registers and SRAM are lost except
for the Standby circuitry.

6.1.2. Power on reset (POR) / power down reset (PDR)

The device has an integrated power-on reset (POR) and power-down reset (PDR) circuits which are always
active and ensure proper operation above a threshold of VPOR.

The POR monitors only the VDD supply voltage. During the startup phase VDDA must arrive first and be equal
to VDD.
The PDR monitors both the VDD and VDDA supply voltages. However, the VDDA power supply supervisor can
be disabled to reduce the power consumption if the application is designed to make sure that VDDA is higher
than or equal to VDD.

VDD/VDDA

VPOR
40mV
hysteresis VPDR

Temporization
tRSTTEMPO

Reset

Figure 6-2 Power on reset/power down reset waveform

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6.1.3. Programmable voltage detector (PVD)

You can use the PVD to monitor the VDD power supply by comparing it to a threshold selected by the
PLS[3:0] bits. The PVD is enabled by setting the PVDE bit.

A PVDO flag is available, to indicate if VDD is higher or lower than the PVD threshold. This event is internally
connected to the EXTI line16 and can generate an interrupt if enabled through the EXTI registers.

VDD

VPVD threshold

100mV
hysteresis

PVD output

Figure 6-3 PVD thresholds

6.2. Low-power modes

By default, the microcontroller is in Run mode after a system or a power Reset. Several low- power modes
are available to save power when the CPU does not need to be kept running, for example when waiting for
an external event. It is up to the user to select the mode that gives the best compromise between low-power
consumption, short startup time and available wakeup sources.

The device features three low-power modes:


 Sleep mode
 Stop mode
 Standby mode

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In addition, the power consumption in Run mode can be reduce by one of the following means:
 Slowing down the system clocks
 Gating the clocks to the APB and AHB peripherals when they are unused.
Table 6-1 Low-power mode summary
Effect on 1.6V Effect on VDD
Mode Voltage
Entry wakeup ___domain ___domain
name regulatior
clocks clocks
WFI Any interrupt CPU clock
OFF
no effect on
Sleep 1 None ON
WFE Wakeup event other clocks
or analog
clock sources
ON or in low-
Any EXTI line
PDDS and LPDS power mode
(configured in the
Stop bits+SLEEPDEEP+WFI (depends on
EXTI registers)
or WFE PWR_CR
All 1.6V HSI、HSE、
register)
___domain HSI48 and
WKUP pin rising 2
clocks OFF PLL OFF
PDDS and edge, RTC alarm,
Standby SLEEPDEEP bit +WFI external reset in OFF
or WFE NRST pin, IWDG
reset
Note 1: Executing WFE single instruction may not be able to enter low power mode, It is recommended to
execute SEV, WFE, and WFE consecutive three instructions to enter low power mode. Executing WFI single
instruction can enter low power mode.
Note 2: When the HSI14ON=1 which HSI14 clock enable bit in the RCC_CR2 register , the HSI14 clock
keeps running.

6.2.1. Slowing down system clocks

In Run mode the speed of the system clocks can be reduced by programming the prescaler registers
(RCC_CFGR). These prescalers can also be used to slow down peripherals before entering Sleep mode.

6.2.2. Peripheral clock gating

In Run mode, the AHB clock (HCLK) and the APB clock (PCLK) for individual peripherals and memories can
be stopped at any time to reduce power consumption.

To further reduce power consumption in Sleep mode the peripheral clocks can be disabled prior to executing
the WFI or WFE instructions.

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Fremont Micro Devices FT32F0xxx8 RM

Peripheral clock gating is controlled by the RCC_AHBENR、RCC_APB1ENR and RCC_APB2ENR register

6.2.3. Sleep mode

Entering Sleep mode:


The Sleep mode is entered by executing the WFI (Wait For Interrupt) or WFE (Wait for Event) instructions.
Two options are available to select the Sleep mode entry mechanism, depending on the SLEEPONEXIT bit
in the ARM® Cortex®-M0 System Control register:
Sleep-now: if the SLEEPONEXIT bit is cleared, the MCU enters Sleep mode as soon as WFI or WFE
instruction is executed.
Sleep-on-exit: if the SLEEPONEXIT bit is set, the MCU enters Sleep mode as soon as it exits the lowest
priority ISR.

In the Sleep mode, all I/O pins keep the same state as in the Run mode.

Exiting Sleep mode:


If the WFI instruction is used to enter Sleep mode, any peripheral interrupt acknowledged by the nested
vectored interrupt controller (NVIC) can wake up the device from Sleep mode.
If the WFE instruction is used to enter Sleep mode, the MCU exits Sleep mode as soon as an event occurs.
The wakeup event can be generated either by:
 enabling an interrupt in the peripheral control register but not in the NVIC, and enabling the
SEVONPEND bit in the ARM® Cortex®-M0 System Control register. When the MCU resumes from
WFE, the peripheral interrupt pending bit and the peripheral NVIC IRQ channel pending bit (in the NVIC
interrupt clear pending register) have to be cleared.
 or configuring an external or internal EXTI line in event mode. When the CPU resumes from WFE, it is
not necessary to clear the peripheral interrupt pending bit or the NVIC IRQ channel pending bit as the
pending bit corresponding to the event line is not set.
This mode offers the lowest wakeup time as no time is wasted in interrupt entry/exit. Refer to Table 6-2 and
Table 6-3 for more details on how to exit Sleep mode.
Table 6-2 sleep-now mode
sleep-now mode Description
Mode entry WFI (Wait for Interrupt) or WFE (Wait for Event) while:
SLEEPDEEP=0 and SLEEPONEXIT=0
Mode exit If WFI was used for entry: refer to vector table
If WFE was used for entry: refer to event management
Wakeup latency None

Table 6-3 sleep-on-exit mode


sleep-on-exit mode Description
Mode entry WFI (wait for interrupt) while: SLEEPDEEP=0 and SLEEPONEXIT=1
Mode exit If WFI was used for entry: refer to vector table
Wakeup latency None

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6.2.4. Stop mode

The Stop mode is based on the ARM® Cortex®-M0 deep sleep mode combined with peripheral clock gating.
The voltage regulator can be configured either in normal or low- power mode. In Stop mode, all clocks in the
1.6 V ___domain are stopped, the PLL, the HSI and the HSE oscillators are disabled. SRAM and register
contents are preserved.

In the Stop mode, all I/O pins keep the same state as in the Run mode.

Entering Stop mode


To further reduce power consumption in Stop mode, the 1.6V voltage regulator can be put in low-power mode.
This is configured by the LPDS bit

If Flash memory programming is ongoing, the Stop mode entry is delayed until the memory access is
finished.

If an access to the APB ___domain is ongoing, The Stop mode entry is delayed until the APB access is finished.

In Stop mode, the following features can be selected by programming individual control bits:
 Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by hardware option.
Once started it cannot be stopped except by a Reset.
 Real-time clock (RTC): this is configured by the RCC_BDCR register
 Internal RC oscillator (LSI): this is configured by the LSION bit in the RCC_CSR register
 External 32.768 kHz oscillator (LSE): this is configured by the LSEON bit in the RCC_BDCR register

The ADC can also consume power during Stop mode, unless it is disabled before entering this mode.

Exiting Stop mode


When exiting Stop mode by issuing an interrupt or a wakeup event, the HSI oscillator is selected as system
clock.

When the voltage regulator operates in low-power mode, an additional startup delay is incurred when
waking up from Stop mode. By keeping the internal regulator ON during Stop mode, the consumption is
higher although the startup time is reduced.

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Table 6-4 Stop mode


Stop mode Description
WFI (Wait for Interrupt) or WFE (Wait for Event) while:
SLEEPDEEP=1
PDDS=0
Mode entry Select the voltage regulator mode by configuring LPDS bit in PWR_CR
Note: To enter Stop mode, all EXTI Line pending bits, all peripherals interrupt pending bits
and RTC Alarm flag must be reset. Otherwise, the Stop mode entry procedure is ignored
and program execution continues.
Mode exit If WFI was used for entry:
Any EXTI Line configured in Interrupt mode (the corresponding EXTI Interrupt vector must
be enabled in the NVIC).
If WFE was used for entry:
Any EXTI Line configured in event mode.
Wakeup
HSI wakeup time + 1.6V regulator wakeup time from Low-power mode
latency

6.2.5. Standby mode

The Standby mode allows to achieve the lowest power consumption. It is based on the ARM ® Cortex®-M0
deepsleep mode, with the voltage regulator disabled. The 1.6 V ___domain is consequently powered off. The
PLL, the HSI oscillator and the HSE oscillator are also switched off. SRAM and register contents are lost
except for registers in the Standby circuitry and 1.5V voltage regulator.

RTC normally work in standby mode if 1.5V voltage regulator enabled before entering the standby mode.
The power consumption can be reduced if 1.5V voltage regulator disabled before entering the standby mode
Entering Standby mode
In Standby mode, the following features can be selected by programming individual control bits:
 Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by hardware option.
Once started it cannot be stopped except by a reset.
 Real-time clock (RTC): this is configured by the RCC_BDC Rregister
 Internal RC oscillator (LSI): this is configured by the LSION bit in the RCC_CSR register
 External 32.768 kHz oscillator (LSE): this is configured by the LSEON bit in the RCC_BDCR register

Exiting Standby mode

The microcontroller exits the Standby mode when an external reset (NRST pin), an IWDG reset, a rising
edge on one of the enabled WKUPx pins or an RTC event occurs. All registers are reset after wakeup from
Standby except for PWR_CSR register.

After waking up from Standby mode, program execution restarts in the same way as after a Reset. The SBF

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status flag in the PWR_CSR register indicates that the MCU was in Standby mode.
Table 6-5 Standby mode
Standby mode Description
Mode entry WFI (Wait for Interrupt) or WFE (Wait for Event) while:
SLEEPDEEP=1
PDDS=1
Clear WUF bit
Mode exit WKUP pin rising edge
RTC alarm event’s rising edge
External Reset in NRST pin,
IWDG Reset.
Wakeup latency Reset phase

In Standby mode, all I/O pins are high impedance except:


 NRST pin
 PC13, PC14 and PC15 if configured by RTC or LSE
 WKUPx pins

By default, the debug connection is lost if the application puts the MCU in Stop or Standby mode while the
debug features are used. This is due to the fact that the ARM ® Cortex®-M0 core is no longer
clocked.However, by setting some configuration bits in the DBGMCU_CR register, the software can be
debugged even when using the low-power modes extensively.

6.2.6. RTC wakeup from low-power mode

The RTC can be used to wakeup the MCU from low-power mode by means of the RTC alarm. For this
purpose, two of the three alternative RTC clock sources can be selected by programming the RTCSEL[1:0]
bits in the RCC_BDCR register
 Low-power 32.768 kHz external crystal oscillator, this clock source provides a precise time base with
very low-power consumption
 Low-power internal RC Oscillator: This clock source has the advantage of saving the cost of the 32.768
kHz crystal. This internal RC Oscillator is designed to add minimum power consumption.

To wakeup from Stop mode with an RTC alarm event, it is necessary to:
 Configure the EXTI Line 17 to be sensitive to rising edge
 Configure the RTC to generate the RTC alarm

To wakeup from Standby mode, there is no need to configure the EXTI Line 17.

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6.3. PWR register map

The peripheral registers can be accessed by byte (8-bit) or words (32-bit).


31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10
offset Register

PLS[3] 9

CWUF 2

0
PVDE

PDDS
CSBF

LDPS
DBP

[2:0]
PLS
PWR_CR
-

-
0x00
Reset x x x x x x x x x x x x x x x x x x x x x x 1 0 0 0 0 0 0 0 0 0

EWUP2

EWUP1

PVDO

WUF
SBF
PWR_CSR
-

-
0x04

Reset x x x x x x x x x x x x x x x x x x x x x x 0 0 x x x x x 0 0 0

6.3.1. PWR_CR

Address Offset:0x00
Reset value:0x0000 0200
Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 — PLS[3] DBP
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RW RW
7:0 PLS[2:0] PVDE CSBF CWUF PDDS LDPS
Type RW RW RW RW RW-0 RW-0 RW RW

Bit Name Function


31:10 NA Resrved
9 PLS[3] PVD threshold configuration
8 DBP Disable RTC ___domain write protection.
0: Access to RTC, RCC_BDCR disabled
1: Access to RTC, RCC_BDCR enabled
7:5 PLS[2:0] PVD threshold configuration
4’b0000:1.78V
4’b0001:1.88V
4’b0010:1.98V
4’b0011:2.08V
4’b0100:2.18V
4’b0101:2.28V
4’b0110:2.38V
4’b0111:2.48V
4’b1000:2.58V
4’b1001:2.68V
4’b1010:2.78V

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4’b1011:2.88V
4’b1100:2.98V
4’b1101:3.08V
4’b1110:3.18V
4’b1111:3.28V
4 PVDE 0:PVD disabled
1:PVD enabled
3 CSBF Clear standby flag,This bit is always read as 0.
0: No effect
1:Clear the SBF Standby Flag (write)
2 CWUF Clear wakeup flag,This bit is always read as 0
0:No effect
1:Clear the WUF Wakeup Flag
1 PDDS Power down deepsleep.
This bit is set and cleared by software.
0: Enter Stop mode when the CPU enters Deepsleep. The regulator status
depends on the LPDS bit.
1: Enter Standby mode when the CPU enters Deepsleep.
0 LDPS Low-power deepsleep This bit is set and cleared by software
0:Voltage regulator on during Stop mode
1:Voltage regulator in low-power mode during Stop mode

6.3.2. PWR_CSR

Address Offset:0x04
Reset value:0x0000 0000
Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 — EWUP2 EWUP1
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RW RW
7:0 — PVDO SBF WUF
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO RO RO

Bit Name Function


31:10 NA Resrved
9:8 EWUPx Enable WKUPx pin These bits are set and cleared by software
0: WKUPx pin is used for general purpose I/O. An event on the WKUPx pin
does not wakeup the device from Standby mode.
1: WKUPx pin is used for wakeup from Standby mode and forced in input

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pull down configuration (rising edge on WKUPx pin wakes-up the system
from Standby mode).
7:3 NA Resrved
2 PVDO PVD output
This bit is set/cleared by hardware, and effective when PVDE =1
0:VDD > PVD threshold voltage
1:VDD < PVD threshold voltage
1 SBF Standby flag
This bit is set by hardware when the device enters Standby mode and it is
cleared only by a POR/PDR or by setting the CSBF bit
0: Device has not been in Standby mode
1: Device has been in Standby mode
0 WUF Wakeup flag This bit is set by hardware to indicate that the device received
a wakeup event. It is cleared by a system reset
0: No wakeup event occurred
1: A wakeup event was received from one of the enabled WKUPx pins or
from the RTC alarm.
Note: An additional wakeup event is detected if one WKUPx pin is enabled
(by setting the EWUPx bit) when its pin level is already high.

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7. Reset and clock control (RCC)

7.1. Reset

There are three types of reset, defined as system reset, power reset and RTC ___domain reset.

7.1.1. Power reset

A power reset is generated when one of the following events occurs:


1. Power-on/power-down reset (POR/PDR reset)
2. When exiting Standby mode
3. VDDA power down reset

7.1.2. System reset

A system reset is generated when one of the following events occurs:


1. A low level on the NRST pin
2. Window watchdog event (WWDG reset)
3. Independent watchdog event (IWDG reset)
4. A software reset
5. Low-power management reset
6. Option byte loader reset
7. A power reset

VDD

Rpu
NRST
Filter System reset

WWDG reset
IWDG reset
Pulse
Power reset
generator Software reset
(min 20us) Low-power management reset
Option byte loader reset

Figure 7-1 Simplified diagram of the reset circuit


The reset source can be identified by checking the reset flags in the Control/Status register, RCC_CSR
Power-on/power-down reset in VDDL ___domain will not clear the reset flags. The VDD ___domain reset will clear
the reset signal but its reset flag.
These sources act on the NRST pin and it is always kept low during the delay phase. The RESET service

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routine vector is fixed at address 0x0000_0004 in the memory map.The system reset signal provided to the
device is output on the NRST pin. The pulse generator guarantees a minimum reset pulse duration of 20 µs
for each internal reset source. In case of an external reset, the reset pulse is generated while the NRST pin
is asserted low.

NRST pin can be configured to debounce and it is only effective for external reset source., the debounce
time is configure by the RCC_RSTCR register.

Software reset:
The SYSRESETREQ bit in ARM® Cortex®-M0 Application Interrupt and Reset Control Register must be set
to force a software reset on the device.

There are two ways to generate a low-power management reset:


1. Reset generated when entering Standby mode: This type of reset is enabled by resetting nRST_STDBY
bit in User Option Bytes. In this case, whenever a Standby mode entry sequence is successfully
executed, the device is reset instead of entering Standby mode.
2. This type of reset is enabled by resetting nRST_STOP bit in User Option Bytes. In this case, whenever a
Stop mode entry sequence is successfully executed, the device is reset instead of entering Stop mode.

Option byte loader reset:


The option byte loader reset is generated when the OBL_LAUNCH bit is set in the FLASH_CR register. This
bit is used to launch the option byte loading by software.

7.1.3. RTC ___domain reset

An RTC ___domain reset only affects the RTC and the RCC_BDCR register. It is generated when one of the
following events occurs.
1. Software reset, triggered by setting the BDRST bit in the RCC_BDCR register
2. POR/PDR reset

7.2. Clocks

Various clock sources can be used to drive the system clock (SYSCLK):
1. HSI 8 MHz RC oscillator clock(HSI)
2. HSI 14 MHz RC oscillator clock(HSI14)
3. HSI 48 MHz RC oscillator clock(HSI48)
4. PLL clock
5. HSE oscillator clock(HSE)

The FT32F0xxx8 device embeds a 40kHz low speed internal crystal for IWDG and RTC. 32.768 kHz low
speed external crystal (LSE crystal) which optionally drives the RTC and USART1, 14 MHz high speed
internal RC (HSI14) dedicated for ADC.

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All the peripheral clocks are derived from their bus clock:
1. The Flash memory programming interface clock is HCLK.
2. The ADC clock which is derived (selected by software) from the dedicated HSI14 clock or APB clock
(PCLK) divided by 2 or 4
3. The USART1 clock is derived (selected by software) from system clock, HSI, LSE or APB clock(PCLK):
4. The I2C1 clock which is derived (selected by software) from system clock or HSI.
5. The USB clock which is derived (selected by software) from HSI48 and PLL
6. The RTC clock which is derived from the LSE, LSI or from the HSE clock divided by 32.
7. The IWDG clock which is always the LSI clock.
8. The timer clock frequencies are automatically fixed by hardware, if the APB prescaler is 1, the timer
clock frequencies are set to the same frequency as that of the APB ___domain, otherwise, they are set to
twice (x2) the frequency of the APB ___domain.

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Fremont Micro Devices FT32F0xxx8 RM

CRS
to ADC
asynchronous
HSI48 RC HSI48 clock input
48MHz

to I2C
HSI RC HSI
8MHz SYSCLK

to AHB bus,
HSI14 RC HSI14
core,Flash,DMA
14MHz /8 to system timer
SW FCLK Cortex free
PLLSRC PLLMUL running clock
PLL AHB APB
/1,2,3, *2,*3, prescaler prescaler PCLK to APB
...16 peripherals
…*16 PLLCLK /1,2,...512 /1,2,4,8,16
PREDIV
HSE
if(APB1
CSS prescaler to TIM1,3,6,
14,15,16,17
=1)*1 else *2
to USART2
4~32MHz PCLK
HSE OSC SYSCLK to USART1
HSI
RTCSEL[1:0] LSE

/32
LSE OSC to RTC
32.768kHz
HSI48
to USB
PLLCLK
LSI RC
to IWDG
40kHz PLLNODIV
PLLCLK /1,2 MCO
HSI MCOPRE to TMI14
HSI48
HSI14 /1,2,4,
HSE … 128 Main clock output
SYSCLK
LSI
LSE

Figure 7-2 Clock tree

7.2.1. HSE clock

The high speed external clock signal (HSE) can be generated from two possible clock sources:
1. HSE external crystal/ceramic resonator
2. HSE user external clock
The external clock signal has to drive the OSC_IN pin while OSC_OUT pin can be used a GPIO. OSC_IN

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and OSC_OUT pin need to be used when a crystal is connected to the device and the load capacitor have to
connect to them. The crystal frequency range can be 4 to 32 MHz

The HSE Crystal can be switched on and off using the HSEON bit in the RCC_CR register.

The HSERDY flag in the RCC_CR register indicates if the HSE oscillator is stable or not. At startup, the
clock is not released until this bit is set by hardware. An interrupt can be generated if enabled in the rcc_CIR
register.

Note: Once the oscillator is started, it needs another 6 HSE clock pulses to complete a switching OFF
sequence. If for any reason the oscillations are no more present on the OSC_IN pin, the oscillator cannot be
switched OFF, locking the OSC pins from any other use and introducing unwanted power consumption. To
avoid such situation, it is strongly recommended to always enable the Clock Security System (CSS) which is
able to switch OFF the oscillator even in this case.

In external clock source mode. It can have a frequency of up to 32 MHz. You select this mode by setting the
HSEBYP and HSEON bits in the

7.2.2. HSI clock

The HSI clock signal is generated from an internal 8 MHz RC oscillator and can be used directly as a system
clock or for PLL input.

The HSI RC oscillator has the advantage of providing a clock source at low cost (no external components). It
also has a faster startup time than the HSE crystal oscillator however, even with calibration the frequency is
less accurate than an external crystal oscillator or ceramic resonator.

RC oscillator frequencies can vary from one chip to another due to manufacturing process variations, this is
why each device is factory calibrated by FMD After reset, the factory calibration value is loaded in the
HSICAL[7:0] bits in the RCC_CR register.If the application is subject to voltage or temperature variations this
may affect the RC oscillator speed. You can trim the HSI frequency in the application using the HSITRIM[4:0]
bits in the RCC_CR register.

The HSIRDY flag in the RCC_CR register indicates if the HSI RC is stable or not. At startup, the HSI RC
output clock is not released until this bit is set by hardware.

The HSI RC can be switched on and off using the HSION bit in the RCC_CR register.

7.2.3. PLL clock

The internal PLL can be used to multiply the HSI, a divided HSI48 or the HSE output clock frequency. The
PLL configuration must be done before enabling the PLL. Once the PLL is enabled, these parameters

Rev1.3 66 2024-03-22
Fremont Micro Devices FT32F0xxx8 RM

cannot be changed.

The PLL output frequency must be set in the range 16-48 MHz and the minimum frequency is 0.8MHz

To modify the PLL configuration, proceed as follows:


1. Disable the PLL by setting PLLON to 0;
2. Wait until PLLRDY is cleared. The PLL is now fully stopped;
3. Change the desired parameter;
4. Enable the PLL again by setting PLLON to 1.
5. Wait until PLLRDY is set;
An interrupt can be generated when the PLL is ready

7.2.4. LSE clock

The LSE crystal is a 32.768 kHz Low Speed External crystal or ceramic resonator. It has the advantage of
providing a low-power but highly accurate clock source to the real-time clock peripheral (RTC) for
clock/calendar or other timing functions.

The LSE crystal is switched on and off using the LSEON bit in RCC_BDCR register. The crystal oscillator
driving strength can be changed at runtime using the LSEDRV[1:0] bits in the RCC_BDCR register.

The LSERDY flag in the RCC_BDCR register indicates whether the LSE crystal is stable or not. At startup,
the LSE crystal output clock signal is not released until this bit is set by hardware.

An interrupt can be generated if enabled in the RCC_CIR register.

To switch ON the LSE oscillator, 4096 LSE clock pulses need to be seen by an internal stabilization counter
after the LSEON bit is set. Even in the case that no crystal or resonator is connected to the device, excessive
external noise on the OSC32_IN pin may still lead the oscillator to start. Once the oscillator is started, it
needs another 6 LSE clock pulses to complete a switching OFF sequence. If for any reason the oscillations
are no more present on the OSC_IN pin, the oscillator cannot be switched OFF, locking the OSC32 pins from
any other use and introducing unwanted power consumption. The only way to recover such situation is to
perform the RTC ___domain reset by software.

In this mode, an external clock source must be provided. It can have a frequency of up to 1 MHz. You select
this mode by setting the LSEBYP and LSEON bits in the RCC_BDCR register. The external clock signal
(square, sinus or triangle) with ~50% duty cycle has to drive the OSC32_IN pin while the OSC32_OUT pin
can be used as GPIO.

Rev1.3 67 2024-03-22
Fremont Micro Devices FT32F0xxx8 RM

7.2.5. LSI clock

The LSI RC acts as a low-power clock source that can be kept running in Stop and Standby mode for the
independent watchdog (IWDG) and RTC. The clock frequency is around 40 kHz.

The LSI RC can be switched on and off using the LSION bit in the RCC_CSR. The LSIRDY flag in the
RCC_CSR register indicates if the LSI oscillator is stable or not. At startup, the clock is not released until this
bit is set by hardware.

An interrupt can be generated if enabled in the RCC_CIR.

7.2.6. HSI14 clock

The HSI14 clock signal is generated from an internal 14 MHz RC oscillator and can be used directly as a
system clock or for ADC clock or output from MCO pin.
The HSI14 RC can be switched on and off using the HSI14ON bit in the RCC_CR2 register. The HSIRDY
flag in the RCC_CR2 register indicates if the HSI14 RC is stable or not. An interrupt can be generated if
enabled in the RCC_CIR.
HSI14 clock can run in the STOP mode.

7.2.7. HSI48 clock

The HSI48 clock signal is generated from an internal 48 MHz RC oscillator and can be used directly as a
system clock or for USB clock or for PLL input or output from MCO pin.

The internal 48MHz RC oscillator is mainly dedicated to provide a high precision clock to the USB peripheral
by means of a special Clock Recovery System (CRS) circuitry, it will be disabled as soon as the system
enters in Stop or Standby mode. The HSI48 RC can be switched on and off using the HSI48ON bit in the
RCC_CR2 register. The HSIRDY flag in the RCC_CR2 register indicates if the HSI48 RC is stable or not. An
interrupt can be generated if enabled in the RCC_CIR..

7.2.8. Clock Calibration

The formula of HSI8 calibration is:


Calibration value = {~HSICAL[8],HSICAL[7:0]}+(HSITRIM[4:0]-5’h10),HSICAL[8:0] is HSITRIM[4:0] default
value.

HSI8 calibrated range is 9’h000~9’h1FF, 9’h000~9’h0FF is calibrated to small value. 9’h101~9’h1FF is


calibrate to big value. 9’h100 is not calibrated.

User calibrate HSI8 by writing to the HSITRIM[4:0] should meet

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Fremont Micro Devices FT32F0xxx8 RM

{~HSICAL[8],HSICAL[7:0]}+(HSITRIM[4:0]-5’h10) <=9’h1ff or >=9’h000, otherwise the calibration is not


correct.

The formula of HSI14 calibration is:


Calibration value ={~HSI14CAL[7],HSI14CAL[6:0]}+(HSI14TRIM[4:0]-5’h10), HSI14CAL[7:0] is
HSI14TRIM[4:0] default value

HSI14 calibrated range is 8’h00~8’hFF, 8’h00~8’h7F is calibrated to small value. 8’h81~8’hFF is calibrate to
big value. 9’h100 is not calibrated.

User calibrate HSI14 by writing to the HSI14TRIM[4:0] should meet


{~HSI14CAL[8],HSI14CAL[7:0]}+(HSI14TRIM[4:0]-5’h10) <=9’h1ff or >=9’h000, otherwise the calibration is
not correct.

7.2.9. System clock selection

Various clock sources can be used to drive the system clock (SYSCLK):
1. HSI
2. HSI14
3. HSE
4. HSI48
5. PLL

After a system reset, the HSI oscillator is selected as system clock. When a clock source is used directly as
a system clock, it is not possible to stop it.A switch from one clock source to another occurs only if the target
clock source is ready. SWS[1:0] bits in the RCC_CFGR register and SWS[2] bit in the RCC_CFGR4 register
indicate which clock is currently used as a system clock.

7.2.10. Clock security system(CSS)

Clock Security System can be activated by software. In this case, the clock detector is enabled after the
HSE oscillator startup delay, and disabled when this oscillator is stopped.

If a failure is detected on the HSE clock, the HSE oscillator is automatically disabled, a clock failure event is
sent to the break input of the advanced-control timers (TIM1) and general- purpose timers (TIM15, TIM16
and TIM17) and an interrupt is generated to inform the software about the failure), allowing the MCU to
perform rescue operations. In the NMI ISR user must clear the CSS interrupt by setting the CSSC bit in the
RCC_CIR

If the HSE oscillator is used directly or indirectly as the system clock (indirectly means: it is used as PLL
input clock, and the PLL clock is used as system clock), a detected failure causes a switch of the system
clock to the HSI oscillator and the disabling of the HSE oscillator. If the HSE clock (divided or not) is the clock

Rev1.3 69 2024-03-22
Fremont Micro Devices FT32F0xxx8 RM

entry of the PLL used as system clock when the failure occurs, the PLL is disabled too.

7.2.11. RTC clock

The RTC clock source can be either the HSE/32, LSE or LSI clocks. This is selected by programming the
RTCSEL[1:0] bits in the RCC_BDCR register. This selection cannot be modified without resetting the RTC
___domain. The system must be always configured in a way that the PCLK frequency is greater then or equal to
the RTC clock.

7.2.12. Independent watchdog clock

If the Independent watchdog (IWDG) is started by either hardware option or software access, the LSI
oscillator is forced ON and cannot be disabled.

7.2.13. Clock-out capability(MCO)

The microcontroller clock output (MCO) capability allows the clock to be output onto the external MCO pin.
One of the following clock signals can be selected as the MCO clock:
1. HSI
2. HSI14
3. SYSCLK
4. HSE
5. PLL clock divided by 2 or direct
6. LSE
7. LSI
8. HSI48
The selection is controlled by the MCO[3:0] bits of the RCC_CFGR. The MCO frequency can be reduced by
a configurable binary divider, controlled by the MCOPRE[2:0] bits.

7.2.14. Internal/external clock measurement

It is possible to indirectly measure the frequency of all on-board clock sources by mean of the TIM14
channel 1 input capture. The input capture channel of the Timer 14 can be a GPIO line or an internal clock of
the MCU. This selection is performed through the TI1_RMP [1:0] bits in the TIM14_OR register.

7.2.15. Low-power modes

Sleep mode stops the CPU clock. The memory interface clocks (Flash and SRAM interfaces) can be stopped
by software during sleep mode. The AHB to APB bridge clocks are disabled by hardware during Sleep mode
when all the clocks of the peripherals connected to them are disabled.

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Fremont Micro Devices FT32F0xxx8 RM

Stop mode stops all the clocks in the core supply ___domain and disables the PLL and the HSI, HSI48 and HSE
oscillators. Standby mode stops all the clocks in the core supply ___domain and disables the PLL and the HSI,
HSI48, HSI14 and HSE oscillators. The Stop and Standby mode can be overridden for debugging by setting
the DBG_STOP or DBG_STANDBY bits in the DBGMCU_CR register.

When waking up from deepsleep after an interrupt (Stop mode) or reset (Standby mode), the HSI oscillator
is selected as system clock.
If a Flash programming operation is on going, deepsleep mode entry is delayed until the Flash interface
access is finished. If an access to the APB ___domain is ongoing, deepsleep mode entry is delayed until the
APB access is finished.

Rev1.3 71 2024-03-22
0x34
0x30
0x28
0x24
0x20
0x18
0x14
0x10
0x08
0x04
0x00

0x2C
0x1C
0x0C
offset

Rev1.3
Reset
Reset
Reset
Reset
Reset
Reset
Reset
Reset
Reset
Reset
Reset
Reset
Reset
Reset
Register

RCC_CR

RCC_CIR

RCC_CR2
RCC_CSR
RCC_BDCR
RCC_CFGR

RCC_CFGR3
RCC_CFGR2
RCC_AHBENR
RCC_APB2RSTR

RCC_APB1ENR
RCC_APB2ENR

RCC_AHBRSTR
RCC_APB1RSTR

x
x
x
x
x
x
x
x
x
x
x
x
31

0
- - - LPWRSTF - - - - - - - PLL NODIV -
Fremont Micro Devices

x
x
x
x
x
x
x
x
x
x
x
x

0
- - - WWDGRSTF - - - - - - - - 30

x
x
x
x
x
x
x
x
x
x
x
x

0
- - - IWDGRSTF - - - - - - - - 29

x
x
x
x
x
x
x
x
x
x

0
0
0
- - - SFTRSTF - PWREN - - PWRRST - - MCOPRE[2:0] - 28

x
x
x
x
x
x
x
x
x
x

27

0
0
0
- - - PORRSTF - CRSEN - - CRSRST - - -

x
x
x
x
x
x
x
x
x
x
x
x

26
0
- - - PINRSTF - - - - - - - -

HSI48CAL[8:0]
7.3. RCC register map

x
x
x
x
x
x
x
x
x
x
x
25
0
0

- - - OBLRSTF - - - - - - - PLLRDY
MCO[3:0]

x
x
x
x
x
x
x
x
x
x
24

0
0
0

- - TSCRST RMVF - - - TSCEN - - - PLLON

x
x
x
x
x
x
x
x
x
x

23

0
0
0
- - - V18PWRRSTF - USBEN - - USBRST - CSSC - -

x
x
x
x
x
x

22

0
0
0
0
0
0
0
- - - IOPFRST - - I2C2EN DBGMCUEN IOPFEN I2C2RST DBGMCURST HSI48RDYC - -

x
x
x
x
x
x
x
x

21

0
0
0
0
0

- - - - - - I2C1EN - - I2C1RST - HSI4RDYC -

x
x
x
x
x
x
x
x
x

20

0
0
0
0

- - - IOPDRSF - - - - IOPDEN - - PLLRDYC -

x
x
x
x
x
x
x
x
19

0
0
0
0
0

- - - IOPCREF - - - - IOPCEN - - HSERDYC CSSON

72
PLLMUL[3:0]

x
x
x
x
x
x

0
0
0
0
0
0
0

- - - IOPBREF - - - TIM17EN IOPBEN - TIM17RST HSIRDYC HSEBYP 18

x
x
x

0
0
0
0
0
0
0
0
0
0

HSI48RDY - - IOPAREF - - USART2EN TIM16EN IOPAEN USART2RST TIM16RST LSERDYC PLLXTPRE HSERDY 17

x
x
x
x
x
x
16

0
0
0
0
0
0
0

HSI48ON - - - - BDRST - TIM15EN - - TIM15RST LSIRDYC PLLSRC[1] HSEON

x
x
x
x
x
x
x
x
x
x

15

0
0
0

- - - - RTCEN - - - - - - PLLSRC[0]

x
x
x
x
x
14

0
0
0
0
0
0
0
0

- - - - RTCPD SPI2EN USART1EN - SPI2RST USART1RST HSI48RDYIE ADC PRE

x
x
x
x
x
x
x
x
x
x

13

0
0
0

- - - - RTCISO - - - - - HSI4RDYIE -

x
x
x
x
x
x
x
x
x

12

0
0
0
0

- - - - - - SPIEN - - SPI1RST PLLRDYIE -

x
x
x
x
x
x
x

11

0
0
0
0
0
0

- - - - - WWDGEN TIM1EN - WWDGRST TIM1RST HSERDYIE -


HSICAL[7:0]

HSI14CAL[7:0]

x
x
x
x
x
x
x
x
x
x

10
0
0
0

- - - - - - - - - - HSIRDYIE

x
x
x
x
x
x
x

0
0
0
0
0
0

- - - - - ADCNE - - ADCRST LSERDYIE

[1:0]
PPRE[2:0]

x
x
x
x
x
x

0
0
0
0
0
0
0

ADCSW - - - TIM14EN - - TIM14RST - LSIRDYIE

RTCSEL

x
x
x
x
x
x
x
x

1
0
0
0
1

USBSW - - - - - - - - - CSSF

x
x
x
x
x
x
x
x

0
0
0
0
0

- - - - - - - CRCEN - - HSI48RDYF

x
x
x
x
x
x
x
x

0
0
0
0
0

- - - - - - - - - HSI14RDYF
HPRE[3:0]

x
x
x
x
x

0
0
1
0
0
0
0
0

I2C1SW - - - TIM6EN - - TIM6RST - PLLRDYF


HSITRIM[4:0]

[2:0]

HSI14TRIM[4:0]
LSEDRV

x
x
x
x
x
x
x
x

0
0
0
0
0
0

- - - - - - - - HSERDYF

x
x
x
x
x
x
x
x

0
0
0
1
0
0

HSI14DIS - - - LSEBYP - - SRAMEN - - HSIRDYF - 2

x
x
x
x

0
0
0
0
0
0
0
0
0
1

HSI14RDY - LSIRDY LSERDY TIM3EN - - TIM3RST - LSERDYF HSIRDY 1

PREDIV[3:0]
x
0

0
0
0
0
0
0
0
0
0
0
0
0
1

HSI14ON - LSION LSEON - SYSCFGCOMEN DMAEN - SYSCFGRST LSIRDYF HSION

SW[1:0]
SWS[1:0] SW[1:0]

USART1
FT32F0xxx8 RM

2024-03-22
Fremont Micro Devices FT32F0xxx8 RM

HSEADD

HSEDRVEN
RCC_HSECFG HSEDRV[2:0]

-
0x38

Reset x x x x x x x x x x x x x x x x x x x x x x x x x x x 0 0 0 0 0

SWS[2]

SW[2]
RCC_CFGR4
-

-
0x3C

Reset x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 0 0

HSICAL[8]
RCC_TRIM
-

-
0x40

Reset x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x

7.3.1. RCC_CR

Address Offset:0x00
Reset value:0x0000 XX83
Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 — PLLRDY PLLON
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO RW
23:16 — CSSON HSEBYP HSERDY HSEON
Type RO-0 RO-0 RO-0 RO-0 RW RW RO RW
15:8 HSICAL[7:0]
Type RO RO RO RO RO RO RO RO
7:0 HSITRIM[4:0] — HSIRDY HSION
Type RW RW RW RW RW RO-0 RO RW

Bit Name Function


31:26 NA Reserved
25 PLLRDY PLL clock ready flag
1:PLL clock ready
0:PLL clock not ready
24 PLLON PLL enable
Set and cleared by software to enable PLL.
Cleared by hardware when entering Stop or Standby mode. This bit can not
be reset if the PLL clock is used as system clock or is selected to become
the system clock.
1: PLL ON
0: PLL OFF
23:20 NA Reserved
19 CSSON Clock security system enable
Set and cleared by software to enable the clock security system. When
CSSON is set, the clock detector is enabled by hardware when the HSE
oscillator is ready, and disabled by hardware if a HSE clock failure is
detected.

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Fremont Micro Devices FT32F0xxx8 RM

1: Clock security system enabled


0: Clock security system disabled
18 HSEBYP HSE crystal oscillator bypass
Set and cleared by software to bypass the oscillator with an external clock.
The external clock must be enabled with the HSEON bit set, to be used by
the device.
1: HSE crystal oscillator bypassed with external clock
0: HSE crystal oscillator not bypassed
17 HSERDY HSE clock ready flag
1: HSE oscillator ready
0: HSE oscillator not ready
Note: Set by hardware to indicate that the HSE oscillator is stable. This bit
needs 5 cycles of the HSE oscillator clock to fall down after HSEON reset.
16 HSEON HSE clock enable
Set and cleared by software.
Cleared by hardware to stop the HSE oscillator when entering Stop or
Standby mode. This bit cannot be reset if the HSE oscillator is used directly
or indirectly as the system clock.
1: HSE oscillator ON
0: HSE oscillator OFF
15:8 HSICAL[7:0] HSI clock calibration These bits are initialized automatically at startup. Use
with the HSICAL[8] of the RCC_TRIM
7:3 HSITRIM[4:0] HSI clock trimming
These bits provide an additional user-programmable trimming value that is
added to the HSICAL[8:0] bits. It can be programmed to adjust to variations
in voltage and temperature that influence the frequency of the HSI.
2 NA Reserved
1 HSIRDY HSI clock ready flag
1: HSI oscillator ready
0: HSI oscillator not ready
Note: After the HSION bit is cleared, HSIRDY goes low after 3 HSI oscillator
clock cycles.
0 HSION HSI clock enable
Set by hardware to force the HSI oscillator ON when leaving Stop or Standby
mode or in case of failure of the HSE crystal oscillator used directly or
indirectly as system clock. This bit cannot be reset if the HSI is used directly
or indirectly as system clock or is selected to become the system clock.
1: HSI oscillator ON
0: HSI oscillator OFF

Rev1.3 74 2024-03-22
Fremont Micro Devices FT32F0xxx8 RM

7.3.2. RCC_CFGR

Address Offset:0x04
Reset value:0x0000 0000
Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 PLLNODIV MCOPRE[2:0] MCO[3:0]
Type RW RW RW RW RW RW RW RW
23:16 — PLLMUL[3:0] PLLXTPR PLLSRC[
E 1]
Type RO-0 RO-0 RW RW RW RW RW RW
15:8 PLLSRC[0] ADCPRE — PPRE[2:0]
Type RW RW RO-0 RO-0 RO-0 RW RW RW
7:0 HPRE[3:0] SWS[1:0] SW[1:0]
Type RW RW RW RW RO RO RW RW

Bit Name Function


31 PLLNODIV PLL clock not divided for MCO
1: PLL is not divided for MCO
0: PLL is divided by 2 for MCO
30:28 MCOPRE[2:0] Microcontroller Clock Output Prescaler
These bits are set and cleared by software to select the MCO prescaler
division factor. To avoid glitches, it is highly recommended to change this
prescaler only when the MCO output is disabled.
111: MCO is divided by 128
110: MCO is divided by 64
101: MCO is divided by 32
100: MCO is divided by 16
011: MCO is divided by 8
010: MCO is divided by 4
001: MCO is divided by 2
000: MCO is divided by 1
27:24 MCO[3:0] Microcontroller clock output
1000:(HSI48)Internal RC 48 MHz (HSI48) oscillator clock selected
0111: PLL clock selected
0110:(HSE)External 4-32 MHz (HSE) oscillator clock selected
0101:(HSI)Internal RC 8 MHz (HSI) oscillator clock selected
0100:System clock selected
0011:(LSE)External low speed (LSE) oscillator clock selected
0010:(LSI)Internal low speed (LSI) oscillator clock selected
0001:(HSI14)Internal RC 14 MHz (HSI14) oscillator clock selected
0000: MCO output disabled, no clock on MCO
Note: This clock output may have some truncated cycles at startup or during

Rev1.3 75 2024-03-22
Fremont Micro Devices FT32F0xxx8 RM

MCO clock source switching.


23:22 NA Reserved
21:18 PLLMUL[3:0] PLL multiplication factor
These bits can be written only when PLL is disabled.
1111:PLL input clock×16
1110:PLL input clock×16
1101:PLL input clock×15
1100:PLL input clock×14
1011:PLL input clock×13
1010:PLL input clock×12
1001:PLL input clock×11
1000:PLL input clock×10
0111:PLL input clock×9
0110:PLL input clock×8
0101:PLL input clock×7
0100:PLL input clock×6
0011:PLL input clock×5
0010:PLL input clock×4
0001:PLL input clock×3
0000:PLL input clock×2
17 PLLXTPRE HSE divider for PLL input clock
This bit is the same bit as bit PREDIV[0] from RCC_CFGR2. Refer to
RCC_CFGR2 PREDIV bits description for its meaning.
16:15 PLLSRC[1:0] PLL input clock source These bits can be written only when PLL is disabled.
00:HSI divided by 2
01:HSI/PREDIV
10:HSE/PREDIV
11:HSI48/PREDIV
14 ADCPRE Reserved, can be written/read
13:11 NA Reserved
10:8 PPRE[2:0] PCLK prescaler
0xx:HCLK not divided
100:HCLK divided by 2
101:HCLK divided by 4
110:HCLK divided by 8
111:HCLK divided by 16
7:4 HPRE[3:0] HLCK prescaler
0xxx:SYSCLK not divided
1000:SYSCLK divided by 2
1001:SYSCLK divided by 4
1010:SYSCLK divided by 8
1011:SYSCLK divided by 16
1100:SYSCLK divided by 64

Rev1.3 76 2024-03-22
Fremont Micro Devices FT32F0xxx8 RM

1101:SYSCLK divided by 128


1110:SYSCLK divided by 256
1111:SYSCLK divided by 512
3:2 SWS[1:0] Use with SWS[2] in the RCC_CFGR4 register, indicate which clock is
currently used as a system clock
000:HSI used as system clock
001:HSE used as system clock
010:PLL used as system clock
011:HSI48 used as system clock
1xx:HSI14 used as system clock
1:0 SW[1:0] System clock switch, use with SW[2] in the RCC_CFGR4 register
Cleared by hardware when leaving Stop and Standby mode or in case of
failure of the HSE oscillator used directly or indirectly as system clock
000:HSI selected as system clock
001:HSE selected as system clock
010:PLL selected as system clock
011:HSI48 selected as system clock
1xx:HSI14 selected as system clock

7.3.3. RCC_CIR

Address Offset:0x08
Reset value:0x0000 0000
Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 CSSC HSI48RDYC HSI14RDYC PLLRDYC HSERDYC HSIRDYC LSERDYC LSIRDYC
Type WO RO-0 WO WO WO WO WO WO
15:8 — HSI48RDYIE HSI4RDYIE PLLRDYIE HSERDYIE HSIRDYIE LSERDYIE LSIRDYIE
Type RO-0 RW RW RW RW RW RW RW
7:0 CSSF — HSI14RDYF PLLRDYF HSERDYF HSIRDYF LSERDYF LSIRDYF
Type RO RO-0 RO RO RO RO RO RO

Bit Name Function


31:24 NA Reserved
23 CSSC Clock security system interrupt clear
1:Clear CSSF flag
0:No effect
22 HSI48RDYC HSI48 Ready Interrupt Clear
This bit is set by software to clear the HSI48RDYF flag
1:Clear HSI48RDYF flag
0:No effect

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Fremont Micro Devices FT32F0xxx8 RM

21 HSI4RDYC HSI14 ready interrupt clear


This bit is set by software to clear the HSI14RDYF flag
1:Clear HSI14RDYF flag
0:No effect
20 PLLRDYC PLL ready interrupt clear
This bit is set by software to clear the PLLRDYF flag.
1:Clear PLLRDYF flag
0:No effect
19 HSERDYC HSE ready interrupt clear
This bit is set by software to clear the HSERDYF flag
1:Clear HSERDYF flag
0:No effect
18 HSIRDYC HSI ready interrupt clear.
This bit is set software to clear the HSIRDYF flag.
1: Clear HSIRDYF flag
0:No effect
17 LSERDYC LSE ready interrupt clear
This bit is set by software to clear the LSERDYF flag.
1:LSERDYF cleared
0:No effect
16 LSIRDYC LSI ready interrupt clear
This bit is set by software to clear the LSIRDYF flag.
1:LSIRDYF cleared
0:No effect
15 NA Resrved
14 HSI48RDYIE HSI48 ready interrupt enable
1:HSI48 ready interrupt enabled
0:HSI48 ready interrupt disabled
13 HSI14RDYIE HSI14 ready interrupt enable
1: HSI14 ready interrupt enabled
0: HSI14 ready interrupt disabled
12 PLLRDYIE PLL ready interrupt enable
1: PLL ready interrupt enabled
0: PLL ready interrupt disabled
11 HSERDYIE HSE ready interrupt enable
1: HSE ready interrupt enabled
0:HSE ready interrupt disabled
10 HSIRDYIE HSI ready interrupt enable
1: HSI ready interrupt enabled
0: HSI ready interrupt disabled
9 LSERDYIE LSE ready interrupt enable
1: LSE ready interrupt enabled
0: LSE ready interrupt disabled

Rev1.3 78 2024-03-22
Fremont Micro Devices FT32F0xxx8 RM

8 LSIRDYIE LSI ready interrupt enable


1: LSI ready interrupt enabled
0: LSI ready interrupt disabled
7 CSSF Clock security system interrupt flag
Set by hardware when a failure is detected in the HSE oscillator. Cleared by
software setting the CSSC bit.
1: Clock security interrupt caused by HSE clock failure
0: No clock security interrupt caused by HSE clock failure
6 NA Reserved
5 HSI14RDYF HSI14 ready interrupt flag
Set by hardware when the HSI14 becomes stable, HSI14RDYIE=1 and
HSI14ON=1. When HSI14ON is not set but the HSI14 oscillator is enabled by
the peripheral through a clock request, this bit is not set and no interrupt is
generated.
1:Clock ready interrupt caused by the HSI14 oscillator
0:No clock ready interrupt caused by the HSI14 oscillator
4 PLLRDYF PLL ready interrupt flag
Set by hardware when the PLL locks and PLLRDYDIE is set.
Cleared by software setting the PLLRDYC bit.
1:Clock ready interrupt caused by PLL lock
0:No clock ready interrupt caused by PLL lock
3 HSERDYF HSE ready interrupt flag
Set by hardware when the HSE clock becomes stable and HSERDYDIE is set.
Cleared by software setting the HSERDYC bit
1:Clock ready interrupt caused by the HSE oscillator
0: No clock ready interrupt caused by the HSE oscillator
2 HSIRDYF HSI ready interrupt flag
Set by hardware when the HSI clock becomes stable and HSIRDYIE=1,
HSION=1 When HSION is not set but the HSI oscillator is enabled by the
peripheral through a clock request, this bit is not set and no interrupt is
generated.
1:Clock ready interrupt caused by the HSI oscillator
0:No clock ready interrupt caused by the HSI oscillator
1 LSERDYF LSE ready interrupt flag
Set by hardware when the LSE clock becomes stable and LSERDYIE=1
Cleared by software setting the LSERDYC bit.
1:Clock ready interrupt caused by the LSE oscillator
0:No clock ready interrupt caused by the LSE oscillator
0 LSIRDYF LSI ready interrupt flag
Set by hardware when the LSI clock becomes stable and LSIRDYIE=1
Cleared by software setting the LSIRDYC bit.
1:Clock ready interrupt caused by the LSI oscillator
0:No clock ready interrupt caused by the LSI oscillator

Rev1.3 79 2024-03-22
Fremont Micro Devices FT32F0xxx8 RM

7.3.4. RCC_APB2RSTR

Address offset:0x0C
Reset value:0x0000 0000
Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 — DBGMCU – TIM17RST TIM16RST TIM15RST
RST
Type RO-0 RW RO-0 RO-0 RO-0 RW RW RW
15:8 — USART1 — SPI1RST TIM1RST — ADCRST —
RST
Type RO-0 RW RO-0 RW RW RO-0 RW RO-0
7:0 — SYSCFG
RST
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RW

Bit Name Function


31:23 NA Reserved
22 DBGMCURST Debug MCU reset Set and cleared by software.
1:Reset Debug MCU
0:No effect
21:19 NA Reserved
18 TIM17RST TIM17 reset Set and cleared by software.
1:Reset TIM17
0:No effect
17 TIM16RST TIM16 reset Set and cleared by software.
1:Reset TIM16
0:No effect
16 TIM15RST TIM15 reset Set and cleared by software.
1:Reset TIM15
0:No effect
15 NA Reserved
14 USART1RST USART1 reset Set and cleared by software.
1:Reset USART1
0:No effect
13 NA Reserved
12 SPI1RST SPI1 reset Set and cleared by software.
1:Reset SPI1
0:No effect
11 TIM1RST TIM1 reset Set and cleared by software.
1:Reset TIM1

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Fremont Micro Devices FT32F0xxx8 RM

0:No effect
10 NA Reserved
9 ADCRST ADC reset Set and cleared by software.
1:Reset ADC
0:No effect
8:1 NA Reserved
0 SYSCFGRST SYSCFG reset Set and cleared by software.
1:Reset SYSCFG
0:No effect

7.3.5. RCC_APB1RSTR

Address offset:0x10
Reset value:0x0000 0000
Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 LEBRST — PWRRST CRSRST —
Type RW RO-0 RO-0 RW RW RO-0 RO-0 RO-0
23:16 USBRST I2C2RST I2C1RST — USART2RST —
Type RW RW RW RO-0 RO-0 RO-0 RW RO-0
15:8 — SPI2RST — WWDGRST — TIM14RST
Type RO-0 RW RO-0 RO-0 RW RO-0 RO-0 RW
7:0 — TIM6RST — TIM3RST —
Type RO-0 RO-0 RO-0 RW RO-0 RO-0 RW RO-0

Bit Name Function


31 LEBRST LEB reset, Set and cleared by software.
1:Reset LEB
0:No effect
30:29 NA Reserved
28 PWRRST PWRreset Set and cleared by software.
1:Reset PWR
0:No effect
27 CRSRST CRS reset Set and cleared by software.
1:Reset CRS
0:No effect
26:24 NA Reserved
23 USBRST USB reset Set and cleared by software.
1:Reset USB
0:No effect
22 I2C2RST I2C2 reset Set and cleared by software.
1:Reset I2C2
0:No effect

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Fremont Micro Devices FT32F0xxx8 RM

21 I2C1RST I2C1 reset Set and cleared by software.


1:Reset I2C1
0:No effect
20:18 NA Reserved
17 USART2RST USART2 reset Set and cleared by software.
1:Reset USART2
0:No effect
16:15 NA Reserved
14 SPI2RST SPI2 reset Set and cleared by software.
1:Reset SPI2
0:No effect
13:12 NA Reserved
11 WWDGRST WWDG reset Set and cleared by software.
1:Reset WWDG
0:No effect
10:9 NA Reserved
8 TIM14RST TIM14 reset Set and cleared by software.
1:Reset TIM14
0:No effect
7:5 NA Reserved
4 TIM6RST TIM6 reset Set and cleared by software.
1:Reset TIM6
0:No effect
3:2 NA Reserved
1 TIM3RST TIM3 reset Set and cleared by software.
1:Reset TIM3
0:No effect
0 NA Reserved

7.3.6. RCC_AHBENR

Address offset:0x14
Reset value:0x0000 0004
Note: When the peripheral clock is not active, the peripheral register values may not be readable by software
and the returned value is always 0x0.
Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 — TSCEN
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RW
23:16 — IOPFEN — IOPDEN IOPCEN IOPBEN IOPAEN —
Type RO-0 RW RO-0 RW RW RW RW RO-0
15:8 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0

Rev1.3 82 2024-03-22
Fremont Micro Devices FT32F0xxx8 RM

7:0 — CRCEN — FLITFEN — SRAMEN — DMAEN


Type RO-0 RW RO-0 RO-0 RO-0 RW RO-0 RW

Bit Name Function


31:25 NA Reserved
24 TSCEN Touch sensing controller clock enable
1:Touch clock enabled
0:Touch clock disabled
23 NA Reserved
22 IOPFEN GPIOF clock enable
1:GPIOF clock enabled
0:GPIOF clock disabled
21 NA Reserved
20 IOPDEN GPIOD clock enable
1:GPIOD clock enabled
0:GPIOD clock disabled
19 IOPCEN GPIOC clock enable
1:GPIOC clock enabled
0:GPIOC clock disabled
18 IOPBEN GPIOB clock enable
1:GPIOB clock enabled
0:GPIOB clock disabled
17 IOPAEN GPIOA clock enable
1:GPIOA clock enabled
0:GPIOA clock disabled
16:7 NA Reserved
6 CRCEN CRC clock enable
1:CRC clock enabled
0:CRC clock disabled
5:3 NA Reserved
2 SRAMEN SRAM clock enable
Set and cleared by software to disable/enable SRAM interface clock during
Sleep mode.
1:SRAM clock disabled during Sleep mode
0:SRAM clock enabled during Sleep mode
1 NA Reserved
0 DMAEN DMA clock enable
1:DMA clock enabled
0:DMA clock disabled

Rev1.3 83 2024-03-22
Fremont Micro Devices FT32F0xxx8 RM

7.3.7. RCC_APB2ENR

Address:0x18
Reset value:0x0000 0000
Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 — DBGMCUEN — TIM17EN TIM16EN TIM15EN
Type RO-0 RW RO-0 RO-0 RO-0 RW RW RW
15:8 — USART1EN — SPI1EN TIM1EN — ADCEN —
Type RO-0 RW RO-0 RW RW RO-0 RW RO-0
7:0 — SYSCFGEN
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RW

Bit Name Function


31:23 NA Reserved
22 DBGMCUEN MCU DEBUG clock enable
1:MCU DEBUG clock enabled
0:MCU DEBUG clock disabled
21:19 NA Reserved
18 TIM17EN TIM17 clock enable
1:TIM17 clock enabled
0:TIM17 clock disabled
17 TIM16EN TIM16 clock enable
1:TIM16 clock enabled
0:TIM16 clock disabled
16 TIM15EN TIM15 clock enable
1:TIM15 clock enabled
0:TIM15 clock disabled
15 NA Reserved
14 USART1EN USART1 clock enable
1:USART1 clock enabled
0:USART1 clock disabled
13 NA Reserved
12 SPI1EN SPI1 clock enable
1:SPI1 clock enabled
0:SPI1 clock disabled
11 TIM1EN TIM1 clock enable
1:TIM1 clock enabled
0:TIM1 clock disabled
10 NA Reserved
9 ADCEN ADC clock enable

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Fremont Micro Devices FT32F0xxx8 RM

1:ADC clock enabled


0:ADC clock disabled
8:1 NA Reserved
0 SYSCFGEN SYSCFG clock enable
1:SYSCFG clock enabled
0:SYSCFG clock disabled

7.3.8. RCC_APB1ENR

Address offset:0x1C
Reset value:0x0000 0000
Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 LEBEN — PWREN CRSEN — — —
Type RW RO-0 RO-0 RW RW RO-0 RO-0 RO-0
23:16 USBEN I2C2EN I2C1EN — USART2EN —
Type RW RW RW RO-0 RO-0 RO-0 RW RO-0
15:8 — SPI2EN — WWDGEN — TIM14EN
Type RO-0 RW RO-0 RO-0 RW RO-0 RO-0 RW
7:0 — TIM6EN — TIM3EN —
Type RO-0 RO-0 RO-0 RW RO-0 RO-0 RW RO-0

Bit Name Function


31 LEBEN LEB clock enable
1:LEB clock enabled
0:LEB clock disabled
30:29 NA Reserved
28 PWREN PWR clock enable
1:PWR clock enabled
0:PWR clock disabled
27 CRSEN CRS clock enable
1:CRS clock enabled
0:CRS clock disabled
26:24 NA Reserved
23 USBEN USB clock enable
1:USB clock enabled
0:USB clock disabled
22 I2C2EN I2C2 clock enable
1:I2C2 clock enabled
0:I2C2 clock disabled
21 I2C1EN I2C1 clock enable
1:I2C1 clock enabled
0:I2C1 clock disabled

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Fremont Micro Devices FT32F0xxx8 RM

20:18 NA Reserved
17 USART2EN USART2 clock enable
1:USART2 clock enabled
0:USART2 clock disabled
16:15 NA Reserved
14 SPI2EN SPI2 clock enable
1:SPI2 clock enabled
0:SPI2 clock disabled
13:12 NA Reserved
11 WWDGEN WWDG clock enable
1:WWDG clock enabled
0: WWDG clock disabled
10:9 NA Reserved
8 TIM14EN TIM14 clock enable
1:TIM14 clock enable
0:TIM14 clock disabled
7:5 NA Reserved
4 TIM6EN TIM6 clock enable
1:TIM6 clock enable
0:TIM6 clock disabled
3:2 NA Reserved
1 TIM3EN TIM3 clock enable
1:TIM3 clock enable
0:TIM3 clock disabled
0 NA Reserved

7.3.9. RCC_BDCR

Address offset:0x20
Reset value:0x0000 0010
Note: The LSEON, LSEBYP, RTCSEL and RTCEN bits are in the RTC ___domain. As a result, after Reset, these
bits are write-protected and the DBP bit in the PWR_CR register has to be set before these can be modified.
Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 — BDRST
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RW
15:8 RTCEN RTCPD RTCISO — RTCSEL[1:0]
Type RW RW RO RO-0 RO-0 RO-0 RW RW
7:0 — LSEDRV[2:0] LSEBYP LSERDY LSEON
Type RO-0 RO-0 RW RW RW RW RO RW

Rev1.3 86 2024-03-22
Fremont Micro Devices FT32F0xxx8 RM

Bit Name Function


31:17 NA Reserved
16 BDRST RTC ___domain software reset,Set and cleared by software
1:Resets the entire RTC ___domain (include RCC_BDCR register)
0:Reset not activated
15 RTCEN RTC clock enable
1:RTC clock enabled
0:RTC clock disabled
14 RTCPD RTC ___domain power control
1:RTC ___domain power off
0:RTC ___domain power on
13 RTCISO RTC ___domain isolation flag
1:RTC ___domain is isolated, its register cannot be accessd
0:RTC ___domain is not isolated, its register can be accessd
12:10 NA Reserved
9:8 RTCSEL[1:0] RTC clock source selection
These bits can be write only when RTCSEL[1:0]=2’b00 or after BDRST reset
00:No clock
01:LSE oscillator clock used as RTC clock
10:LSI oscillator clock used as RTC clock
11:HSE oscillator clock divided by 32 used as RTC clock
7:6 NA Reserved
5:3 LSEDRV[2:0] LSE oscillator drive capability
000: lower driving capability
001:medium low driving capability
010:medium high driving capability
011:higher driving capability (reset value)
1xx:maximum driving capability (reset value)
2 LSEBYP LSE oscillator bypass
1:LSE oscillator bypassed
0:LSE oscillator not bypassed
1 LSERDY LSE oscillator ready
1:LSE oscillator ready
0:LSE oscillator not ready
Note: After the LSEON bit is cleared, LSERDY goes low after 4 external
low-speed oscillator clock cycles.
0 LSEON LSE oscillator enable
1:LSE oscillator ON
0:LSE oscillator OFF

Rev1.3 87 2024-03-22
Fremont Micro Devices FT32F0xxx8 RM

7.3.10. RCC_CSR

Address offset:0x24
Reset value:0x0880 0000
Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 LPWRRSTF WWDGRSTF IWDGRSTF SFTRSTF PORRSTF PINRSTF OBLRSTF RMVF
Type RO RO RO RO RO RO RO WO
23:16 VDDLRSTF —
Type RO RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
7:0 — LSIRDY LSION
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO RW
Note: Reset by system Reset, except reset flags by power Reset only

Bit Name Function


31 LPWRRSTF Low-power reset flag,Set by hardware when a Low-power management
reset occurs. Cleared by writing to the RMVF bit.
1:Low-power management reset occurred
0:No Low-power management reset occurred
30 WWDGRSTF Window watchdog reset flag,Set by hardware when a window watchdog
reset occurs. Cleared by writing to the RMVF bit.
1:Window watchdog reset occurred
0:No window watchdog reset occurred
29 IWDGRSTF Independent watchdog reset flag,Set by hardware when an independent
watchdog reset from VDD ___domain occurs. Cleared by writing to the RMVF
bit.
1:Watchdog reset occurred
0:No watchdog reset occurred
28 SFTRSTF Software reset flag,Set by hardware when a software reset occurs. Cleared
by writing to the RMVF bit.
1:Software reset occurred
0:No software reset occurred
27 PORRSTF POR/PDR reset flag,Set by hardware when a POR/PDR reset occurs.
Cleared by writing to the RMVF bit.
1:POR/PDR reset occurred
0:No POR/PDR reset occurred
26 PINRSTF PIN reset flag,NSet by hardware when a reset from the NRST pin occurs.
Cleared by writing to the RMVF bit.
1:Reset from NRST pin occurred
0:No reset from NRST pin occurred
25 OBLRSTF Option byte loader reset flag,Set by hardware when a reset from the OBL

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Fremont Micro Devices FT32F0xxx8 RM

occurs. Cleared by writing to the RMVF bit.


1:Reset from OBL occurred
0:No reset from OBL occurred
24 RMVF Remove reset flag
0:No effect
1:Clear the reset flags
23 VDDLRSTF Reset flag of the VDDL(1.6) V ___domain. Set by hardware when a POR/PDR
of the 1.6 V ___domain occurred. Cleared by writing to the RMVF bit.
1:POR/PDR reset of the VDDL ___domain occurred
0:No POR/PDR reset of the VDDL ___domain occurred
22:2 NA Resrved
1 LSIRDY LSI oscillator ready
1:LSI oscillator ready
0:LSI oscillator not ready
Note: After the LSION bit is cleared, LSIRDY goes low after 3 LSI oscillator
clock cycles.
0 LSION LSI oscillator enable
1:LSI oscillator ON
0: LSI oscillator OFF
Note: Set by hardware when a system reset occurs or exit standby mode.

Rev1.3 89 2024-03-22
Fremont Micro Devices FT32F0xxx8 RM

7.3.11. RCC_AHBRSTR

Address offset:0x28
Reset value:0x0000 0000
Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 — TSCRST
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RW
23:16 — IOPFRST — IOPDRST IOPCRST IOPBRST IOPARST —
Type RO-0 RW RO-0 RW RW RW RW RO-0
15:8 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
7:0 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0

Bit Name Function


31:25 NA Reserved
24 TSCRST Touch sensing controller reset. Set and cleared by software
1:Reset Touch sensing controller
0:No effect
23 NA Reserved
22 IOPFRST GPIOF reset. Set and cleared by software
1:Reset GPIOF
0:No effect
21 NA Reserved
20 IOPDRST GPIOD reset. Set and cleared by software
1:Reset GPIOD
0:No effect
19 IOPCRST GPIOC reset. Set and cleared by software
1:Reset GPIOC
0:No effect
18 IOPBRST GPIOB reset. Set and cleared by software
1:Reset GPIOB
0:No effect
17 IOPARST GPIOA reset. Set and cleared by software
1:Reset GPIOA
0:No effect
16:0 NA Reserved

Rev1.3 90 2024-03-22
Fremont Micro Devices FT32F0xxx8 RM

7.3.12. RCC_CFGR2

Address offset:0x2C
Reset value:0x0000 0000
Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
7:0 — PREDIV[3:0]
Type RO-0 RO-0 RO-0 RO-0 RW RW RW RW

Bit Name Function


31:4 NA Reserved
3:0 PREDIV[3:0] PLL division factor. These bits can be written only when the PLL is disabled.
Note: Modifying PLLXTPRE in the RCC_CFGR register also modified
PREDIV[0]
0000:PLL input clock not divided
0001:PLL input clock divided by 2
0010:PLL input clock divided by 3
0011:PLL input clock divided by 4
0100:PLL input clock divided by 5
0101:PLL input clock divided by 6
0110:PLL input clock divided by 7
0111:PLL input clock divided by 8
1000:PLL input clock divided by 9
1001:PLL input clock divided by 10
1010:PLL input clock divided by 11
1011:PLL input clock divided by 12
1100:PLL input clock divided by 13
1101:PLL input clock divided by 14
1110:PLL input clock divided by 15
1111:PLL input clock divided by 16

Rev1.3 91 2024-03-22
Fremont Micro Devices FT32F0xxx8 RM

7.3.13. RCC_CFGR3

Address offset:0x30
Reset value:0x0000 0000
Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 — ADCSW
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RW
7:0 USBSW — I2C1SW — USART1SW[1:0]
Type RW RO-0 RO-0 RW RO-0 RO-0 RW RW

Bit Name Function


31:9 NA Reserved
8 ADCSW Reserved
7 USBSW USB clock source selection
1: PLL clock selected as USB clock
0:HSI48 as USB clock
6:5 NA Reserved
4 I2C1SW I2C1 clock source selection
1:System clock (SYSCLK) selected as I2C1 clock
0:HSI clock selected as I2C1 clock source
3:2 NA Reserved
1:0 USART1SW[1:0] USART1 clock source selection
11:HSI clock selected as USART1 clock
10:LSE clock selected as USART1 clock
01:System clock (SYSCLK) selected as USART1 clock
00:PCLK selected as USART1 clock source

7.3.14. RCC_CR2

Address offset:0x34
Reset value:0xXXX0 XX80
Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 HSI48CAL[8:1]
Type RO RO RO RO RO RO RO RO
23:16 HSI48CAL[0] — HSI48RDY HSI48ON
Type RO RO-0 RO-0 RO-0 RO-0 RO-0 RO RW

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15:8 HSI14CAL[7:0]
Type RO RO RO RO RO RO RO RO
7:0 HSI14TRIM[4:0] HSI14DIS HSI14RDY HSI14ON
Type RW RW RW RW RW RW RO RW

Bit Name Function


31:23 HSI48CAL[8:0] HSI48 clock calibration
These bits are initialized automatically at startup
22:18 NA Reserved
17 HSI48RDY HSI48 clock ready flag
1:HSI48 oscillator ready
0:HSI48 oscillator not ready
Note: After the HSI48ON bit is cleared, HSI48RDY goes low after 3 HCLK
clock cycles.
16 HSI48ON HSI48 clock enable
1:HSI48 oscillator ON
0:HSI48 oscillator OFF
15:8 HSI14CAL[7:0] HSI14 clock calibration
These bits are initialized automatically at startup
7:3 HSI14TRIM[4:0] HSI14 clock trimming
These bits provide an additional user-programmable trimming value that is
added to the HSI14CAL[7:0] bits. It can be programmed to adjust to
variations in voltage and temperature that influence the frequency of the
HSI14.
2 HSI14DIS HSI14 clock request from ADC disable
1:ADC interface can not turn on the HSI14 oscillator
0:ADC interface can turn on the HSI14 oscillator
1 HSI14RDY HSI14 clock ready flag
1:HSI14 oscillator ready
0:HSI14 oscillator not ready
Note: After the HSI14ON bit is cleared, HSI14RDY goes low after 3 HCLK
clock cycles.
0 HSI14ON HSI14 clock enable
1:HSI14 oscillator ON
0:HSI14 oscillator OFF

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7.3.15. RCC_HSECFG

Address offset:0x38
Reset value:0x0000 0000

Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0


31:24 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
7:0 — HSEADD HSEDRV[2:0] HSEDRVEN
Type RO-0 RO-0 RO-0 RW RW RW RW RW

Bit Name Function


31:5 NA Reserved
4 HSEADD HSE drive current increase control
1:HSE drive current increase
0:HSE drive current not change
3:1 HSEDRV[2:0] HSE drive ability
These bits can only be modified when HSEDRVEN = 0
111:Strong HSE drive ability
….
000:Weak HSE drive ability
0 HSEDRVEN HSE drive ability adjustment control bit
1: Controlled by HSEDRV[2:0]
0: Controlled by the chip automatic adjustment

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7.3.16. RCC_CFGR4

Address offset:0x3C
Reset value:0x0000 0000
Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
7:0 — SWS[2] SW[2]
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO RW

Bit Name Function


31:2 NA Reserved
1 SWS[2] Indicate which clock is currently used as a system clock, Refer to SWS[1:0]
in the RCC_CFGR register
0 SW[2] System clock switch, Refer to SW[1:0] in the RCC_CFGR register

7.3.17. RCC_TRIM

Address offset:0x40
Reset value:0x0000 000X
Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
7:0 — HSICAL[8]
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RW

Bit Name Function


31:1 NA Reserved
0 HSICAL[8] HSI clock calibration. Refer to HSICAL[7:0] bits in the RCC_CR register

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8. Clock recovery system (CRS)

8.1. Introduction

The clock recovery system (CRS) is an advanced digital controller acting on the internal fine-granularity
trimmable RC oscillator HSI48. The CRS provides a powerful means for oscillator output frequency
evaluation, based on comparison with a selectable synchronization signal. It is capable of doing automatic
adjustment of oscillator trimming based on the measured frequency error value, while keeping the possibility
of a manual trimming.

8.2. CRS main features

 Selectable synchronization source with programmable prescaler and polarity:


─ External pin
─ LSE oscillator output
─ USB SOF packet reception
 Possibility to generate synchronization pulses by software
 Automatic oscillator trimming capability with no need of CPU action
 Manual control option for faster start-up convergence
 16-bit frequency error counter with automatic error value capture and reload
 Programmable limit for automatic frequency error value evaluation and status reporting
 Maskable interrupts/events:
─ Expected synchronization(ESYNC)
─ Synchronization OK(SYNCOK)
─ Synchronization warning(SYNCWARN)
─ Synchronization or trimming error(ERR)

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8.3. CRS functional description

8.3.1. CRS block diagram

CRS_SYNC
GPIO
SYNCSRC SWSYNC

OSC32_IN
SYNC divider
LSE
(/1,/2,/4,…,/128)
OSC32_OUT SYNC

USB_DP
USB FELIM
USB_DM

TRIM FEDIR FECAP

RCC
RC 48MHz 16-bit counter

RELOAD

HSI48 To SYSCLK
To PLL
To USB

Figure 8-1 CRS block diagram

8.3.2. Synchronization input

The CRS synchronization (SYNC) source, selectable through the CRS_CFGR register, can be the signal
from the external CRS_SYNC pin, the LSE clock or the USB SOF signal. For a better robustness of the

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SYNC input, a simple digital filter (2 out of 3 majority votes, sampled by the HSI48 clock) is implemented to
filter out any glitches. This source signal also has a configurable polarity and can then be divided by a
programmable binary prescaler to obtain a synchronization signal in a suitable frequency range (usually
around 1 kHz).
For more information on the CRS synchronization source configuration, refer to section 8.6.2: CRS_CFGR
It is also possible to generate a synchronization event by software, by setting the SWSYNC bit in the
CRS_CR register.

8.3.3. Frequency error evaluation

The frequency error counter is a 16-bit down/up counter which is reloaded with the RELOAD value on each
SYNC event. It starts counting down till it reaches the zero value, where the ESYNC (expected
synchronization) event is generated. Then it starts counting up to the OUTRANGE limit where it eventually
stops (if no SYNC event is received) and generates a SYNCMISS event. The OUTRANGE limit is defined
as the frequency error limit (FELIM field of the CRS_CFGR register) multiplied by 128.
When the SYNC event is detected, the actual value of the frequency error counter and its counting direction
are stored in the FECAP (frequency error capture) field and in the FEDIR (frequency error direction) bit of
the CRS_ISR register. When the SYNC event is detected during the downcounting phase (before reaching
the zero value), it means that the actual frequency is lower than the target (and so, that the TRIM value
should be incremented), while when it is detected during the upcounting phase it means that the actual
frequency is higher (and that the TRIM value should be decremented).

CRS counter value

RELOAD

ESYNC

Down Up

Frequency error counter stopped


OUTRANGE
(128 x FELIM)

WARNING LIMIT
(3 x FELIM)
TOLERANCE LIMIT
(3 x FELIM)
Trimming action： 0 +2 +1 0 -1 -2 0

CRS event： SYNCERR SYNCWARN SYNCOK SYNCWARN

SYNCMISS

Figure 8-2 CRS counter behavior

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8.3.4. Frequency error evaluation and automatic trimming

The measured frequency error is evaluated by comparing its value with a set of limits:
─ TOLERANCE LIMIT, given directly in the FELIM field of the CRS_CFGR register
─ WARNING LIMIT, defined as 3 * FELIM value
─ OUTRANGE (error limit), defined as 128 * FELIM value
The result of this comparison is used to generate the status indication and also to control the automatic
trimming which is enabled by setting the AUTOTRIMEN bit in the CRS_CR register:
 When the frequency error is below the tolerance limit, it means that the actual trimming value in the
TRIM field is the optimal one and that then, no trimming action is necessary.
─ SYNCOK status indicated
─ TRIM value not changed in AUTOTRIM mode
 When the frequency error is below the warning limit but above or equal to the tolerance limit, it means
that some trimming action is necessary but that adjustment by one trimming step is enough to reach the
optimal TRIM value.
─ SYNCOK status indicated
─ TRIM value adjusted by one trimming step in AUTOTRIM mode
 When the frequency error is above or equal to the warning limit but below the error limit, it means that a
stronger trimming action is necessary, and there is a risk that the optimal TRIM value will not be
reached for the next period.
─ SYNCWARN status indicated
─ TRIM value adjusted by two trimming steps in AUTOTRIM mode
 When the frequency error is above or equal to the error limit, it means that the frequency is out of the
trimming range. This can also happen when the SYNC input is not clean or when some SYNC pulse is
missing (for example when one USB SOF is corrupted).
─ SYNCERR or SYNCMISS status indicated
─ TRIM value not changed in AUTOTRIM mode
Note: If the actual value of the TRIM field is so close to its limits that the automatic trimming would force it to
overflow or underflow, then the TRIM value is set just to the limit and the TRIMOVF status is indicated.
In AUTOTRIM mode (AUTOTRIMEN bit set in the CRS_CR register), the TRIM field of CRS_CR is adjusted
by hardware and is read-only.

8.3.5. CRS initialization and configuration

RELOAD value
The RELOAD value should be selected according to the ratio between the target frequency and the
frequency of the synchronization source after prescaling. It is then decreased by one in order to reach the
expected synchronization on the zero value. The formula is the following:
RELOAD = (fTARGET / fSYNC) - 1
The reset value of the RELOAD field corresponds to a target frequency of 48 MHz and a synchronization
signal frequency of 1 kHz (SOF signal from USB).
FELIM value

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The selection of the FELIM value is closely coupled with the HSI48 oscillator characteristics and its typical
trimming step size. The optimal value corresponds to half of the trimming step size, expressed as a number
of HSI48 oscillator clock ticks. The following formula can be used:
FELIM = (fTARGET / fSYNC) * STEP[%] / 100% / 2
The result should be always rounded up to the nearest integer value in order to obtain the best trimming
response. If frequent trimming actions are not wanted in the application, the trimming hysteresis can be
increased by increasing slightly the FELIM value.
The reset value of the FELIM field corresponds to (fTARGET / fSYNC) = 48000 and to a typical trimming step
size of 0.14%.
Note: There is no hardware protection from a wrong configuration of the RELOAD and FELIM fields which
can lead to an erratic trimming response. The expected operational mode requires proper setup of the
RELOAD value (according to the synchronization source frequency), which is also greater than 128 * FELIM
value (OUTRANGE limit).

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8.4. CRS low-power modes

Table 8-1 Effect of low-power modes on CRS


Mode Description
No effect
Sleep
CRS interrupts cause the device to exit the Sleep mode.
Stop CRS registers are frozen.
The CRS stops operating until the Stop or Standby mode is exited and the HSI48 oscillator
Standby
restarted.

8.5. CRS interrupts

Table 8-2 Interrupt control bits


Enable control
Interrupt event Event flag Clear flag bit
bit
Expected synchronization ESYNCF ESYNCIE ESYNCC
Synchronization OK SYNCOKF SYNCOKIE SYNCOKC
Synchronization warning SYNCWARNF SYNCWARNIE SYNCWARNC
Synchronization or trimming error
ERRF ERRIE ERRC
(TRIMOVF,SYNCMISS,SYNCERR)

8.6. CRS register map


AUTOTRIMEN

SYNCWARNIE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10

Offset Register
9
8
SWSYNC 7
6
5
4
ESYNCIE 3
2
1
SYNCOKIE0
ERRIE
CEN

CRS_CR TRIM[5:0]
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–

0x00

Reset x x x x x x x x x x x x x x x x x x 1 0 0 0 0 0 0 0 0 x 0 0 0 0
SYNCSRC
SYNCPOL

SYNC
[1:0]

DIV FELIM[7:0] RELOAD[15:0]


–

CRS_CFGR
0x04
[2:0]

Reset 0 x 1 0 x 0 0 0 0 0 1 0 0 0 1 0 1 0 1 1 1 0 1 1 0 1 1 1 1 1 1 1
SYNCWARNF
SYNCMISS
SYNCERR

SYNCOKF
TRIMOVF

ESYNCF
FEDIR

ERRF

CRS_ISR FECAP[15:0]
–
–
–
–

–
–
–
–

0x08

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x 0 0 0 x x x x 0 0 0 0
SYNCWARNC
SYNCOKC
ESYNCC
ERRC

CRS_ICR
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–

0x0C

Reset x x x x x x x x x x x x x x x x x x x x x x x x x x x x 0 0 0 0

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8.6.1. CRS_CR

Address offset:0x00
Reset value:0x0000 2000

Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0


31:24 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 — TRIM[5:0]
Type RO-0 RO-0 RW RW RW RW RW RW
AUTOTRI SYNCWA SYNCOKI
7:0 SWSYNC CEN — ESYNCIE ERRIE
MEN RNIE E
Type RT_W RW RW RO-0 RW RW RW RW

Bit Name Function


31:14 NA Reserved
13:8 TRIM[5:0] HSI48 oscillator smooth trimming
These bits provide a user-programmable trimming value to the HSI48
oscillator. They can be programmed to adjust to variations in voltage and
temperature that influence the frequency of the HSI48.
The default value is 32, which corresponds to the middle of the trimming
interval. The trimming step is around 67 kHz between two consecutive TRIM
steps. A higher TRIM value corresponds to a higher output frequency.
When the AUTOTRIMEN bit is set, this field is controlled by hardware and is
read-only.
7 SWSYNC Generate software SYNC event
This bit is set by software in order to generate a software SYNC event. It is
automatically cleared by hardware.
0:No action
1:A software SYNC event is generated.
6 AUTOTRIMEN Automatic trimming enable
This bit enables the automatic hardware adjustment of TRIM bits according
to the measured frequency error between two SYNC events. If this bit is set,
the TRIM bits are read-only. The TRIM value can be adjusted by hardware by
one or two steps at a time, depending on the measured frequency error
value. Refer to section 8.3.4 for more details.
0:Automatic trimming disabled, TRIM bits can be adjusted by the user.
1:Automatic trimming enabled, TRIM bits are read-only and under hardware
control.
5 CEN Frequency error counter enable

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This bit enables the oscillator clock for the frequency error
0:Frequency error counter disabled
1:Frequency error counter enabled
When this bit is set, the CRS_CFGR register is write-protected and cannot
be modified.
4 NA Reserved
3 ESYNCIE Expected SYNC interrupt enable
0:Expected SYNC (ESYNCF) interrupt disabled
1:Expected SYNC (ESYNCF) interrupt enabled
2 ERRIE Synchronization or trimming error interrupt enable
0:Synchronization or trimming error (ERRF) interrupt disabled
1:Synchronization or trimming error (ERRF) interrupt enabled
1 SYNCWARNIE SYNC warning interrupt enable
0:SYNC warning (SYNCWARNF) interrupt disabled
1:SYNC warning (SYNCWARNF) interrupt enabled
0 SYNCOKIE SYNC event OK interrupt enable
0:SYNC warning (SYNCWARNF) interrupt disabled
1:SYNC warning (SYNCWARNF) interrupt enabled

8.6.2. CRS_CFGR

Address offset:0x04
Reset value:0x2022 BB7F
This register can be written only when the frequency error counter is disabled (CEN bit is cleared in
CRS_CR). When the counter is enabled, this register is write-protected.

Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0


31:24 SYNCPOL — SYNCSRC[1:0] — SYNCDIV[2:0]
Type RW RO-0 RW RW RO-0 RW RW RW
23:16 FELIM[7:0]
Type RW RW RW RW RW RW RW RW
15:8 RELOAD[15:8]
Type RW RW RW RW RW RW RW RW
7:0 RELOAD[7:0]
Type RW RW RW RW RW RW RW RW

Bit Name Function


31 SYNCPOL SYNC polarity selection
This bit is set and cleared by software to select the input polarity for the
SYNC signal source
0:SYNC active on rising edge (default)

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1:SYNC active on falling edge


30 NA Resrved
29:28 SYNCSRC[1:0] SYNC signal source selection
These bits are set and cleared by software to select the SYNC signal source
00:GPIO selected as SYNC signal source
01:LSE selected as SYNC signal source
10:USB SOF selected as SYNC signal source (default)
11:Reserved
Note: When using USB LPM (Link Power Management) and the device is in
Sleep mode, the periodic USB SOF will not be generated by the host. No
SYNC signal will therefore be provided to the CRS to calibrate the HSI48 on
the run. To guarantee the required clock precision after waking up from
Sleep mode, the LSE or reference clock on the GPIOs should be used as
SYNC signal.
27 NA Reserved
26:24 SYNCDIV[2:0] SYNC divider
These bits are set and cleared by software to control the division factor of
the SYNC signal.
000:SYNC not divided (default)
001:SYNC divided by 2
010:SYNC divided by 4
011:SYNC divided by 8
100:SYNC divided by 16
101:SYNC divided by 32
110:SYNC divided by 64
111:SYNC divided by 128
23:16 FELIM[7:0] Frequency error limit
FELIM contains the value to be used to evaluate the captured frequency
error value latched in the FECAP[15:0] bits of the CRS_ISR register. Refer
to FELIM section 8.3.4 for more details about FECAP evaluation.
15:0 RELOAD[15:0] Counter reload value
RELOAD is the value to be loaded in the frequency error counter with each
SYNC event. Refer to section 8.3.3 for more details about counter behavior.

8.6.3. CRS_ISR

Address offset:0x08
Reset value:0x0000 0000

Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0


31:24 FECAP[15:8]
Type RO RO RO RO RO RO RO RO

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23:16 FECAP[7:0]
Type RO RO RO RO RO RO RO RO
15:8 FEDIR — TRIMOVF SYNCMISS SYNCERR
Type RO RO-0 RO-0 RO-0 RO-0 RO RO RO
7:0 — ESYNCF ERRF SYNCWAR SYNCOKF
NF
Type RO-0 RO-0 RO-0 RO-0 RO RO RO RO

Bit Name Function


31:16 FECAP[15:0] Frequency error capture
FECAP is the frequency error counter value latched in the time of the last
SYNC event. Refer to section 7.3.4 for more details about FECAP usage
15 FEDIR Frequency error direction
FEDIR is the counting direction of the frequency error counter latched in the
time of the last SYNC event. It shows whether the actual frequency is below
or above the target.
0:Upcounting direction, the actual frequency is above the target.
1:Downcounting direction, the actual frequency is below the target.
14:11 NA Reserved
10 TRIMOVF Trimming overflow or underflow
This flag is set by hardware when the automatic trimming tries to over- or
under-flow the TRIM value. An interrupt is generated if the ERRIE bit is set in
the CRS_CR register. It is cleared by software by setting the ERRC bit in the
CRS_ICR register.
0:No trimming error
1:Trimming error signalized
9 SYNCMISS SYNC missed
This flag is set by hardware when the frequency error counter reached value
FELIM * 128 and no SYNC was detected, meaning either that a SYNC pulse
was missed or that the frequency error is too big (internal frequency too
high) to be compensated by adjusting the TRIM value, and that some other
action should be taken. At this point, the frequency error counter is stopped
(waiting for a next SYNC) and an interrupt is generated if the ERRIE bit is set
in the CRS_CR register. It is cleared by software by setting the ERRC bit in
the CRS_ICR register.
0:No SYNC missed error
1:SYNC missed error
8 SYNCERR SYNC error
This flag is set by hardware when the SYNC pulse arrives before the ESYNC
event and the measured frequency error is greater than or equal to FELIM *
128. This means that the frequency error is too big (internal frequency too
low) to be compensated by adjusting the TRIM value, and that some other
action should be taken. An interrupt is generated if the ERRIE bit is set in the

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CRS_CR register. It is cleared by software by setting the ERRC bit in the


CRS_ICR register.
0:No SYNC error
1:SYNC error
7:4 NA Reserved
3 ESYNCF Expected SYNC flag
This flag is set by hardware when the frequency error counter reached a
zero value. An interrupt is generated if the ESYNCIE bit is set in the
CRS_CR register. It is cleared by software by setting the ESYNCC bit in the
CRS_ICR register.
0:No expected SYNC
1:Expected SYNC
2 ERRF Error flag
This flag is set by hardware in case of any synchronization or trimming error.
It is the logical OR of the TRIMOVF, SYNCMISS and SYNCERR bits. An
interrupt is generated if the ERRIE bit is set in the CRS_CR register. It is
cleared by software in reaction to setting the ERRC bit in the CRS_ICR
register, which clears the TRIMOVF, SYNCMISS and SYNCERR bits.
0:No synchronization or trimming error
1:Synchronization or trimming error signalized
1 SYNCWARNF SYNC warning flag
This flag is set by hardware when the measured frequency error is greater
than or equal to FELIM * 3, but smaller than FELIM * 128. This means that to
compensate the frequency error, the TRIM value must be adjusted by two
steps or more. An interrupt is generated if the SYNCWARNIE bit is set in the
CRS_CR register. It is cleared by software by setting the SYNCWARNC bit
in the CRS_ICR register.
0:No SYNC warning
1:SYNC warning signalized
0 SYNCOKF SYNC event OK flag
This flag is set by hardware when the measured frequency error is smaller
than FELIM * 3. This means that either no adjustment of the TRIM value is
needed or that an adjustment by one trimming step is enough to
compensate the frequency error. An interrupt is generated if the SYNCOKIE
bit is set in the CRS_CR register. It is cleared by software by setting the
SYNCOKC bit in the CRS_ICR register.
0:No SYNC event OK
1:SYNC event OK signalized

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8.6.4. CRS_ICR

Address offset:0x0C
Reset value:0x0000 0000

Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0


31:24 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
7:0 — ESYNCC ERRC SYNCWA SYNCOKC
RNC
Type RO-0 RO-0 RO-0 RO-0 RW RW RW RW

Bit Name Function


31:4 NA Reserved
3 ESYNCC Expected SYNC clear flag
Writing 1 to this bit clears the ESYNCF flag in the CRS_ISR register.
2 ERRC Error clear flag
Writing 1 to this bit clears TRIMOVF, SYNCMISS and SYNCERR bits and
consequently also the ERRF flag in the CRS_ISR register.
1 SYNCWARNC SYNC warning clear flag
Writing 1 to this bit clears the SYNCWARNF flag in the CRS_ISR register.
0 SYNCOKC SYNC event OK clear flag
Writing 1 to this bit clears the SYNCOKF flag in the CRS_ISR register.

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9. General-purpose I/Os (GPIO)

9.1. Introduction

GPIO have A, B, C, D, F five groups, each group has 16 I/O ports except group F and group d, group f has 6
I/O ports and group d has 1 I/O port. Each general-purpose I/O port has four 32-bit configuration registers
(GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR and GPIOx_PUPDR), two 32-bit data registers
(GPIOx_IDR and GPIOx_ODR) and a 32-bit set/reset register (GPIOx_BSRR). Ports A and B also have a
32-bit locking register (GPIOx_LCKR) and two 32-bit alternate function selection registers (GPIOx_AFRH
and GPIOx_AFRL).

9.2. GPIO main features

 Output states: push-pull or open drain + pull-up/down;


 Output data from output data register (GPIOx_ODR) or peripheral (alternate function output);
 Speed selection for each I/O;
 Input states: floating, pull-up/down, analog;
 Input data to input data register (GPIOx_IDR) or peripheral (alternate function input);
 Bit set and reset register (GPIOx_ BSRR), write GPIOx_BSRR[15:0] to 1 means set GPIOx_ODRy,
write GPIOx_BSRR[31:16] to 1 means reset GPIOx_ODRy ;
 Locking mechanism (GPIOx_LCKR) provided to freeze the port A or B I/O port configuration;
 Analog function;
 Alternate function selection registers;
 Highly flexible pin multiplexing allows the use of I/O pins as GPIOs or as one of several peripheral
functions;
 Up to 55 Digital I/Os.

9.3. GPIO functional description

Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each port bit of the
general-purpose I/O (GPIO) ports can be individually configured by software in several modes:
 Input floatin, Input pull-up, Input-pull-down;
 Analog;
 Output open-drain with pull-up or pull-down capability, output push-pull with pull-up or pull-down
capability;
 Alternate function pull-up or pull-down capability.
Each I/O port bit is freely programmable, however the I/O port registers have to be accessed as 32-bit words,
half-words or bytes. The purpose of the GPIOx_BSRR and GPIOx_BRR registers is to allow atomic
read/modify accesses to any of the GPIOx_ODR registers. In this way, there is no risk of an IRQ occurring
between the read and the modify access.

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Fremont Micro Devices FT32F0xxx8 RM

Figure 9-1 shows the basic structures of a standard I/O port bit, Table 9-1 gives the possible port bit
configurations.

To on-chip Analog input


peripherals, power
control and EXTI Digital input

Read on/off

Input data register


Bit set/reset register

VDDIOx
on/off Pull-up
Input driver
write I/O pin
Output data register

Output driver on/off Pull-down


VDDIOx
VSS
P-MOS
Output
Read/write control
N-MOS

VSS
From on-chip Alternate function output
peripheral Push-pull,
open_drain or
disabled

Figure 9-1 Basic structure of an I/O port bit

Table 9-1 Port bit configuration table


MODER(i) [1:0] OTYPER(i) OSPEEDR(i) [1:0] PUPDR(i) [1:0] I/O configuration
0 0 0 output push-pull
push-pull
0 0 1 output
+pull-up
push-pull +
0 1 0 output
pull-down
0 1 1 Reserved
01 SPEED[1:0]
1 0 0 output open drain
open drain
1 0 1 output
+pull-up
open drain
1 1 0 output
+ pull-down
1 1 1 Reserved(open drain)
0 0 0 AF output push-pull
push-pull
0 0 1 AF output
+pull-up
push-pull +
0 1 0 AF output
pull-down
0 1 1 Reserved
10 SPEED[1:0]
1 0 0 AF output open drain
open drain
1 0 1 AF output
+pull-up
open drain
1 1 0 AF output
+pull-down
1 1 Reserved

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Fremont Micro Devices FT32F0xxx8 RM

x x x 0 0 input Floating
x x x 0 1 input pull-up
00
x x x 1 0 input pull-down
x x x 1 1 Input/output
x x x 0 0 Input/output analog
x x x 0 1
11
x x x 1 0 Reserved
x x x 1 1

9.3.1. General-purpose I/O (GPIO)

During and just after reset, the alternate functions are not active and most of the I/O ports are configured in
input floating mode.
The debug pins are in AF pull-up/pull-down after reset:
 PA14: SWCLK in pull-down
 PA13: SWDIO in pull-up
When the pin is configured as output, the value written to the output data register (GPIOx_ODR) is output on
the I/O pin. It is possible to use the output driver in push-pull mode or open-drain mode. All GPIO pins have
weak internal pull-up and pull-down resistors, which can be activated or not depending on the value in the
GPIOx_PUPDR register.

9.3.2. I/O pin alternate function multiplexer and mapping

The device I/O pins are connected to on-board peripherals/modules through a multiplexer that allows only
one peripheral alternate function (AF) connected to an I/O pin at a time. In this way, there can be no conflict
between peripherals available on the same I/O pin.
Each I/O pin has a multiplexer with up to sixteen alternate function inputs (AF0 to AF15) that can be
configured through the GPIOx_AFRL (for pin 0 to 7) and GPIOx_AFRH (for pin 8 to 15) registers:
 After reset the multiplexer selection is alternate function 0 (AF0). The I/Os are configured in alternate
function mode through GPIOx_MODER register.
 The specific alternate function assignments for each pin are detailed in the device datasheet.

In addition to this flexible I/O multiplexing architecture, each peripheral has alternate functions mapped onto
different I/O pins to optimize the number of peripherals available in smaller packages.

To use an I/O in a given configuration, you have to proceed as follows:


 Debug function: after each device reset these pins are assigned as alternate function pins immediately
usable by the debugger host
 GPIO: configure the desired I/O as output, input or analog in the GPIOx_MODER register.
 Peripheral alternate function:
 Connect the I/O to the desired AFx in one of the GPIOx_AFRL or GPIOx_AFRH
register.

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Fremont Micro Devices FT32F0xxx8 RM

 Select the type, pull-up/pull-down and output speed via the GPIOx_OTYPER,
GPIOx_PUPDR and GPIOx_OSPEEDER registers, respectively.
 Configure the desired I/O as an alternate function in the GPIOx_MODER register.
 Additional functions:
 For the ADC and DAC, configure the desired I/O in analog mode in the
GPIOx_MODER register and configure the required function in the ADC or DAC
registers.
 For the additional functions like RTC, WKUPx and oscillators, configure the required
function in the related RTC, PWR and RCC registers. These functions have priority
over the configuration in the standard GPIO registers.

Please refer to the “Alternate function mapping” table in the device datasheet for the detailed mapping of the
alternate function I/O pins.

9.3.3. I/O port control registers

Each of the GPIO ports has four 32-bit memory-mapped control registers (GPIOx_MODER,
GPIOx_OTYPER, GPIOx_OSPEEDR, GPIOx_PUPDR) to configure up to 16 I/Os. The GPIOx_MODER
register is used to select the I/O mode (input, output, AF, analog). The GPIOx_OTYPER and
GPIOx_OSPEEDR registers are used to select the output type (push- pull or open-drain) and speed. The
GPIOx_PUPDR register is used to select the pull- up/pull-down whatever the I/O direction.

9.3.4. I/O port data registers

Each GPIO has two 16-bit memory-mapped data registers: input and output data registers (GPIOx_IDR and
GPIOx_ODR). GPIOx_ODR stores the data to be output, it is read/write accessible. The data input through
the I/O are stored into the input data register (GPIOx_IDR), a read-only register.
 GPIO output register:GPIOx_ODR(x=A、B、C、D、F)
 GPIO input register:GPIOx_IDR(x=A、B、C、D、F)

9.3.5. I/O data bitwise handling

The bit set reset register (GPIOx_BSRR) is a 32-bit register which allows the application to set and reset
each individual bit in the output data register (GPIOx_ODR). The bit set reset register has twice the size of
GPIOx_ODR.
To each bit in GPIOx_ODR, correspond two control bits in GPIOx_BSRR: BS(i) and BR(i). When written to 1,
bit BS(i) sets the corresponding ODR(i) bit. When written to 1, bit BR(i) resets the ODR(i) corresponding
bit.Writing any bit to 0 in GPIOx_BSRR does not have any effect on the corresponding bit in GPIOx_ODR. If
there is an attempt to both set and reset a bit in GPIOx_BSRR, the set action takes priority.Using the
GPIOx_BSRR register to change the values of individual bits in GPIOx_ODR is a “one-shot” effect that does
not lock the GPIOx_ODR bits. The GPIOx_ODR bits can always be accessed directly. The GPIOx_BSRR

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Fremont Micro Devices FT32F0xxx8 RM

register provides a way of performing atomic bitwise handling.


There is no need for the software to disable interrupts when programming the GPIOx_ODR at bit level: it is
possible to modify one or more bits in a single atomic AHB write access.

9.3.6. GPIO locking mechanism

It is possible to freeze the port A and B GPIO control registers by applying a specific write sequence to the
GPIOx_LCKR register. The frozen registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
To write the GPIOx_LCKR register, a specific write / read sequence has to be applied. When the right LOCK
sequence is applied to bit 16 in this register, the value of LCKR[15:0] is used to lock the configuration of the
I/Os (during the write sequence the LCKR[15:0] value must be the same). When the LOCK sequence has
been applied to a port bit, the value of the port bit can no longer be modified until the next MCU reset or
peripheral reset. Each GPIOx_LCKR bit freezes the corresponding bit in the control registers
(GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, GPIOx_PUPDR, GPIOx_AFRL and
GPIOx_AFRH.)

9.3.7. I/O alternate function input/output

The GPIOx_AFRL and GPIOx_AFRH register are provided to select one of the alternate function
inputs/outputs available for each I/O. With these registers, you can connect an alternate function to some
other pin as required by your application.

For more details please refer to datasheet.

9.3.8. External interrupt/wakeup lines

All ports have external interrupt capability. To use external interrupt lines, the given pin must not be
configured in analog mode or being used as oscillator pin, so the input trigger is kept enabled. For more
details please refer to EXTI.

9.3.9. Input configuration

When the I/O port is programmed as input:


 The output buffer is disabled
 The Schmitt trigger input is activated
 The pull-up and pull-down resistors are activated depending on the value in the GPIOx_PUPDR register
 The data present on the I/O pin are sampled into the input data register every AHB clock cycle
 A read access to the input data register provides the I/O state

Figure 9-2 shows the input configuration of the I/O port bit

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Fremont Micro Devices FT32F0xxx8 RM

Read on/off

Input data register


Bit set/reset registers
VDDIOx
on/off Pull-up
Input driver
Write I/O pin
on/off
Output data register
Pull-down

Output driver VSS

Read/Write

Figure 9-2 Input floating/pull up/pull down configurations

9.3.10. Output configuration

When the I/O port is programmed as output:


 The output buffer is enabled:
- Open drain mode: A “0” in the Output register activates the N-MOS whereas a “1” in the Output register
leaves the port in Hi-Z. (the P-MOS is never activated)
- Push-pull mode: A “0” in the Output register activates the N-MOS whereas a “1” in the Output register
activates the P-MOS
 The Schmitt trigger input is activated
 The pull-up and pull-down resistors are activated depending on the value in the GPIOx_PUPDR register
 The data present on the I/O pin are sampled into the input data register every AHB clock cycle
 A read access to the input data register gets the I/O state
 A read access to the output data register gets the last written value

Figure 9-3 shows the output configuration of the I/O port bit

Read on/off
Input data register

VDDIOx
Bit set/reset registers

on/off
Input driver pull-up
I/O pin
Write
Output data registers

Output driver on/off pull-down


VDDIOx
VSS
P-MOS
Output
control
Read/Write N-MOS

VSS
Push-pull or
open-drain

Figure 9-3 Output configuration

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Fremont Micro Devices FT32F0xxx8 RM

9.3.11. Alternate function configuration

When the I/O port is programmed as alternate function:


 The output buffer can be configured in open-drain or push-pull mode
 The output buffer is driven by the signals coming from the peripheral
 The Schmitt trigger input is activated
 The weak pull-up and pull-down resistors are activated or not depending on the value in the
GPIOx_PUPDR register
 The data present on the I/O pin are sampled into the input data register every AHB clock cycle
 A read access to the input data register gets the I/O state
Figure 9-4 shows the Alternate function configuration of the I/O port bit

To on-chip
peripheral
Alternate function input

Read on/off
Input data register

VDDIOx
Bit set/reset registers

pull-up
Input driver on/off
Write I/O pin
Output data register

Output driver on/off pull-down


VDDIOx
VSS
P-MOS
Output
Read/Write control
N-MOS

VSS
From on-chip Alternate function output
peripheral Push-pull or
open drain

Figure 9-4 Alternate function configuration

9.3.12. Analog configuration

When the I/O port is programmed as analog configuration:


 The output buffer is disabled
 The Schmitt trigger input is deactivated, providing zero consumption for every analog value of the I/O
pin. The output of the Schmitt trigger is forced to a constant value (0).
 The weak pull-up and pull-down resistors are disabled by hardware
 Read access to the input data register gets the value “0”
Figure 9-5 shows the high-impedance, analog-input configuration of the I/O port bit.

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Fremont Micro Devices FT32F0xxx8 RM

To on-chip Analog
peripheral

Read on/off

Input data register


Bit set/reset registers

Input driver
Write Output data register I/O pin

Read/write

From on-chip Analog


peripheral

Figure 9-5 High impedance-analog configuration

9.3.13. LED driver mode configuration

Some GPIO can use for LED driver. Setting GPIOx_LEDM to choose the appropriate source current and
sink current to satisfied the application requirement.
PB0, PB1, PB3, PB4, PB5, PB6, PB7, PA8, PA9, PA10, PA13, PA14, PA15 can change the current
characteristic to be configured as LED driver

9.3.14. Using the HSE or LSE oscillator pins as GPIOs

When the HSE or LSE oscillator is switched OFF (default state after reset), the related oscillator pins can be
used as normal GPIOs.When the HSE or LSE oscillator is switched ON (by setting the HSEON or LSEON
bit in the RCC_CSR register) the oscillator takes control of its associated pins and the GPIO configuration of
these pins has no effect.When the oscillator is configured in a user external clock mode, only the pin is
reserved for clock input and the OSC_OUT or OSC32_OUT pin can still be used as normal GPIO.

9.3.15. Using the OPx analog input pin as GPIO pins

After configuring the related register, the corresponding I/O will be switched to analog mode., and the GPIO
registers have no effect at this time.For more details please refer to OPx operational amplifier section.

9.3.16. Using the I2C1 fast-mode as GPIO pins

I2C1 fast-mode: Configure the I2C1 register to change the GPIO drive capability which alternate function is

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Fremont Micro Devices FT32F0xxx8 RM

I2C1. For more details please refer to I2C section.

9.3.17. Using the TOUCH as GPIO pins

The GPIO Schmitt trigger is not activated if it is configured as TOUCH sensor.

9.3.18. Alternate function of additional function

Table 9-2 priority of port additional function


PIN Priority (left is the highest priority)
PC13 RTC(input>output) WAKEUP GPIO -
PC14 OSC OSC_IN RTC GPIO
PC15 OSC RTC GPIO -
PA0 RTC WAKEUP OP0 GPIO

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0x24
0x20
0x18
0x14
0x10
0x08
0x08
0x04
0x00
0x00

0x1C
0x0C
0x0C
Offset
9.4.

Rev1.3
Reset
Reset
Reset
Reset
Reset
Reset
Reset
Reset
Reset
Reset
Reset
Reset
Reset
Register

GPIOx_IDR

GPIOx_ODR

GPIOx_AFRL

GPIOx_AFRH
GPIOx_LCKR
GPIOx_BSRR
GPIOx_PUPDR

(where x = A B)
(where x = A B)
(where x = A B)
GPIOA_PUPDR
GPIOx_MODER
GPIOA_MODER

GPIOx_OTYPER

GPIOx_OSPEEDR
GPIOA_OSPEEDR

(where x =B..D，F)
(where x =B..D，F)
(where x = B..D，F)

(where x = A.. D，F)


(where x = A.. D，F)
(where x = A.. D，F)
(where x = A.. D，F)
Fremont Micro Devices

– – – –

x
x
x
x
BR15 #

0
0
0
0
0
0
0
0
0
PUPDR15[1:0] PUPDR15[1:0] OSPEEDR15[1:0] OSPEEDR15[1:0] MODER15[1:0] MODER15[1:0]
– – – –

x
x
x
x
BR14 #

0
0
0
0
0
0
0
0
AFSEL15 [3:0] AFSEL7 [3:0] 0
– – – –

x
x
x
x
BR13 #

0
0
0
0
1
0
0
0
1

PUPDR14[1:0] PUPDR14[1:0] OSPEEDR14[1:0] OSPEEDR14[1:0] MODER14[1:0] MODER14[1:0]


– – – –

x
x
x
x
BR12 #

0
0
0
0
0
0
0
0
0

– – – –

x
x
x
x
BR11 #

0
0
0
0
0
0
1
0
1

PUPDR13[1:0] PUPDR13[1:0] OSPEEDR13[1:0] OSPEEDR13[1:0] MODER13[1:0] MODER13[1:0]


– – – –

x
x
x
x
BR10 #

0
0
0
0
1
0
1
0
0

AFSEL14 [3:0] AFSEL6 [3:0]


– – – –

x
x
x
x
BR9 #

0
0
0
0
0
0
0
0
0

PUPDR12[1:0] PUPDR12[1:0] OSPEEDR12[1:0] OSPEEDR12[1:0] MODER12[1:0] MODER12[1:0]


– – – –

x
x
x
x
BR8 #

0
0
0
0
0
0
0
0
0
GPIO register map

– – – –

x
x
x
x
BR7 #

0
0
0
0
0
0
0
0
0

PUPDR11[1:0] PUPDR11[1:0] OSPEEDR11[1:0] OSPEEDR11[1:0] MODER11[1:0] MODER11[1:0]


– – – –

x
x
x
x
BR6 #

0
0
0
0
0
0
0
0
0

AFSEL13 [3:0] AFSEL5 [3:0]


– – – –

x
x
x
x
BR5 #

0
0
0
0
0
0
0
0
0

PUPDR10[1:0] PUPDR10[1:0] OSPEEDR10[1:0] OSPEEDR10[1:0] MODER10[1:0] MODER10[1:0]


– – – –

x
x
x
x

BR4 #

0
0
0
0
0
0
0
0
0

– – – –

x
x
x
x

BR3 #

0
0
0
0
0
0
0
0
0

117
PUPDR9[1:0] PUPDR9[1:0] OSPEEDR9[1:0] OSPEEDR9[1:0] MODER9[1:0] MODER9[1:0]
– – – –

x
x
x
x

BR2 #

0
0
0
0
0
0
0
0
0

AFSEL12 [3:0] AFSEL4 [3:0]


– – – –

x
x
x
x

BR1 #

0
0
0
0
0
0
0
0
0

PUPDR8[1:0] PUPDR8[1:0] OSPEEDR8[1:0] OSPEEDR8[1:0] MODER8[1:0] MODER8[1:0]


LCKK – – –

x
x
x

BR0 #

0
0
0
0
0
0
0
0
0
0

x
LCK15 BS15 ODR15 IDR15 OT15 #

0
0
0
0
0
0
0
0
0
0
0
0

PUPDR7[1:0] PUPDR7[1:0] OSPEEDR7[1:0] OSPEEDR7[1:0] MODER7[1:0] MODER7[1:0]

x
LCK14 BS14 ODR14 IDR14 OT14 #

0
0
0
0
0
0
0
0
0
0
0
0

AFSEL11 [3:0] AFSEL3 [3:0]

x
LCK13 BS13 ODR13 IDR13 OT13 #

0
0
0
0
0
0
0
0
0
0
0
0

PUPDR6[1:0] PUPDR6[1:0] OSPEEDR6[1:0] OSPEEDR6[1:0] MODER6[1:0] MODER6[1:0]

x
LCK12 BS12 ODR12 IDR12 OT12 #

0
0
0
0
0
0
0
0
0
0
0
0

x
LCK11 BS11 ODR11 IDR11 OT11 #

0
0
0
0
0
0
0
0
0
0
0
0

PUPDR5[1:0] PUPDR5[1:0] OSPEEDR5[1:0] OSPEEDR5[1:0] MODER5[1:0] MODER5[1:0]

x
LCK10 BS10 ODR10 IDR10 OT10 #

0
0
0
0
0
0
0
0
0
0
0
0

AFSEL10 [3:0] AFSEL2 [3:0]

x
LCK9 BS9 ODR9 IDR9 OT9 9

0
0
0
0
0
0
0
0
0
0
0
0

PUPDR4[1:0] PUPDR4[1:0] OSPEEDR4[1:0] OSPEEDR4[1:0] MODER4[1:0] MODER4[1:0]

x
LCK8 BS8 ODR8 IDR8 OT8 8

0
0
0
0
0
0
0
0
0
0
0
0

x
LCK7 BS7 ODR7 IDR7 OT7 7

0
0
0
0
0
0
0
0
0
0
0
0

PUPDR3[1:0] PUPDR3[1:0] OSPEEDR3[1:0] OSPEEDR3[1:0] MODER3[1:0] MODER3[1:0]

x
LCK6 BS6 ODR6 IDR6 OT6 6

0
0
0
0
0
0
0
0
0
0
0
0

AFSEL9 [3:0] AFSEL1 [3:0]

x
LCK5 BS5 ODR5 IDR5 OT5 5

0
0
0
0
0
0
0
0
0
0
0
0

PUPDR2[1:0] PUPDR2[1:0] OSPEEDR2[1:0] OSPEEDR2[1:0] MODER2[1:0] MODER2[1:0]

x
LCK4 BS4 ODR4 IDR4 OT4 4

0
0
0
0
0
0
0
0
0
0
0
0

x
LCK3 BS3 ODR3 IDR3 OT3 3

0
0
0
0
0
0
0
0
0
0
0
0

PUPDR1[1:0] PUPDR1[1:0] OSPEEDR1[1:0] OSPEEDR1[1:0] MODER1[1:0] MODER1[1:0]


x
LCK2 BS2 ODR2 IDR2 OT2 2

0
0
0
0
0
0
0
0
0
0
0
0

AFSEL8 [3:0] AFSEL0 [3:0] x


LCK1 BS1 ODR1 IDR1 OT1 1

0
0
0
0
0
0
0
0
0
0
0
0

PUPDR0[1:0] PUPDR0[1:0] OSPEEDR0[1:0] OSPEEDR0[1:0] MODER0[1:0] MODER0[1:0]


x

LCK0 BS0 ODR0 IDR0 OT0 0

0
0
0
0
0
0
0
0
0
0
0
0
FT32F0xxx8 RM

2024-03-22
Fremont Micro Devices FT32F0xxx8 RM

GPIOx_BRR

–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0x2C (where x = A.. D，F)

BR15

BR14

BR13

BR12

BR11

BR10

BR9

BR8

BR7

BR6

BR5

BR4

BR3

BR2

BR1

BR0
Reset x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GPIOx_LEDM

–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–

–
–

–
–
–
–
–
–
–
–
LEDM15

LEDM14

LEDM13

LEDM10
0x30 (where x = A)

LEDM9

LEDM8
Reset x x x x x x x x x x x x x x x x 0 0 0 x x 0 0 0 x x x x x x x x

GPIOx_LEDM
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–

–
0x30 (where x = B)

LEDM7

LEDM6

LEDM5

LEDM4

LEDM3

LEDM1

LEDM0
Reset x x x x x x x x x x x x x x x x x x x x x x x x 0 0 0 0 0 x 0 0

9.4.1. GPIOx_MODER

x=A、B、C、D、F
Address offset:0x00
Reset value:
0x2800 0000 (Port A)
0x0000 0000 (Other ports)
Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 MODER15[1:0] MODER14[1:0] MODER13[1:0] MODER12[1:0]
Type RW RW RW RW RW RW RW RW
23:16 MODER11[1:0] MODER10[1:0] MODER9[1:0] MODER8[1:0]
Type RW RW RW RW RW RW RW RW
15:8 MODER7[1:0] MODER6[1:0] MODER5[1:0] MODER4[1:0]
Type RW RW RW RW RW RW RW RW
7:0 MODER3[1:0] MODER2[1:0] MODER1[1:0] MODER0[1:0]
Type RW RW RW RW RW RW RW RW

Bit Name Function


31:0 MODERy(y=15..0) These bits are written by software to configure the I/O mode
00:Input mode (reset state)
01:General purpose output mode
10:Alternate function mode
11:Analog mode

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Fremont Micro Devices FT32F0xxx8 RM

9.4.2. GPIOx_OTYPER

x=A、B、C、D、F
Address offset:0x04
Reset value:0x0000 0000
Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 OT15 OT14 OT13 OT12 OT11 OT10 OT9 OT8
Type RW RW RW RW RW RW RW RW
7:0 OT7 OT6 OT5 OT4 OT3 OT2 OT1 OT0
Type RW RW RW RW RW RW RW RW

Bit Name Function


31:16 NA Reserved
15:0 OTy(y=15..0) These bits are written by software to configure the I/O output type
0:Output push-pull (reset state)
1:Output open-drain

9.4.3. GPIOx_OSPEEDR

x=A、B、C、D、F
Address offset:0x08
Reset value:0x0000 0000
Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 OSPEEDR15[1:0] OSPEEDR14[1:0] OSPEEDR13[1:0] OSPEEDR12[1:0]
Type RW RW RW RW RW RW RW RW
23:16 OSPEEDR11[1:0] OSPEEDR10[1:0] OSPEEDR9[1:0] OSPEEDR8[1:0]
Type RW RW RW RW RW RW RW RW
15:8 OSPEEDR7[1:0] OSPEEDR6[1:0] OSPEEDR5[1:0] OSPEEDR4[1:0]
Type RW RW RW RW RW RW RW RW
7:0 OSPEEDR3[1:0] OSPEEDR2[1:0] OSPEEDR1[1:0] OSPEEDR0[1:0]
Type RW RW RW RW RW RW RW RW

Bit Name Function


31:0 OSPEEDRy(y=15..0) These bits are written by software to configure the I/O output speed.
x0:Low speed

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Fremont Micro Devices FT32F0xxx8 RM

01:Medium speed
11:High speed

9.4.4. GPIOx_PUPDR

Address offset:0x0C
Reset value:0x2400 0000(Port A)
0x0000 0000(Other ports)
Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 PUPDR15[1:0] PUPDR14[1:0] PUPDR13[1:0] PUPDR12[1:0]
Type RW RW RW RW RW RW RW RW
23:16 PUPDR11[1:0] PUPDR10[1:0] PUPDR9[1:0] PUPDR8[1:0]
Type RW RW RW RW RW RW RW RW
15:8 PUPDR7[1:0] PUPDR6[1:0] PUPDR5[1:0] PUPDR4[1:0]
Type RW RW RW RW RW RW RW RW
7:0 PUPDR3[1:0] PUPDR2[1:0] PUPDR1[1:0] PUPDR0[1:0]
Type RW RW RW RW RW RW RW RW

Bit Name Function


31:0 PUPDRy(y=15..0) These bits are written by software to configure the I/O pull-up or pull-down
00:No pull-up, pull-down
01:Pull-up
10:Pull-down
11:Reserved
Note: When MODER=2’b00 and PUPDR=2’b11, pull-up and pull-down
enable at the same time, and it is in 1/2VDD mode. If MODER not equal to
2’b00,PUPDR=2’b11,No pull-up, pull-down.

9.4.5. GPIOx_IDR

x=A、B、C、D、F
Address offset:0x10
Reset value:0x0000 xxxx
Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 IDR15 IDR14 IDR13 IDR12 IDR11 IDR10 IDR9 IDR8
Type RO RO RO RO RO RO RO RO

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Fremont Micro Devices FT32F0xxx8 RM

7:0 IDR7 IDR6 IDR5 IDR4 IDR3 IDR2 IDR1 IDR0


Type RO RO RO RO RO RO RO RO

Bit Name Function


31:16 NA Reserved
15:0 IDR[15:0] These bits are read-only. They contain the input value of the corresponding
I/O port.

9.4.6. GPIOx_ODR

x=A、B、C、D、F
Address offset:0x14
Reset value:0x0000 0000
Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 ODR15 ODR14 ODR13 ODR12 ODR11 ODR10 ODR9 ODR8
Type RW RW RW RW RW RW RW RW
7:0 ODR7 ODR6 ODR5 ODR4 ODR3 ODR2 ODR1 ODR0
Type RW RW RW RW RW RW RW RW

Bit Name Function


31:16 NA Reserved
15:0 ODR[15:0] These bits can be read and written by software.
Note:For atomic bit set/reset, the ODR bits can be individually set and/or reset by writing to the GPIOx_BSRR or
GPIOx_BRR registers (x = A..D, F).

9.4.7. GPIOx_BSRR

x=A、B、C、D、F
Address offset:0x18
Reset value:0x0000 0000
Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 BR15 BR14 BR13 BR12 BR11 BR10 BR9 BR8
Type WO WO WO WO WO WO WO WO
23:16 BR7 BR6 BR5 BR4 BR3 BR2 BR1 BR0
Type WO WO WO WO WO WO WO WO
15:8 BS15 BS14 BS13 BS12 BS11 BS10 BS9 BS8
Type WO WO WO WO WO WO WO WO

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Fremont Micro Devices FT32F0xxx8 RM

7:0 BS7 BS6 BS5 BS4 BS3 BS2 BS1 BS0


Type WO WO WO WO WO WO WO WO

Bit Name Function


31:16 BRx These bits are write-only. A read to these bits returns the value 0x0000
(x=15…0) 0:No action on the corresponding ODRx bit
1:Resets the corresponding ODRx bit
15:0 BSx These bits are write-only. A read to these bits returns the value 0x0000
(x=15…0) 0:No action on the corresponding ODRx bit
1:Sets the corresponding ODRx bit

9.4.8. GPIOx_LCKR

x=A、B
This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit
16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence,
the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the
value of this port bit can no longer be modified until the next MCU reset or peripheral reset.
Note: A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long)
is allowed during this locking sequence.
Address offset:0x1C
Reset value:0x0000 0000
Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 — LCKK
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RW
15:8 LCK15 LCK14 LCK13 LCK12 LCK11 LCK10 LCK9 LCK8
Type RW RW RW RW RW RW RW RW
7:0 LCK7 LCK6 LCK5 LCK4 LCK3 LCK2 LCK1 LCK0
Type RW RW RW RW RW RW RW RW

Bit Name Function


31:17 NA Reserved
16 LCKK Lock key
This bit can be read any time. It can only be modified using the lock key write
sequence.
0:Port configuration lock key not active
1:Port configuration lock key active. The GPIOx_LCKR register is locked
until the next MCU reset or peripheral reset.
LOCK key write sequence:

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Fremont Micro Devices FT32F0xxx8 RM

Write(LCKR[16] = 1’b1) + LCKR[15:0]


Write(LCKR[16] = 1’b0) + LCKR[15:0]
Write(LCKR[16] = 1’b0) + LCKR[15:0]
Read LCKR
Read LCKR[16]= 1’b1(this read operation is optional but it confirms that the
lock is active)
Note: During the LOCK key write sequence, the value of LCK[15:0] must not
change.
Any error in the lock sequence aborts the lock.
After the first lock sequence on any bit of the port, any read access on the
LCKK bit will return ‘1’ until the next MCU reset or peripheral reset.
15:0 LCKy These bits are read/write but can only be written when the LCKK bit is ‘0.
(y=15…0) 0:Port configuration not locked
1:Port configuration locked

9.4.9. GPIOx_AFRL

x=A、B
Address offset:0x20
Reset value:0x0000 0000
Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 — AFRSEL7 — AFRSEL6
Type RO-0 RW RW RW RO-0 RW RW RW

23:16 — AFRSEL5 — AFRSEL4


Type RO-0 RW RW RW RO-0 RW RW RW
15:8 — AFRSEL3 — AFRSEL2
Type RO-0 RW RW RW RO-0 RW RW RW
7:0 — AFRSEL1 — AFRSEL0
Type RO-0 RW RW RW RO-0 RW RW RW

Bit Name Function


31:0 AFRSELy(y=7..0) These bits are written by software to configure alternate function I/Os
000:AF0
001:AF1
010:AF2
011:AF3
100:AF4
101:AF5
110:AF6
111:AF7

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Fremont Micro Devices FT32F0xxx8 RM

9.4.10. GPIOx_AFRH

x=A、B
Address offset:0x24
Reset value:0x0000 0000
Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 — AFRSEL15 — AFRSEL14
Type RO-0 RW RW RW RO-0 RW RW RW

23:16 — AFRSEL13 — AFRSEL12


Type RO-0 RW RW RW RO-0 RW RW RW
15:8 — AFRSEL11 — AFRSEL10
Type RO-0 RW RW RW RO-0 RW RW RW
7:0 — AFRSEL9 — AFRSEL8
Type RO-0 RW RW RW RO-0 RW RW RW

Bit Name Function


31:0 AFRSELy(y=15..8) These bits are written by software to configure alternate function I/Os
000:AF0
001:AF1
010:AF2
011:AF3
100:AF4
101:AF5
110:AF6
111:AF7

9.4.11. GPIOx_BRR

x=A、B、C、D、F
Address offset:0x28
Reset value:0x0000 0000
Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 BR15 BR14 BR13 BR12 BR11 BR10 BR9 BR8
Type WO WO WO WO WO WO WO WO
7:0 BR7 BR6 BR5 BR4 BR3 BR2 BR1 BR0
Type WO WO WO WO WO WO WO WO

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Fremont Micro Devices FT32F0xxx8 RM

Bit Name Function


31:16 NA Reserved
15:0 BRx These bits are write-only. A read to these bits returns the value 0x0000
(x=15…0) 0:No action on the corresponding ODRx bit
1:Reset the corresponding ODRx bit

9.4.12. GPIOA_LEDM

LED driver mode configuration


Address offset:0x30
Reset value:0x0000 0000
Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 LEDM15 LEDM14 LEDM13 — LEDM10 LEDM9 LEDM8
Type RW RW RW RO-0 RO-0 RW RW RW
7:0 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0

Bit Name Function


31:16 NA Reserved
15:0 LEDMx LED driver mode configuration:
(x=15、14、13、 0:GPIO mode,source current 18mA,sink current 24mA
10、9、8) 1:LED driver mode,source current 2mA,sink current 45mA

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Fremont Micro Devices FT32F0xxx8 RM

9.4.13. GPIOB_LEDM

LED driver mode configuration


Address offset:0x30
Reset value:0x0000 0000
Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
7:0 LEDM7 LEDM6 LEDM5 LEDM4 LEDM3 — LEMD1 LEDM0
Type RW RW RW RW RW RO-0 RW RW

Bit Name Function


31:16 NA Reserved
15:0 LEDMx LED driver mode configuration
(x=7、6、5、4、 0:GPIO mode,source current 18mA,sink current 24mA
3、1、0) 1:LED driver mode,source current 2mA,sink current 45mA

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Fremont Micro Devices FT32F0xxx8 RM

10. System configuration controller


(SYSCFG)
Main function:
1. Enabling/disabling I2C Fast Mode Plus on some IO ports
2. Remapping some DMA trigger sources to different DMA channels
3. Remapping the memory located at the beginning of the code area
4. Managing the external interrupt line connection to the GPIOs
5. Managing robustness feature

10.1. SYSCFG register map


31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

USART1_RX_DMA_RMP 10
offset Register

USART1_TX_DMA_RMP 9

0
IRDA_ENV_SEL[1:0]
TIM17_DMA-RMP

TIM16_DMA-RMP

ADC_DMA_RMP
I2C_PB9_FMP

I2C_PB8_FMP

I2C_PB7_FMP

I2C_PB6_FMP

MEM_MODE
I2C1_FMP

SYSCFG_CFGR1
-

-
0x00

Reset x x x x x x x x x x x 0 0 0 0 0 x x x 0 0 0 0 0 0 0 x x x x x x
SYSCFG_EXTICR1 EXTI3[2:0] EXTI2[2:0] EXTI1[2:0] EXTI0[3:0]
-

0x08
Reset x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SYSCFG_EXTICR2 EXTI7[2:0] EXTI6[2:0] EXTI5[2:0] EXTI4[2:0]
-

0x0C
Reset x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SYSCFG_EXTICR3 EXTI11[2:0] EXTI10[2:0] EXTI9[2:0] EXTI8[2:0]
-

0x10
Reset x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SYSCFG_EXTICR4 EXTI5[2:0] EXTI4[2:0] EXTI13[2:0] EXTI12[2:0]
-

0x14
Reset x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

LOCKUP_LOCK
PVD_LOCK
SYSCFG_CFGR2
-

-
0x18

Reset x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 0 x 0

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Fremont Micro Devices FT32F0xxx8 RM

10.1.1. SYSCFG_CFGR1

Address offset:0x00
Reset value:0x0000 000X
Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
Type RW RW RW RW RW RW RW RW
23:16 — — — I2C1_FMP I2C_PB9 I2C_PB8 I2C_PB7 I2C_PB6
_FMP _FMP _FMP _FMP
Type RW RW RW RW RW RW RW RW
15:8 — — — TIM17_ TIM16_ USART1_ USART1_ ADC_
DMA DMA RX_DMA TX_DMA DMA
_RMP _RMP _RMP _RMP _RMP
Type RW RW RW RW RW RW RW RW
7:0 IRDA_ENV_SEL[1:0] — MEM_MODE
Type RW RW RW RW RW RW RW RW

Bit Name Function


31:21 NA Reserved
20 I2C1_FMP FM+ driving capability activation for I2C1
0:FM+ mode is controlled by I2C_Pxx_FM+ bits only.
1: FM+ mode is enabled on all I2C1 pins selected through selection
bits in GPIOx_AFR registers. This is the only way to enable the
FM+ mode for pads without a dedicated I2C_Pxx_FM+ control bit.
19:16 I2C_PBx_FMP Fast Mode Plus (FM+) driving capability activation bits,x = 6~9
0:PBx pin operates in standard mode
1:I2C FM+ mode enabled on PBx pin and the Speed control is
bypassed.
15:13 NA Reserved
12 TIM17_DMA_RMP TIM17 DMA request remapping bit, This bit is set and cleared by
software.
0:No remap (TIM17_CH1 and TIM17_UP DMA requests mapped
on DMA channel 1)
1:Remap (TIM17_CH1 and TIM17_UP DMA requests mapped on
DMA channel 2)
11 TIM16_DMA_RMP TIM16 DMA request remapping bit, This bit is set and cleared by
software.
0:No remap (TIM16_CH1 and TIM16_UP DMA requests mapped
on DMA channel 3)
1:Remap (TIM16_CH1 and TIM16_UP DMA requests mapped on
DMA channel 4)

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Fremont Micro Devices FT32F0xxx8 RM

10 USART1_RX_DMA_RMP USART1_RX DMA request remapping bit.


0:No remap (USART1_RX DMA request mapped on DMA channel
3)
1:Remap (USART1_RX DMA request mapped on DMA channel 5)
9 USART1_TX_DMA_RMP USART1_TX DMA request remapping bit.
0:No remap (USART1_TX DMA request mapped on DMA channel
2)
1:Remap (USART1_TX DMA request mapped on DMA channel 4)
8 ADC_DMA_RMP ADC DMA request remapping bit.
0:No remap (ADC DMA request mapped on DMA channel 1)
1:Remap (ADC DMA request mapped on DMA channel 2)
7:6 IRDA_ENV_SEL[1:0] IRDA envelop signal selection
00: TIM16
01:USART1
10:USART2
11: Reserved
5:2 NA Reserved
1:0 MEM_MODE[1:0] Memory mapping selection bits
x0:Main Flash memory mapped at 0x00000000
01:System Flash memory mapped at 0x00000000
11:Embedded SRAM mapped at 0x00000000

10.1.2. SYSCFG_EXTICR1

Address offset:0x08
Reset value:0x0000 0000
Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 EXTI3[3:0] EXTI2[3:0]
Type RW RW RW RW RW RW RW RW
7:0 EXTI1[3:0] EXTI0[3:0]
Type RW RW RW RW RW RW RW RW

Bit Name Function


31:16 NA Reserved
15:12 EXTI3[3:0] EXTI 3 configuration bits
0000:PA3 pin
0001:PB3 pin

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Fremont Micro Devices FT32F0xxx8 RM

0010:PC3 pin
0011:Reserved
0100:Reserved
0101:Reserved
Other configurations: Reserved
11:8 EXTI2[3:0] EXTI 2 configuration bits
0000:PA2 pin
0001:PB2 pin
0010:PC2 pin
0011:PD2 pin
0100:Reserved
0101:Reserved
Other configurations: Reserved
7:4 EXTI1[3:0] EXTI 1 configuration bits
0000:PA1 pin
0001:PB1 pin
0010:PC1 pin
0011:Reserved
0100:Reserved
0101:PF1 pin
Other configurations: Reserved
3:0 EXTI0[3:0] EXTI 0 configuration bits
0000:PA0 pin
0001:PB0 pin
0010:PC0 pin
0011:Reserved
0100:Reserved
0101:PF0 pin
Other configurations: Reserved

10.1.3. SYSCFG_EXTICR2

Address offset:0x0C
Reset value:0x0000 0000
Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 EXTI7[3:0] EXTI6[3:0]
Type RW RW RW RW RW RW RW RW

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Fremont Micro Devices FT32F0xxx8 RM

7:0 EXTI5[3:0] EXTI4[3:0]


Type RW RW RW RW RW RW RW RW

Bit Name Function


31:16 NA Reserved
15:12 EXTI7[3:0] EXTI 7 configuration bits
0000:PA7 pin
0001:PB7 pin
0010:PC7 pin
0011:Reserved
0100:Reserved
0101:PF7 pin
Other configurations: Reserved
11:8 EXTI6[3:0] EXTI 6 configuration bits
0000:PA6 pin
0001:PB6 pin
0010:PC6 pin
0011:Reserved
0100:Reserved
0101:PF6 pin
Other configurations: Reserved
7:4 EXTI5[3:0] EXTI 5 configuration bits
0000:PA5 pin
0001:PB5 pin
0010:PC5 pin
0011:Reserved
0100:Reserved
0101:PF5 pin
Other configurations: Reserved
3:0 EXTI4[3:0] EXTI 4 configuration bits
0000:PA4 pin
0001:PB4 pin
0010:PC4 pin
0011:Reserved
0100:Reserved
0101:PF4 pin
Other configurations: Reserved

10.1.4. SYSCFG_EXTICR3

Address offset:0x10

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Reset value:0x0000 0000


Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 EXTI11[3:0] EXTI10[3:0]
Type RW RW RW RW RW RW RW RW
7:0 EXTI9[3:0] EXTI8[3:0]
Type RW RW RW RW RW RW RW RW

Bit Name Function


31:16 NA Reserved
15:12 EXTI11[3:0] EXTI 11 configuration bits
0000:PA11 pin
0001:PB11 pin
0010:PC11 pin
0011:Reserved
0100:Reserved
0101:Reserved
Other configurations: Reserved
11:8 EXTI10[3:0] EXTI 10 configuration bits
0000:PA10 pin
0001:PB10 pin
0010:PC10 pin
0011:Reserved
0100:Reserved
0101:Reserved
Other configurations: Reserved
7:4 EXTI9[3:0] EXTI 9 configuration bits
0000:PA9 pin
0001:PB9 pin
0010:PC9 pin
0011:Reserved
0100:Reserved
0101:Reserved
Other configurations: Reserved
3:0 EXTI8[3:0] EXTI 8 configuration bits
0000:PA8 pin
0001:PB8 pin
0010:PC8 pin
0011:Reserved
0100:Reserved

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0101:Reserved
Other configurations: Reserved

10.1.5. SYSCFG_EXTICR4

Address offset:0x14
Reset value:0x0000 0000
Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 EXTI15[3:0] EXTI14[3:0]
Type RW RW RW RW RW RW RW RW
7:0 EXTI3[3:0] EXTI2[3:0]
Type RW RW RW RW RW RW RW RW

Bit Name Function


31:16 NA Reserved
15:12 EXTI15[3:0] EXTI 15 configuration bits
0000:PA15 pin
0001:PB15 pin
0010:PC15 pin
0011:Reserved
0100:Reserved
0101:Reserved
Other configurations: Reserved
11:8 EXTI14[3:0] EXTI 14 configuration bits
0000:PA14 pin
0001:PB14 pin
0010:PC14 pin
0011:Reserved
0100:Reserved
0101:Reserved
Other configurations: Reserved
7:4 EXTI13[3:0] EXTI 13 configuration bits
0000:PA13 pin
0001:PB13 pin
0010:PC13 pin
0011:Reserved
0100:Reserved

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0101:Reserved
Other configurations: Reserved
3:0 EXTI12[3:0] EXTI 12 configuration bits
0000:PA12 pin
0001:PB12 pin
0010:PC12 pin
0011:Reserved
0100:Reserved
0101:Reserved
Other configurations: Reserved

10.1.6. SYSCFG_CFGR2

Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0


31:24 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
7:0 — PVD_ — LOCKUP
LOCK _LOCK
Type RO-0 RO-0 RO-0 RO-0 RO-0 RW RO-0 RW

Bit Name Function


31:3 NA Reserved, do not write “1”
2 PVD_LOCK PVD lock bit,This bit is set and cleared by software.
0:PVD interrupt not connect to TIM1/15/16/17 break input,PVDE and
PLS[2:0] bits can be write by software
1:PVD interrupt interrupt not connect to TIM1/15/16/17 break input,PVDE
and PLS[2:0] bits can be read by software
1 NA Reserved
0 LOCKUP_LOCK Cortex-M0 LOCKUP output to TIM1 break input
0:Cortex-M0 LOCKUP output not connect to TIM1/15/16/17 break input
1:Cortex-M0 LOCKUP output connect to TIM1/15/16/17 break input

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11. Direct memory access controller(DMA)

11.1. Introduction

Direct memory access (DMA) is used in order to provide high-speed data transfer between peripherals and
memory as well as memory to memory. Data can be quickly moved by DMA without any CPU actions. This
keeps CPU resources free for other operations.
The DMA controller has up to 5 channels, each dedicated to managing memory access requests from one or
more peripherals. It has an arbiter for handling the priority between DMA requests.

11.2. DMA main features

 Up to 5 independently configurable channels (requests) on DMA


 Each channel is connected to dedicated hardware DMA requests, software trigger is also supported on
each channel. This configuration is done by software.
 Priorities between requests from the DMA channels are software programmable (4 levels consisting of
very high, high, medium, low) or hardware in case of equality (request 1 has priority over request 2,
etc.)
 Independent source and destination transfer size (byte, half word, word), emulating packing and
unpacking. Source/destination addresses must be aligned on the data size.
 Support for circular buffer management
 3 event flags (DMA Half Transfer, DMA Transfer complete and DMA Transfer Error) logically ORed
together in a single interrupt request for each channel
 Memory-to-memory transfer
 Peripheral-to-memory and memory-to-peripheral, and peripheral-to-peripheral transfers
 Access to Flash, SRAM, APB and AHB peripherals as source and destination
 Programmable number of data to be transferred: up to 4095

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11.3. DMA functional description

FLITF Flash

System
Cortex-M0

DMA SRAM
Ch.1
Bus matrix
DMA
Ch.2 Reset & clock control
CRC GPIOA GPIOB
（RCC）

up to
Ch.5 Bridge

Arbiter APB
GPIOC GPIOD GPIOF

AHB Slave
ADC TIM1
USART1 TIM3
USART2 TIM6
I2C1 TIM15
I2C2 TIM16
SPI1 TIM17
SPI2

Figure 11-1 DMA block diagram

The DMA controller performs direct memory transfer by sharing the system bus with the Cortex ®-M0 core.
The DMA request may stop the CPU access to the system bus for some bus cycles, when the CPU and
DMA are targeting the same destination (memory or peripheral). The bus matrix implements round-robin
scheduling, thus ensuring at least half of the system bus bandwidth (both to memory and peripheral) for the
CPU.

11.3.1. DMA transactions

After an event, the peripheral sends a request signal to the DMA Controller. The DMA controller serves the
request depending on the channel priorities. As soon as the DMA Controller accesses the peripheral, an
Acknowledge is sent to the peripheral by the DMA Controller. The peripheral releases its request as soon as
it gets the Acknowledge from the DMA Controller. Once the request is de-asserted by the peripheral, the
DMA Controller release the Acknowledge. If there are more requests, the peripheral can initiate the next
transaction.
In summary, each DMA transfer consists of three operations:
 The loading of data from the peripheral data register or a ___location in memory addressed through an
internal current peripheral/memory address register. The start address used for the first transfer is the

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base peripheral/memory address programmed in the DMA_CPARx or DMA_CMARx register


 The storage of the data loaded to the peripheral data register or a ___location in memory addressed
through an internal current peripheral/memory address register. The start address used for the first
transfer is the base peripheral/memory address programmed in the DMA_CPARx or DMA_CMARx
register
 The post-decrementing of the DMA_CNDTRx register, which contains the number of transactions that
have still to be performed.

11.3.2. Arbiter

The arbiter manages the channel requests based on their priority and launches the peripheral/memory
access sequences.
The priorities are managed in two stages:
 Software: each channel priority can be configured in the DMA_CCRx register. There are four levels:
─ Very high priority
─ High priorit
─ Medium priority
─ Low priority
 Hardware: if 2 requests have the same software priority level, the channel with the lowest number will
get priority versus the channel with the highest number. For example, channel 2 gets priority over
channel 4.

11.3.3. DMA channels

Each channel can handle DMA transfer between a peripheral register located at a fixed address and a
memory address. The amount of data to be transferred (up to 65535) is programmable. The register which
contains the amount of data items to be transferred is decremented after each transaction.

Programmable data sizes


Transfer data sizes of the peripheral and memory are fully programmable through the PSIZE and MSIZE bits
in the DMA_CCRx register.

Pointer incrementation
Peripheral and memory pointers can optionally be automatically post-incremented after each transaction
depending on the PINC and MINC bits in the DMA_CCRx register. If incremented mode is enabled, the
address of the next transfer will be the address of the previous one incremented by 1, 2 or 4 depending on
the chosen data size. The first transfer address is the one programmed in the DMA_CPARx/DMA_CMARx
registers. During transfer operations, these registers keep the initially programmed value. The current
transfer addresses (in the current internal peripheral/memory address register) are not accessible by
software.
If the channel is configured in non-circular mode, no DMA request is served after the last transfer (that is
once the number of data items to be transferred has reached zero). In order to reload a new number of data

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items to be transferred into the DMA_CNDTRx register, the DMA channel must be disabled.
Note: If a DMA channel is disabled, the DMA registers are not reset. The DMA channel registers
(DMA_CCRx, DMA_CPARx and DMA_CMARx) retain the initial values programmed during the channel
configuration phase.
In circular mode, after the last transfer, the DMA_CNDTRx register is automatically reloaded with the initially
programmed value. The current internal address registers are reloaded with the base address values from
the DMA_CPARx/DMA_CMARx registers.

Channel configuration procedure


The following sequence should be followed to configure a DMA channel x (where x is the channel number):
1. Set the peripheral register address in the DMA_CPARx register. The data will be moved from/ to this
address to/ from the memory after the peripheral event.
2. Set the memory address in the DMA_CMARx register. The data will be written to or read from this
memory after the peripheral event.
3. Configure the total number of data to be transferred in the DMA_CNDTRx register. After each peripheral
event, this value will be decremented.
4. Configure the channel priority using the PL[1:0] bits in the DMA_CCRx register
5. Configure data transfer direction, circular mode, peripheral & memory incremented mode, peripheral &
memory data size, and interrupt after half and/or full transfer in the DMA_CCRx register
6. Activate the channel by setting the ENABLE bit in the DMA_CCRx register.
As soon as the channel is enabled, it can serve any DMA request from the peripheral connected on the
channel.
Once half of the bytes are transferred, the half-transfer flag (HTIF) is set and an interrupt is generated if the
Half-Transfer Interrupt Enable bit (HTIE) is set. At the end of the transfer, the Transfer Complete Flag (TCIF)
is set and an interrupt is generated if the Transfer Complete Interrupt Enable bit (TCIE) is set.

Circular mode
Circular mode is available to handle circular buffers and continuous data flows (e.g. ADC scan mode). This
feature can be enabled using the CIRC bit in the DMA_CCRx register. When circular mode is activated, the
number of data to be transferred is automatically reloaded with the initial value programmed during the
channel configuration phase, and the DMA requests continue to be served.

Memory-to-memory mode
The DMA channels can also work without being triggered by a request from a peripheral. This mode is called
Memory to Memory mode.
If the MEM2MEM bit in the DMA_CCRx register is set, then the channel initiates transfers as soon as it is
enabled by software by setting the Enable bit (EN) in the DMA_CCRx register. The transfer stops once the
DMA_CNDTRx register reaches zero. Memory to Memory mode may not be used at the same time as
Circular mode.

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11.3.4. Programmable data width, data alignment and


endians

When PSIZE and MSIZE are not equal, the DMA performs some data alignments as described in Table 11-1

Table 11-1 Programmable data width & endian behavior


So
urc Desti
Number Source
e natio Destination
of data content:
por n Transfer operations content:
items to address /
t port address / data
transfer data
wid width
th
@0x0 / B0 1:READ B0[7:0] @0x0 then WRITE B0[7:0] 0x0 @0x0 / B0

@0x1 / B1 2:READ B1[7:0] @0x1 then WRITE B1[7:0] 0x1 @0x1 / B1


8 8 4
@0x2 / B2 3:READ B2[7:0] @0x2 then WRITE B2[7:0] 0x2 @0x2 / B2

@0x3 / B3 4:READ B3[7:0] @0x3 then WRITE B3[7:0] 0x3 @0x3 / B3

@0x0 / B0 1:READ B0[7:0] @0x0 then WRITE 00B0[15:0] 0x0 @0x0 / 00B0

@0x1 / B1 2:READ B1[7:0] @0x1 then WRITE 00B1[15:0] 0x2 @0x2 / 00B1
8 16 4
@0x2 / B2 3:READ B2[7:0] @0x2 then WRITE 00B2[15:0] 0x4 @0x4 / 00B2

@0x3 / B3 4:READ B3[7:0] @0x3 then WRITE 00B3[15:0] 0x6 @0x6 / 00B3

@0x0 / B0 1:READ B0[7:0] @0x0 then WRITE 000000B0[31:0] 0x0 @0x0 / 000000B0

@0x1 / B1 2:READ B1[7:0] @0x1 then WRITE 000000B1[31:0] 0x4 @0x4 / 000000B1
8 32 4
@0x2 / B2 3:READ B2[7:0] @0x2 then WRITE 000000B2[31:0] 0x8 @0x8 / 000000B2

@0x3 / B3 4:READ B3[7:0] @0x3 then WRITE 000000B3[31:0] 0xC @0xC / 000000B3

@0x0 / B1B0 1:READ B1B0[15:0] @0x0 then WRITE B0[7:0] 0x0 @0x0 / B0

@0x2 / B3B2 2:READ B3B2[15:0] @0x2 then WRITE B2[7:0] 0x1 @0x1 / B2
16 8 4
@0x4 / B5B4 3:READ B5B4[15:0] @0x4 then WRITE B4[7:0] 0x2 @0x2 / B4

@0x6 / B7B6 4:READ B7B6[15:0] @0x6 then WRITE B6[7:0] 0x3 @0x3 / B6

@0x0 / B1B0 1:READ B1B0[15:0] @0x0 then WRITE B1B0[15:0] 0x0 @0x0 / B1B0

@0x2 / B3B2 2:READ B3B2[15:0] @0x2 then WRITE B3B2[15:0] 0x2 @0x2 / B3B2
16 16 4
@0x4 / B5B4 3:READ B5B4[15:0] @0x4 then WRITE B5B4[15:0] 0x4 @0x4 / B5B4

@0x6 / B7B6 4:READ B7B6[15:0] @0x6 then WRITE B7B6[15:0] 0x6 @0x6 / B7B6

@0x0 / B1B0 1:READ B1B0[15:0] @0x0 then WRITE 0000B1B0[31:0] 0x0 @0x0 / 0000B1B0

@0x2 / B3B2 2:READ B3B2[15:0] @0x2 then WRITE 0000B3B2[31:0] 0x4 @0x4 / 0000B3B2
16 32 4
@0x4 / B5B4 3:READ B5B4[15:0] @0x4 then WRITE 0000B5B4[31:0] 0x8 @0x8 / 0000B5B4

@0x6 / B7B6 4:READ B7B6[15:0] @0x6 then WRITE 0000B7B6[31:0] 0xC @0xC / 0000B7B6

@0x0 / 1:READ B3B2B1B0[31:0] @0x0 then WRITE B0[7:0] 0x0 @0x0 / B0

B3B2B1B0 2:READ B7B6B5B4[31:0] @0x4 then WRITE B4[7:0] 0x1 @0x1 / B4


32 8 4
@0x4 / 3:READ BBBAB9B8[31:0] @0x8 then WRITE B8[7:0] 0x2 @0x2 / B8

B7B6B5B4 4:READ BFBEBDBC[31:0] @0xC then WRITE BC[7:0] 0x3 @0x3 / BC

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@0x8 /

BBBAB9B8

@0xC /

BFBEBDBC

@0x0 /

B3B2B1B0

@0x4 / 1:READ B3B2B1B0[31:0] @0x0 then WRITE B1B0[15:0] 0x0 @0x0 / B1B0

B7B6B5B4 2:READ B7B6B5B4[31:0] @0x4 then WRITE B5B4[15:0] 0x2 @0x2 / B5B4
32 16 4
@0x8 / 3:READ BBBAB9B8[31:0] @0x8 then WRITE B9B8[15:0] 0x4 @0x4 / B9B8

BBBAB9B8 4:READ BFBEBDBC[31:0] @0xC then WRITE BDBC[15:0] 0x6 @0x6 / BDBC

@0xC /

BFBEBDBC

@0x0 / 1:READ B3B2B1B0[31:0] @0x0 then WRITE B3B2B1B0[31:0]

B3B2B1B0 0x0

@0x4 / 2:READ B7B6B5B4[31:0] @0x4 then WRITE B7B6B5B4[31:0] @0x0 / B3B2B1B0

B7B6B5B4 0x4 @0x4 / B7B6B5B4


32 32 4
@0x8 / 3:READ BBBAB9B8[31:0] @0x8 then WRITE BBBAB9B8[31:0] @0x8 / BBBAB9B8

BBBAB9B8 0x8 @0xC / BFBEBDBC

@0xC / 4:READ BFBEBDBC[31:0] @0xC then WRITE BFBEBDBC[31:0]

BFBEBDBC 0xC

Addressing an AHB peripheral that does not support byte or halfword write operations
When the DMA initiates an AHB byte or halfword write operation, the data are duplicated on the unused
lanes of the HWDATA[31:0] bus. So when the used AHB slave peripheral does not support byte or halfword
write operations (when HSIZE is not used by the peripheral) and does not generate any error, the DMA
writes the 32 HWDATA bits as shown in the two examples below:
 To write the halfword “0xABCD”, the DMA sets the HWDATA bus to “0xABCDABCD” with HSIZE =
HalfWord
 To write the byte “0xAB”, the DMA sets the HWDATA bus to “0xABABABAB” with HSIZE = Byte
Assuming that the AHB/APB bridge is an AHB 32-bit slave peripheral that does not take the HSIZE data into
account, it will transform any AHB byte or halfword operation into a 32-bit APB operation in the following
manner:
 an AHB byte write operation of the data “0xB0” to 0x0 (or to 0x1, 0x2 or 0x3) will be converted to an
APB word write operation of the data “0xB0B0B0B0” to 0x0
 an AHB halfword write operation of the data “0xB1B0” to 0x0 (or to 0x2) will be converted to an APB
word write operation of the data “0xB1B0B1B0” to 0x0
For instance, if you want to write the APB backup registers (16-bit registers aligned to a 32- bit address
boundary), you must configure the memory source size (MSIZE) to “16-bit” and the peripheral destination
size (PSIZE) to “32-bit”.

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11.3.5. Error management

A DMA transfer error can be generated by reading from or writing to a reserved address space. When a
DMA transfer error occurs during a DMA read or a write access, the faulty channel is automatically disabled
through a hardware clear of its EN bit in the corresponding Channel configuration register (DMA_CCRx). The
channel's transfer error interrupt flag (TEIF) in the DMA_IFR register is set and an interrupt is generated if
the transfer error interrupt enable bit (TEIE) in the DMA_CCRx register is set.

11.3.6. DMA interrupts

An interrupt can be produced on a Half-transfer, Transfer complete or Transfer error for each DMA channel.
Separate interrupt enable bits are available for flexibility.
Table 11-2 DMA interrupt requests
Interrupt event Event flag Enable control bit
Half-transfer HTIF HTIE
Transfer complete TCIF TCIE
Transfer error TEIF TEIE

DMA controller
The hardware requests from the peripherals (TIMx, ADC, DAC, SPI, I2C, and USARTx) are simply logically
ORed before entering the DMA. This means that on one channel, only one request must be enabled at a
time.
The peripheral DMA requests can be independently activated/de-activated by programming the DMA control
bit in the registers of the corresponding peripheral.

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DMA
Fixed hardware priority

ADC(1), Hardware request 1 High


TIM17_CH1(1), priority
Ch1
TIM17_UP(1) Software trigger 1
（MEM2MEM位）
ADC(2),SPI1_RX,
USART1_TX(1),
Hardware request 2
I2C1_TX,TIM1_CH1,
TIM3_CH3, Ch2
Software trigger 2
TIM17_CH1(2),
（MEM2MEM位）
TIM17_UP(2)

SPI1_TX,
USART1_RX(1),
I2C1_RX,TIM1_CH2, Hardware request 3
Internal DMA
TIM3_CH4,TIM3_UP, Ch3 request
TIM6_UP,TIM16_CH1(1), Software trigger 3
TIM16_UP(1) （MEM2MEM位）

SPI2_RX,
USART1_TX(2),
I2C2_TX,USART2_TX,
TIM1_CH4,TIM1_TRIG, Hardware request 4
TIM1_COM, Ch4
TIM3_CH1,TIM3_TRIG, Software trigger 4
TIM16_CH1(2), （MEM2MEM位）
TIM16_UP(2)

SPI2_TX,
USART1_RX(2),
I2C2_RX,USART2_RX, Hardware request 5
TIM1_CH3,TIM1_UP, Ch5
TIM15_CH1, Software trigger 5
TIIM15_UP,TIM15_TRIG, （MEM2MEM位） Low
TIM15_COM priority

Figure 11-2 DMA request mapping


1. DMA request mapped on this DMA channel only if the corresponding remapping bit is cleared in the
SYSCFG_CFGR1 register. For more details, please refer to section 10.1.1:SYSCFG_CFGR1;
2. DMA request mapped on this DMA channel only if the corresponding remapping bit is cleared in the
SYSCFG_CFGR1 register. For more details, please refer to section 10.1.1:SYSCFG_CFGR1.

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Table 11-3 lists the DMA requests for each channel


Table 11-3 Summary of the DMA requests for each channel
Peripherals Channel 1 Channel 2 Channel 3 Channel 4 Channel 5
(1) (2)
ADC ADC ADC - - -
SPI - SPI1_RX SPI1_TX SPI2_RX SPI2_TX
USART1_RX(2
USART1_RX(1 USART1_TX(2)
USART - USART1_TX(1) )
)
USART2_TX
USART2_RX
I2C - I2C1_TX I2C1_RX I2C2_TX I2C2_RX
TIM1_CH4
TIM1_CH3
TIM1 - TIM1_CH1 TIM1_CH2 TIM1_TRIG
TIM1_UP
TIM1_COM
TIM3_CH4 TIM3_CH1
TIM3 - TIM3_CH3 -
TIM3_UP TIM3_TRIG
TIM6 - - TIM6_UP - -
TIM15_CH1
TIM15_UP
TIM15 - - - -
TIM15_TRIG
TIM15_COM
(1) (2)
TIM16_CH1 TIM16_CH1
TIM16 - - (1) -
TIM16_UP TIM16_UP(2)
TIM17_CH1(1) TIM17_CH1(2)
TIM17 - - -
TIM17_UP(1) TIM17_UP(2)
1. DMA request mapped on this DMA channel only if the corresponding remapping bit is cleared in the
SYSCFG_CFGR1 register. For more details, please refer to section 9.1.1:SYSCFG_CFGR1;
2. DMA request mapped on this DMA channel only if the corresponding remapping bit is cleared in the
SYSCFG_CFGR1 register. For more details, please refer to section 9.1.1:SYSCFG_CFGR1.

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11.4. DMA register map

31
30
29
28
27
26
25
24
23
22
21
20
TEIF5 19
HTIF5 18
TCIF5 17
16
TEIF4 15
HTIF4 14
TCIF4 13
12
TEIF3 11
HTIF3 10
Offset Register

TCIF3 9
8
TEIF2 7
HTIF2 6
TCIF2 5
4
TEIF1 3
HTIF1 2
TCIF1 1
0
GIF5

GIF4

GIF3

GIF2

GIF1
DMA_ISR
–
–
–
–
–
–
–
–
–
–
–
–
0x00

Reset x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CTEIF5
CHTIF5
CTCIF5

CTEIF4
CHTIF4
CTCIF4

CTEIF3
CHTIF3
CTCIF3

CTEIF2
CHTIF2
CTCIF2

CTEIF1
CHTIF1
CTCIF1
CGIF5

CGIF4

CGIF3

CGIF2

CGIF1
DMA_IFCR
–
–
–
–
–
–
–
–
–
–
–
–
0x04

Reset x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MEM2MEM

MSIZE[1:0]

PSIZE[1:0]

MINC
PINC
CIRC

TEIE
HTIE
TCIE
DIR
PL

EN
DMA_CCR1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0x08 [1:0]

Reset x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_CNDTR1 NDT[15:0]
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0x0C
Reset x x x x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0
DMA_CPAR1 PA[31:0]
0x10
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_CMAR1 MA[31:0]
0x14
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MEM2MEM

MSIZE[1:0]

PSIZE[1:0]

MINC
PINC
CIRC

TEIE
HTIE
TCIE
DIR
PL

EN
DMA_CCR2
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–

0x1C [1:0]

Reset x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_CNDTR2 NDT[15:0]
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–

0x20
Reset x x x x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0
DMA_CPAR2 PA[31:0]
0x24
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_CMAR2 MA[31:0]
0x28
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MEM2MEM

MSIZE[1:0]

PSIZE[1:0]

MINC
PINC
CIRC

TEIE
HTIE
TCIE
DIR

PL

EN
DMA_CCR3
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–

0x30 [1:0]

Reset x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_CNDTR3 NDT[11:0]
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–

0x34
Reset x x x x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0
DMA_CPAR3 PA[31:0]
0x38
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_CMAR3 MA[31:0]
0x3C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MEM2MEM

MSIZE[1:0]

PSIZE[1:0]

MINC
PINC
CIRC

TEIE
HTIE
TCIE
DIR

PL
EN

DMA_CCR4
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–

0x44 [1:0]

Reset x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_CNDTR4 NDT[15:0]
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–

0x48
Reset x x x x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0
DMA_CPAR4 PA[31:0]
0x4C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x50 DMA_CMAR4 MA[31:0]

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Fremont Micro Devices FT32F0xxx8 RM

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
MEM2MEM 14
13
12
11
10
Offset Register

9
8
7
6
5
4
3
2
1
0
MSIZE[1:0]

PSIZE[1:0]

MINC
PINC
CIRC

HTIE
TEIE

TCIE
DIR
PL

EN
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
DMA_CCR5
0x58 [1:0]

Reset x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_CNDTR5 NDT[15:0]
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0x5C
Reset x x x x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0
DMA_CPAR5 PA[31:0]
0x60
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_CMAR5 MA[31:0]
0x64
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

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Fremont Micro Devices FT32F0xxx8 RM

11.4.1. DMA_ISR

Address offset:0x00
Reset value:0x0000 0000

Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0


31:24 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 — TEIF5 HTIF5 TCIF5 GIF5
Type RO-0 RO-0 RO-0 RO-0 RO RO RO RO
15:8 TEIF4 HTIF4 TCIF4 GIF4 TEIF3 HTIF3 TCIF3 GIF3
Type RO RO RO RO RO RO RO RO
7:0 TEIF2 HTIF2 TCIF2 GIF2 TEIF1 HTIF1 TCIF1 GIF1
Type RO RO RO RO RO RO RO RO

Bit Name Function


31:20 NA Reserved
19,15,11, TEIFx Channel x transfer error flag(x=1..5)
7,3 This bit is set by hardware. It is cleared by software writing 1 to the
corresponding bit in the DMA_IFCR register
0:No transfer error (TE) on channel x
1:A transfer error (TE) occurred on channel x
18,14,10, HTIFx Channel x half transfer flag(x=1..5)
6,2 This bit is set by hardware. It is cleared by software writing 1 to the
corresponding bit in the DMA_IFCR register.
0:No half transfer (HT) event on channel x
1:A half transfer (HT) event occurred on channel x
17,13,9,5, TCIFx Channel x transfer complete flag(x=1..5)
1 This bit is set by hardware. It is cleared by software writing 1 to the
corresponding bit in the DMA_IFCR register.
0:No transfer complete (TC) event on channel x
1:A transfer complete (TC) event occurred on channel x
16,12,8,4, GIFx Channel x global interrupt flag(x=1..5)
0 This bit is set by hardware. It is cleared by software writing 1 to the
corresponding bit in the DMA_IFCR register.
0:No TE, HT or TC event on channel x
1:A TE, HT or TC event occurred on channel x

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Fremont Micro Devices FT32F0xxx8 RM

11.4.2. DMA_IFCR

Address offset:0x04
Reset value:0x0000 0000

Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0


31:24 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 — CTEIF5 CHTIF5 CTCIF5 CGIF5
Type RO-0 RO-0 RO-0 RO-0 W W W W
15:8 CTEIF4 CHTIF4 CTCIF4 CGIF4 CTEIF3 CHTIF3 CTCIF3 CGIF3
Type W W W W W W W W
7:0 CTEIF2 CHTIF2 CTCIF2 CGIF2 CTEIF1 CHTIF1 CTCIF1 CGIF1
Type W W W W W W W W

Bit Name Function


31:20 NA Reserved
19,15,11, CTEIFx Channel x transfer error clear(x=1..5)
7,3 This bit is set and cleared by software.
0:No effect
1:Clears the corresponding TEIF flag in the DMA_ISR register
18,14,10, CHTIFx Channel x half transfer clear(x=1..5)
6,2 This bit is set and cleared by software.
0:No effect
1:Clears the corresponding HTIF flag in the DMA_ISR register
17,13,9,5, CTCIFx Channel x transfer complete clear(x=1..5)
1 This bit is set and cleared by software.
0:No effect
1: Clears the corresponding TCIF flag in the DMA_ISR register
16,12,8,4, CGIFx Channel x global interrupt clear(x=1..5)
0 This bit is set and cleared by software.
0:No effect
1:Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register

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Fremont Micro Devices FT32F0xxx8 RM

11.4.3. DMA_CCRx(x=1..5)

Address offset:0x08 + 0d20 × (channel number - 1)


Reset value:0x0000 0000

Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0


31:24 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 — MEM2MEM PL[1:0] MSIZE[1:0] PSIZE[1:0]
Type RO-0 RW RW RW RW RW RW RW
7:0 MINC PINC CIRC DIR TEIE HTIE TCIE EN
Type RW RW RW RW RW RW RW RW

Bit Name Function


31:15 NA Reserved
14 MEM2MEM Memory to memory mode
This bit is set and cleared by software.
0:Memory to memory mode disabled
1:Memory to memory mode enabled
13:12 PL[1:0] Channel priority level
These bits are set and cleared by software.
00:Low
01:Medium
10:High
11:Very high
11:10 MSIZE[1:0] Memory size
These bits are set and cleared by software
00:8-bits
01:16-bits
10:32-bits
11:Reserved
9:8 PSIZE[1:0] Peripheral size
These bits are set and cleared by software
00:8-bits
01:16-bits
10:32-bits
11:Reserved
7 MINC Memory increment mode
This bit is set and cleared by software

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Fremont Micro Devices FT32F0xxx8 RM

0:Memory increment mode disabled


1:Memory increment mode enabled
6 PINC Peripheral increment mode
This bit is set and cleared by software.
0:Peripheral increment mode disabled
1:Peripheral increment mode enabled
5 CIRC Circular mode
This bit is set and cleared by software
0:Circular mode disabled
1:Circular mode enabled
4 DIR Data transfer direction
This bit is set and cleared by software
0:Read from peripheral
1:Read from memory
3 TEIE Transfer error interrupt enable
This bit is set and cleared by software
0:TE interrupt disabled
1:TE interrupt enabled
2 HTIE Half transfer interrupt enable
This bit is set and cleared by software.
0:HT interrupt disabled
1:HT interrupt enabled
1 TCIE Transfer complete interrupt enable
This bit is set and cleared by software.
0:TC interrupt disabled
1:TC interrupt enabled
0 EN Channel enable
This bit is set and cleared by software
0:Channel disabled
1:Channel enabled

11.4.4. DMA_CNDTRx(x=1..5)

Address offset:0x0C + 0d20 × (channel number - 1)


Reset value:0x0000 0000

Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0


31:24 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 — NDT[11:8]

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Fremont Micro Devices FT32F0xxx8 RM

Type RW RW RW RW RW RW RW RW
7:0 NDT[7:0]
Type RW RW RW RW RW RW RW RW

Bit Name Function


31:12 NA Reserved
11:0 NDT[11:0] Number of data to transfer
Number of data to be transferred (0 up to 4095). This register can only be
written when the channel is disabled. Once the channel is enabled, this
register is read-only, indicating the remaining bytes to be transmitted. This
register decrements after each DMA transfer.
Once the transfer is completed, this register can either stay at zero or be
reloaded automatically by the value previously programmed if the channel is
configured in auto-reload mode.
If this register is zero, no transaction can be served whether the channel is
enabled or not.

11.4.5. DMA_CPARx(x=1..5)

Address offset:0x10 + 0d20 × (channel number - 1)


Reset value:0x0000 0000
This register must not be written when the channel is enabled.

Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0


31:24 PA[31:24]
Type RW RW RW RW RW RW RW RW
23:16 PA[23:16]
Type RW RW RW RW RW RW RW RW
15:8 PA[15:8]
Type RW RW RW RW RW RW RW RW
7:0 PA[7:0]
Type RW RW RW RW RW RW RW RW

Bit Name Function


31:0 PA[31:0] Peripheral address
Base address of the peripheral data register from/to which the data will be
read/written.
When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically
aligned to a half- word address.
When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically
aligned to a word address

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Fremont Micro Devices FT32F0xxx8 RM

11.4.6. DMA_CMARx(x=1..5)

Address offset:0x14 + 0d20 × (channel number - 1)


Reset value:0x0000 0000
This register must not be written when the channel is enabled.

Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0


31:24 MA[31:24]
Type RW RW RW RW RW RW RW RW
23:16 MA[23:16]
Type RW RW RW RW RW RW RW RW
15:8 MA[15:8]
Type RW RW RW RW RW RW RW RW
7:0 MA[7:0]
Type RW RW RW RW RW RW RW RW

Bit Name Function


31:0 MA[31:0] Memory address
Base address of the memory area from/to which the data will be
read/written.
When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically
aligned to a half- word address.
When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically
aligned to a word address.

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Fremont Micro Devices FT32F0xxx8 RM

12. Interrupts and events

12.1. Nested vectored interrupt controller(NVIC)

12.1.1. Main features

 32 maskable interrupt channels (not including the sixteen ARM ® Cortex®-M0 interrupt lines)
 4 programmable priority levels (2 bits of interrupt priority are used)
 Low-latency exception and interrupt handling
 Power management control
 Implementation of System Control Registers

12.1.2. Interrupt and exception vectors

Table 12-1 Vector table


Type of
Position Priority Acronym Description Address
priority
— — — Reserved — 0x00000000
-3 fixed Reset Reset 0x00000004
-2 fixed NMI Non maskable interrupt. The RCC 0x00000008
Clock Security System (CSS) is
linked to the NMI vector.
-1 fixed HardFault Hardware fault 0x0000000C
3 settable SVCall System service call via SWI 0x0000002C
instruction
5 settable PendSV Pendable request for system service 0x00000038
6 settable SysTick System tick timer 0x0000003C
0 7 settable WWDG Window watchdog interrupt 0x00000040
1 8 settable PVD PVD interrupt (combined EXTI lines) 0x00000044
2 9 settable RTC RTC global interrupt 0x00000048
3 10 settable Flash Flash global interrupt 0x0000004C
4 11 settable RCC_CRS RCC and CRS global interrupts 0x00000050
5 12 settable EXTI0_1 EXTI Line[1:0] interrupts 0x00000054
6 13 settable EXTI2_3 EXTI Line[3:2] interrupts 0x00000058
7 14 settable EXTI4_15 EXTI Line[15:4] interrupts 0x0000005C
8 — — Reserved — 0x00000060
9 16 settable DMA_CH1 DMA channel 1 interrupt 0x00000064
10 17 settable DMA_CH2_3 DMA channel 2 and 3 interrupts 0x00000068

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Fremont Micro Devices FT32F0xxx8 RM

11 18 settable DMA_CH4_5 DMA channel 4 and 5 interrupts 0x0000006C


12 19 settable ADC_COMP ADC interrupts 0x00000070
13 20 settable TIM1_BRK_UP TIM1 break, update, trigger and 0x00000074
_TRG_COM commutation interrupt
14 21 settable TIM1_CC TIM1 capture compare interrupt 0x00000078
15 — — Reserved — 0x0000007C
16 23 settable TIM3 TIM3 global interrupt 0x00000080
17 24 settable TIM6 TIM6 global interrupt 0x00000084
18 — — Reserved — 0x00000088
19 27 settable TIM14 TIM14 global interrupt 0x0000008C
20 28 settable TIM15 TIM15 global interrupt 0x00000090
21 29 settable TIM16 TIM16 global interrupt 0x00000094
22 30 settable TIM17 TIM17 global interrupt 0x00000098
23 31 settable I2C1 I2C1 global interrupt 0x0000009C
24 32 settable I2C2 I2C2 global interrupt 0x000000A0
25 33 settable SPI1 SPI1 global interrupt 0x000000A4
26 34 settable SPI2 SPI2 global interrupt 0x000000A8
27 35 settable USART1 USART1 global interrupt 0x000000AC
28 36 settable USART2 USART2 global interrupt 0x000000B0
29 37 settable DIV Divider interrupt 0x000000B4
30 — — Reserved — 0x000000B8
31 38 settable USB USB global interrupt (combined with 0x000000BC
EXTI line 18)

12.2. Extended interrupts and events controller(EXTI)

The extended interrupts and events controller (EXTI) manages the external and internal asynchronous
events/interrupts and generates the event request to the CPU/Interrupt Controller and a wake-up request to
the Power Manager.

The EXTI allows the management of up to 28 external/internal event line

The active edge of each external interrupt line can be chosen independently, whilst for internal interrupt the
active edge is always the rising one. An interrupt could be left pending: in case of an external one, a status
register is instantiated and indicates the source of the interrupt; an event is always a simple pulse and it’s
used for triggering the core Wake-up. For internal interrupts, the pending status is assured by the generating
IP, so no need for a specific flag. Each input line can be masked independently for interrupt or event
generation, in addition the internal lines are sampled only in STOP mode. This controller allows also to
emulate the (only) external events by software, multiplexed with the corresponding hardware event line, by
writing to a dedicated register.

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Fremont Micro Devices FT32F0xxx8 RM

Rising edge Software


Falling edge Interrupt Pending
selection interrupt
selection mask request
register event
register register register
register

Rising
edge
detect

External events
Edge detect circuit

event

Event mask
register
Interrupt

Internal events
Rising edge
Stop mode
detect

Figure 12-1 EXTI block diagram

12.2.1. Main features

The EXTI main features are the following:


 Supports generation of up to 28 event/interrupt requests
 Independent mask on each event/interrupt line
 Automatic disable of internal lines when system is not in STOP mode
 Independent trigger for external event/interrupt line
 Dedicated status bit for external interrupt line
 Emulation for all the external event requests

12.2.2. Event management

FT32F0xxx8 is able to handle external or internal events in order to wake up the core (WFE). The wakeup
event can be generated either by:
1 Enabling an interrupt in the peripheral control register but not in the NVIC, and enabling the
SEVONPEND bit in the Cortex-M0 System Control register. When the MCU resumes from WFE, the
EXTI peripheral interrupt pending bit and the peripheral NVIC IRQ channel pending bit (in the NVIC
interrupt clear pending register) have to be cleared.
2 Or by configuring an external or internal EXTI line in event mode. When the CPU resumes from WFE, it
is not necessary to clear the peripheral interrupt pending bit or the NVIC IRQ channel pending bit as the
pending bit corresponding to the event line is not set.

12.2.3. Functional description

For the external interrupt lines, to generate the interrupt, the interrupt line should be configured and

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Fremont Micro Devices FT32F0xxx8 RM

enabled.This is done by programming the EXTI_RTSR and EXTI_FTSR register with the desired edge
detection and by enabling the interrupt request by writing a ‘1’ to the corresponding bit in the EXTI_IMR
interrupt mask register.

For the internal interrupt lines, the active edge is always the rising edge, the interrupt is enabled by default in
the interrupt mask register and there is no corresponding pending bit in the pending register.

To generate the event, the event line should be configured and enabled. This is done by programming the
EXTI_RTSR and EXTI_FTSR register with the desired edge detection and by enabling the interrupt request
by writing a ‘1’ to the corresponding bit in the EXTI_IMR interrupt mask register.

For the external lines, an interrupt/event request can also be generated by software by writing a ‘1’ in the
software interrupt/event register.

Hardware interrupt selection


To configure a line as interrupt source, use the following procedure:
1. Configure the corresponding mask bit in the EXTI_IMR register.
2. Configure the Trigger Selection bits of the Interrupt line (EXTI_RTSR and EXTI_FTSR)
3. Configure the enable and mask bits that control the NVIC IRQ channel mapped to the EXTI so that an
interrupt coming from one of the EXTI line can be correctly acknowledged.

Hardware event selection:


To configure a line as event source, use the following procedure:
1. Configure the corresponding mask bit in the EXTI_EMR register.
2. Configure the Trigger Selection bits of the Event line (EXTI_RTSR and EXTI_FTSR)

Software interrupt/event selection:


Any of the external lines can be configured as software interrupt/event lines. The following is the procedure
to generate a software interrupt:
1. Configure the corresponding mask bit (EXTI_IMR, EXTI_EMR)
2. Set the required bit of the software interrupt register (EXTI_SWIER)

12.2.4. External and internal interrupt/event line mapping

The GPIOs are connected to the 16 external interrupt/event lines in the following manner:

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Fremont Micro Devices FT32F0xxx8 RM

EXTI0[3:0] EXTI4[3:0] EXTI8[3:0]

PA0 PA4
PA8
PB0 PB4
EXTI0 EXTI4 PB8 EXTI8
PC0 PC4
PC8
PF0 PF4

EXTI1[3:0] EXTI5[3:0]

PA1 PA5
PB1 PB5
EXTI1 EXTI5
PC1 PC5
PF1 PF5

EXTI2[3:0] EXTI6[3:0] EXTI14[3:0]

PA2 PA6
PA14
PB2 PB6
EXTI2 EXTI6 PB14 EXTI14
PC2 PC6
PC14
PD2 PF6

EXTI3[3:0] EXTI7[3:0] EXTI15[3:0]

PA3 PA7
PA15
PB3 PB7
EXTI3 EXTI7 PB15 EXTI15
PC3 PC7
PC15
PF7

Figure 12-2 External interrupt/event GPIO mapping


EXTI1[3:0]~EXTI15[3:0] are in the SYSCFG_EXTICRx regiaster, x means 1~4.
The remaining lines are connected as follow:
 EXTI line 16 is connected to the PVD output
 EXTI line 17 is connected to the RTC Alarm event
 EXTI line 18 is connected to the internal USB wakeup event
 EXTI line 19 is connected to the RTC Tamper and TimeStamp events
 EXTI line 20 is reserved (internally held low)
 EXTI line 21 is connected to the Comparator 1 output
 EXTI line 22 is connected to the Comparator 2 output
 EXTI line 23 is connected to the Comparator 3 output
 EXTI line 24 is reserved (internally held low)
 EXTI line 25 is reserved (internally held low)

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Fremont Micro Devices FT32F0xxx8 RM

 EXTI line 26 is reserved (internally held low)


 EXTI line 27 is reserved (internally held low)
 EXTI line 28 is reserved (internally held low)
 EXTI line 29 is reserved (internally held low)
 EXTI line 30 is reserved (internally held low)
 EXTI line 31 is reserved (internally held low)

12.3. EXTI register map


31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10
offset Register

0
EXTI_IMR IMR[31:0]
0x00
Reset 0 1 1 1 1 1 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EXTI_EMR EMR[31:0]
0x04
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RTSR[22]

RTSR[22]

RTSR[21]

RTSR[19]

EXTI_RTSR RTSR[17:0]
-

0x08

Reset x x x x x x x x 0 0 0 x 0 x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FTSR[22]

FTSR[22]

FTSR[21]

FTSR[19]

EXTI_FTSR FTSR[17:0]
-

0x0C

Reset x x x x x x x x 0 0 0 x 0 x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SWIER[22]

SWIER[22]

SWIER[21]

SWIER[19]

EXTI_SWIER SWIER[17:0]
-

0x10

Reset x x x x x x x x 0 0 0 x 0 x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PR[22]

PR[22]

PR[21]

PR[19]

EXTI_PR PR[17:0]
-

0x14
Reset x x x x x x x x 0 0 0 x 0 x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

12.3.1. EXTI_IMR

Address offset:0x00
Reset value:0x7F04 0000
Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 IMR[31:24]
Type RW RW RW RW RW RW RW RW
23:16 IMR[23:16]
Type RW RW RW RW RW RW RW RW
15:8 IMR[15:8]
Type RW RW RW RW RW RW RW RW
7:0 IMR[7:0]
Type RW RW RW RW RW RW RW RW

Bit Name Function


31:0 IMR[31:0] Interrupt mask on external/internal line x, x means 31~0
0:Interrupt request from Line x is masked
1:Interrupt request from Line x is not masked

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12.3.2. EXTI_EMR

Address offset:0x04
Reset value:0x0000 0000
Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 EMR[31:24]
Type RW RW RW RW RW RW RW RW
23:16 EMR[23:16]
Type RW RW RW RW RW RW RW RW
15:8 EMR[15:8]
Type RW RW RW RW RW RW RW RW
7:0 EMR[7:0]
Type RW RW RW RW RW RW RW RW

Bit Name Function


31:0 EMR[31:0] Event mask on external/internal line x , x means 31~0
0:Event request from Line x is masked
1:Event request from Line x is not masked

12.3.3. EXTI_RTSR

Address offset:0x08
Reset value:0x0000 0000
Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 RTSR[23] RTSR[22] RTSR[21] — RTSR[19] — RTSR[17 RTSR[16]
]
Type RW RW RW RO-0 RW RO-0 RW RW
15:8 RTSR[15:8]
Type RW RW RW RW RW RW RW RW
7:0 RTSR[7:0]
Type RW RW RW RW RW RW RW RW

Bit Name Function


31:24 NA Reserved
23 RTSR[23] Rising trigger event configuration bit of line 23
0:Rising trigger disabled (for Event and Interrupt) for input line
1:Rising trigger enabled (for Event and Interrupt) for input line
22 RTSR[22] Rising trigger event configuration bit of line 22

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0:Rising trigger disabled (for Event and Interrupt) for input line
1:Rising trigger enabled (for Event and Interrupt) for input line
21 RTSR[21] Rising trigger event configuration bit of line 21
0:Rising trigger disabled (for Event and Interrupt) for input line
1:Rising trigger enabled (for Event and Interrupt) for input line
20 NA Reserved
19 RTSR[19] Rising trigger event configuration bit of line 19
0:Rising trigger disabled (for Event and Interrupt) for input line
1:Rising trigger enabled (for Event and Interrupt) for input line
18 NA Reserved
17:0 RTSR[17:0] Rising trigger event configuration bit of line x (x = 17 to 0)
0:Rising trigger disabled (for Event and Interrupt) for input line
1:Rising trigger enabled (for Event and Interrupt) for input line

12.3.4. EXTI_FTSR

Address offset:0x0C
Reset value:0x0000 0000
Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 FTSR[23] FTSR[22] FTSR[21] — FTSR[19] — FTSR[17] FTSR[16]
Type RW RW RW RO-0 RW RO-0 RW RW
15:8 FTSR[15:8]
Type RW RW RW RW RW RW RW RW
7:0 FTSR[7:0]
Type RW RW RW RW RW RW RW RW

Bit Name Function


31:24 NA Reserved
23 FTSR[23] Falling trigger event configuration bit of line 23
0: Falling trigger disabled (for Event and Interrupt) for input line
1: Falling trigger enabled (for Event and Interrupt) for input line
22 FTSR[22] Falling trigger event configuration bit of line 22
0: Falling trigger disabled (for Event and Interrupt) for input line
1: Falling trigger enabled (for Event and Interrupt) for input line
21 FTSR[21] Falling trigger event configuration bit of line 21
0: Falling trigger disabled (for Event and Interrupt) for input line
1: Falling trigger enabled (for Event and Interrupt) for input line
20 NA Reserved
19 FTSR[19] Falling trigger event configuration bit of line 19
0: Falling trigger disabled (for Event and Interrupt) for input line

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1: Falling trigger enabled (for Event and Interrupt) for input line
18 NA Reserved
17:0 FTSR[17:0] Falling trigger event configuration bit of line x (x = 17 to 0)
0: Falling trigger disabled (for Event and Interrupt) for input line
1: Falling trigger enabled (for Event and Interrupt) for input line

12.3.5. EXTI_SWIER

Address offset:0x10
Reset value:0x0000 0000
Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 SWIER[23] SWIER[22] SWIER[21] — SWIER[19] — SWIER[1 SWIER[16]
7]
Type RW RW RW RO-0 RW RO-0 RW RW
15:8 SWIER[15:8]
Type RW RW RW RW RW RW RW RW
7:0 SWIER[7:0]
Type RW RW RW RW RW RW RW RW

Bit Name Function


31:24 NA Reserved
23 SWIER[23] Software interrupt on line 23
If the interrupt is enabled on this line in the EXTI_IMR, writing a ‘1’ to this bit
when it is at ‘0’ sets the corresponding pending bit in EXTI_PR resulting in
an interrupt request generation. This bit is cleared by clearing the
corresponding bit of EXTI_PR (by writing a ‘1’ to the bit)
22 SWIER[22] Software interrupt on line 22
If the interrupt is enabled on this line in the EXTI_IMR, writing a ‘1’ to this bit
when it is at ‘0’ sets the corresponding pending bit in EXTI_PR resulting in
an interrupt request generation. This bit is cleared by clearing the
corresponding bit of EXTI_PR (by writing a ‘1’ to the bit)
21 SWIER[21] Software interrupt on line 21
If the interrupt is enabled on this line in the EXTI_IMR, writing a ‘1’ to this bit
when it is at ‘0’ sets the corresponding pending bit in EXTI_PR resulting in
an interrupt request generation. This bit is cleared by clearing the
corresponding bit of EXTI_PR (by writing a ‘1’ to the bit)
20 NA Reserved
19 SWIER[19] Software interrupt on line 19
If the interrupt is enabled on this line in the EXTI_IMR, writing a ‘1’ to this bit

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when it is at ‘0’ sets the corresponding pending bit in EXTI_PR resulting in


an interrupt request generation. This bit is cleared by clearing the
corresponding bit of EXTI_PR (by writing a ‘1’ to the bit)
18 NA Reserved
17:0 SWIER[17:0] Software interrupt on line x (x = 17 to 0)
If the interrupt is enabled on this line in the EXTI_IMR, writing a ‘1’ to this bit
when it is at ‘0’ sets the corresponding pending bit in EXTI_PR resulting in
an interrupt request generation. This bit is cleared by clearing the
corresponding bit of EXTI_PR (by writing a ‘1’ to the bit)

12.3.6. EXTI_PR

Address offset:0x14
Reset value:0x0000 0000
Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 PR[23] PR[22] PR[21] — PR[19] — PR[17] PR [16]
Type RW RW RW RO-0 RW RO-0 RW RW
15:8 PR [15:8]
Type RW RW RW RW RW RW RW RW
7:0 PR [7:0]
Type RW RW RW RW RW RW RW RW

Bit Name Function


31:24 NA Reserved
23 PR[23] Pending bit on line 23
0:No trigger request occurred
1:selected trigger request occurred
This bit is set when the selected edge event arrives on the external interrupt
line. This bit is cleared by writing a 1 to the bit.
22 PR[22] Pending bit on line 22
0:No trigger request occurred
1:selected trigger request occurred
This bit is set when the selected edge event arrives on the external interrupt
line. This bit is cleared by writing a 1 to the bit.
21 PR [21] Pending bit on line 21
0:No trigger request occurred
1:selected trigger request occurred
This bit is set when the selected edge event arrives on the external interrupt
line. This bit is cleared by writing a 1 to the bit.

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20 NA Reserved
19 PR [19] Pending bit on line 19
0:No trigger request occurred
1:selected trigger request occurred
This bit is set when the selected edge event arrives on the external interrupt
line. This bit is cleared by writing a 1 to the bit.
18 NA Reserved
17:0 PR [17:0] Pending bit on line x (x = 17 to 0)
0:No trigger request occurred
1:selected trigger request occurred
This bit is set when the selected edge event arrives on the external interrupt
line. This bit is cleared by writing a 1 to the bit.

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13. Analog-to-digital converter(ADC)

13.1. Introduction

The 12-bit ADC is a successive approximation analog-to-digital converter. It has up to 20 multiplexed


channels allowing it to measure signals from 16 external and 4 internal sources. A/D conversion of the
various channels can be performed in single, continuous, scan or discontinuous mode. The result of the
ADC is stored in a left-aligned or right-aligned 16-bit data register. And it also provide 3 internal reference
voltage to be selected.

13.2. ADC main features

 High performance
─ 12-bit, 10-bit, 8-bit or 6-bit configurable resolution
─ ADC conversion time: 1.0 µs for 12-bit resolution (1 MHz), 0.93 µs conversion time for 10-bit
resolution, faster conversion times can be obtained by lowering resolution.
─ Self-calibration
─ Programmable sampling time
─ Data alignment with built-in data coherency
─ DMA support
─ Precisely control the sample stop time
─ Flexible hardware trigger configuration
─ Acquire maximum 3 channel conversion value at the same time(ADC_INx、IOSH1、IOSH2)
 Low-power
─ Application can reduce PCLK frequency for low-power operation while still keeping optimum ADC
performance. For example, 1.0 µs conversion time is kept, whatever the frequency of PCLK
─ Wait mode: prevents ADC overrun in applications with low frequency PCLK
─ Auto off mode: ADC is automatically powered off except during the active conversion phase. This
dramatically reduces the power consumption of the ADC.
 Analog input channels
─ 16 external analog inputs
─ 1 channel for internal temperature sensor(VTS)
─ 1 channel for internal reference voltage(VREFINT)
─ 1 I/O Sample and hold circuits(VIOSHx)
─ 1 Operational amplifiers(VOPx)
 Start-of-conversion can be initiated:
─ By software
─ By hardware triggers with configurable polarity (internal timer events from TIM1, TIM3, TIM14,
TIM15, TIM16 and TIM17)
 Conversion modes

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─ Can convert a single channel or can scan a sequence of channels.


─ Single mode converts selected inputs once per trigger
─ Continuous mode converts selected inputs continuously
─ Discontinuous mode
 Interrupt generation at the end of sampling, end of conversion, end of sequence conversion, and in
case of analog watchdog or overrun events
 Analog watchdog
 Configurable ADC reference voltage
─ VDDA as ADC reference voltage
─ Selectable ADC internal reference voltage: 2.5V
 ADC supply requirements:2.4 V to 5.5 V
 ADC input range:VSSA ≤ VIN ≤ VREF+

13.3. ADC pins and internal signals

Table 13-1 ADC internal signal


Internal signal
Signal type Description
name
TRGX Input ADC conversion triggers
VTS Input Internal temperature sensor output voltage
VREFINT Input Internal voltage reference output voltage
VIOSHx Input I/O Sample and hold circuit output voltage
VOPx Input Operational amplifier output voltage

Table 13-2 ADC pins


Name Signal type Remarks
VDDA Input, analog power Analog power supply and positive reference voltage for
supply the ADC, VDDA ≥ VDD
VSSA Input, analog supply Ground for analog power supply. Must be at VSS
ground potential
ADC_IN[15:0] Analog input signals 16 analog input channels

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13.4. ADC functional description

Figure 13-1 shows the ADC block diagram and Table 13-2 gives the ADC pin description.
VDDA VSSA

VREFSEL[1:0]
Internal reference
voltage selection

Reserved
AREADY CPU
EOSMP ADC interrupt
EOSEQ IRQ
2.5 V
EOC
OVR
VREFEN AWD master
Internal reference
A
voltage enable DATA[11:0 AHB H
AUTOFF to slave DMA
B
SCANDIR Auto off mode APB master
Up/down ADEN/ADDIS

CH_SEL[21:0] APB
CONT VREF+ VDD VREF- interface DMA request
Single/cont. Supply and reference
ADCAL
Self- DMAEN
VIOSHx calibration DMACFG
VOPx Input
selecion
VREFINT SMP[2:0] VIN SAR ADC
and scan
VTS control Sampling
ADC_IN[15:0] time
Analog input
channels AWD
Converted Analog
data watchdog
start

Start and
stop control AWDEN
ALIGN AWDSGL
AUTODLY Left/right AWDCH[4:0]
Auto-delayed RES[1:0] LT[11:0]
conv. ADSTART 12, 10, 8, 6bit
ADSTP HT[11:0]
Software
EXTSEL[2:0] trigger
Trigger
source
selection EXTEN[1:0] Hard
Trigger enable and ware
edge selection trigg Sample &hold
TIM1_TRGO DISCEN circuit
er
TIM1_CC4 Discontinuous
mode
TIM3_TRGO
TIM15_TRGO
IOSHx_SMPEN
IOSHx_AMPEN
PBx
+
VOPx
OP VIOSHx
EXTSEL[2:0]

IOSHx_SMPSEL

Figure 13-1 ADC block diagram

13.4.1. Calibration(ADCAL)

The ADC has a calibration feature. During the procedure, the ADC calculates a calibration factor which is
internally applied to the ADC until the next ADC power-off. The application must not use the ADC during
calibration and must wait until it is complete.
Calibration should be performed before starting A/D conversion. It removes the offset error which may vary
from chip to chip due to process variation.
The calibration is initiated by software by setting bit ADCAL=1. Calibration can only be initiated when the
ADC is disabled (when ADEN=0). ADCAL bit stays at 1 during all the calibration sequence. It is then cleared
by hardware as soon the calibration completes. After this, the calibration factor can be read from the

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ADC_DR register (from bits 6 to 0).


The internal analog calibration is kept if the ADC is disabled (ADEN=0). When the ADC operating conditions
change (VDDA changes are the main contributor to ADC offset variations and temperature change to a
lesser extend), it is recommended to re-run a calibration cycle.
The calibration factor is lost each time power is removed from the ADC (for example when the product
enters STANDBY mode).

Calibration software procedure


1. Ensure that ADEN=0 and DMAEN=0;
2. Set ADCAL=1;
3. Wait until ADCAL=0;
4. The calibration factor can be read from bits 6:0 of ADC_DR.

tCAB

ADCAL

ADC State OFF Startup CALIBRATE OFF

ADC_DR[6:0] 0x00 CALIBRATION FACTOR

by S/W by H/W

Figure 13-2 ADC calibration

13.4.2. ADC on-off control(ADEN,ADDIS,ADRDY)

At MCU power-up, the ADC is disabled and put in power-down mode (ADEN=0).
As shown in Figure 13-3, the ADC needs a stabilization time of tSTAB before it starts converting accurately.
Two control bits are used to enable or disable the ADC:
 Set ADEN=1 to enable the ADC. The ADRDY flag is set as soon as the ADC is ready for operation.
 Set ADDIS=1 to disable the ADC and put the ADC in power down mode. The ADEN and ADDIS bits are
then automatically cleared by hardware as soon as the ADC is fully disabled.
Conversion can then start either by setting ADSTART=1 (Refer to section 13.5 Conversion on external
trigger and trigger polarity (EXTMOD, EXTEN, EXTSEL, RTENx, FTENx, EXTDLY)or when an external
trigger event occurs if triggers are enabled.

Follow this procedure to enable the ADC:


1. Clear the ADRDY bit in ADC_ISR register by programming this bit to ‘1’.
2. Set ADEN=1 in the ADC_CR register;
3. Wait until ADRDY=1 in the ADC_ISR register (ADRDY is set after the ADC startup time). This can be
handled by interrupt if the interrupt is enabled by setting the ADRDYIE bit in the ADC_IER register.

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Follow this procedure to disable the ADC:


1. Check that ADSTART=0 in the ADC_CR register to ensure that no conversion is ongoing. If required,
stop any ongoing conversion by writing 1 to the ADSTP bit in the ADC_CR register and waiting until this
bit is read at 0.
2. Set ADDIS=1 in the ADC_CR register.
3. If required by the application, wait until ADEN=0 in the ADC_CR register, indicating that the ADC is fully
disabled (ADDIS is automatically reset once ADEN=0).
4. Clear the ADRDY bit in ADC_ISR register by programming this bit to ‘1’ (optional).
Note: ADEN bit can not be set in 4 ADC clock cycles after ADCAL cleared by hardware.

ADEN

tSTAB
ADRDY

ADDIS

ADC state OFF Startup RDY CONVERTING CH RDY REQ-OFF OFF

by S/W by H/W

Figure 13-3 Enabling/disabling the ADC

Note: In auto-off mode (AUTOFF=1) the power-on/off phases are performed automatically, by hardware and
the ADRDY flag is not set.

13.4.3. ADC clock(CKMODE)

The ADC has a dual clock-___domain architecture, so that the ADC can be fed with a clock (ADC asynchronous
clock) independent from the APB clock (PCLK).

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RCC ADITF
(Reset & Clock controller) APB
PCLK interface
Bits
CKMODE[1:0] of
ADC_CFGR2
Analog
/2 or /4 Others ADC_CK Analog
ADC
00
ADC
asynchronous Bits
clock CKMODE[1:0] of
ADC_CFGR2

Figure 13-4 ADC clock scheme

1. Refer to Section7: RCC to see how PCLK and ADC asynchronous clock are enable

The input clock of the analog ADC can be selected between two different clock sources(See Figure 13-4 to
see how PCLK and the ADC asynchronous clock are enabled):
a) The ADC clock can be a specific clock source, named “ADC asynchronous clock “which is independent
and asynchronous with the APB clock.
Refer to RCC Section for more information on generating this clock source.
To select this scheme, bits CKMODE[1:0] of the ADC_CFGR2 register must be reset.
b) The ADC clock can be derived from the APB clock of the ADC bus interface, divided by a programmable
factor (2 or 4) according to bits CKMODE[1:0].
To select this scheme, bits CKMODE[1:0] of the ADC_CFGR2 register must be different from “00”.
Option a) has the advantage of reaching the maximum ADC clock frequency whatever the APB clock
scheme selected.
Option b) has an uncertainty of the trigger instant is added by the resynchronizations between the two clock
domains.
Table 13-3 Latency between trigger and start of conversion
ADC clock source CKMODE[1:0] Latency between the trigger event and the start of conversion

Dedicated 14MHz 00
clock
Latency is not deterministic(jitter,2~3 * TADC)
PCLK divided by 2 01
PCLK divided by 4 10

13.4.4. Configuring the ADC

Software must write to the ADCAL and ADEN bits in the ADC_CR register if the ADC is disabled (ADEN
must be 0).
Software must only write to the ADSTART and ADDIS bits in the ADC_CR register only if the ADC is enabled
and there is no pending request to disable the ADC (ADEN = 1 and ADDIS = 0).
For all the other control bits in the ADC_IER, ADC_CFGRi, ADC_SMPR, ADC_TR, ADC_CHSELR,

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ADC_ETCR, ADC_RTENR, ADC_FTENR, ADC_CCR and ADC_CR2 registers, software must only write to
the configuration control bits if the ADC is enabled (ADEN = 1) and if there is no conversion ongoing
(ADSTART = 0).
Software must only write to the ADSTP bit in the ADC_CR register if the ADC is enabled (and possibly
converting) and there is no pending request to disable the ADC (ADSTART = 1 and ADDIS = 0)
Note: There is no hardware protection preventing software from making write operations forbidden by the
above rules. If such a forbidden write access occurs, the ADC may enter an undefined state. To recover
correct operation in this case, the ADC must be disabled (clear ADEN=0 and all the bits in the ADC_CR
register).

13.4.5. Channel selection(CHSEL,SCANDIR)

There are up to 20 multiplexed channels:


 16 analog inputs from GPIO pins (ADC_IN0...ADC_IN15)
 4 internal analog inputs(Temperature Sensor, Internal Reference Voltage, I/O Sample and hold circuit，
Operational amplifier)
 I/O Sample and hold circuit input can be select to PB1(same as ADC_IN9) or the output of Operational
amplifier1.
It is possible to convert a single channel or to automatically scan a sequence of channels.
The sequence of the channels to be converted must be programmed in the ADC_CHSELR channel
selection register: each analog input channel has a dedicated selection bit (CHSEL0...CHSEL21).
The order in which the channels will be scanned can be configured by programming the bit SCANDIR bit in
the ADC_CFGR1 register:
 SCANDIR=0: forward scan Channel 0 to Channel 21
 SCANDIR=1: backward scan Channel 21 to Channel 0

VTS, VREFINT, VOPx, VIOSHx internal channels


The temperature sensor is connected to channel ADC_IN16. The internal voltage reference VREFINT is
connected to channel ADC_IN17. The I/O Sample and hold circuit VSH is connected to channel ADC_IN18.
The Operational amplifier is connected to channel ADC_IN19.

13.4.6. Programmable sampling time(SMP)

Before starting a conversion, the ADC needs to establish a direct connection between the voltage source to
be measured and the embedded sampling capacitor of the ADC. This sampling time must be enough for the
input voltage source to charge the sample and hold capacitor to the input voltage level.
Having a programmable sampling time allows to trim the conversion speed according to the input resistance
of the input voltage source.
The ADC samples the input voltage for a number of ADC clock cycles that can be modified using the
SMP[2:0] bits in the ADC_SMPR register.

The total conversion time is calculated as follows:

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tCONV = Sampling time + 12.5 ADC clock cycles


Example:
ADC_CLK = 14MHz and a sampling time of 1.5 ADC clock cycles:
tCONV = 1.5 + 12.5 = 14 ADC clock cycles = 1 μs
The ADC indicates the end of the sampling phase by setting the EOSMP flag.

ADC sampling can precisely stopped by configure TRGDISSMP bit, which can avoid the uncertainty of clock
___domain crossing. For more details please refer to the timing of I/O Sample and hold circuit

TRGDISSMP=0,
Programming sample time is general for every channel. The sampling time can be change by software at
each conversion if the application need.

TRGDISSMP=1,
For specify the sample top time of the measuring voltage source, the trigger source can stop the sample at a
fixed and certain time by set TRGDISSMP.
Software trigger will stop sampling immediately. Hardware trigger will stop sampling after the delay time set
by EXTDLY[9:0], and it can stopped immediately by set EXTDLY[9:0]=0.
The sample time of the first channel after triggering is forced to 1.5 × ADC clock cycles, but it is not sampling
in this stage because ADC sample is stopped. The programming sample time is effected excpt the first
channel.

13.4.7. Single conversion mode(CONT=0)

In Single conversion mode, the ADC performs a single sequence of conversions, converting all the channels
once. This mode is selected when CONT=0 in the ADC_CFGR1 register. Conversion is started by either:
 Setting the ADSTART bit in the ADC_CR register
 Hardware trigger event
Inside the sequence, after each conversion is complete:
 The converted data are stored in the 16-bit ADC_DR register, the IOSHx channel data are stored in the
ADC_IOSHxDR register.
 The EOC (end of conversion) flag is set
 An interrupt is generated if the EOCIE bit is set
After the sequence of conversions is complete:
 The EOSEQ (end of sequence) flag is set
 An interrupt is generated if the EOSEQIE bit is set
Then the ADC stops until a new external trigger event occurs or the ADSTART bit is set again.
Note: To convert a single channel, program a sequence with a length of 1.

13.4.8. Continuous conversion mode(CONT=1)

In continuous conversion mode, when a software or hardware trigger event occurs, the ADC performs a

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sequence of conversions, converting all the channels once and then automatically re-starts and
continuously performs the same sequence of conversions. This mode is selected when CONT=1 in the
ADC_CFGR1 register. Conversion is started by either:
 Setting the ADSTART bit in the ADC_CR register
 Hardware trigger event
Inside the sequence, after each conversion is complete:
 The converted data are stored in the 16-bit ADC_DR register, the IOSHx channel data are stored in the
ADC_IOSHxDR register.
 The EOC (end of conversion) flag is set
 An interrupt is generated if the EOCIE bit is set
After the sequence of conversions is complete:
 The EOSEQ (end of sequence) flag is set
 An interrupt is generated if the EOSEQIE bit is set
Then, a new sequence restarts immediately and the ADC continuously repeats the conversion sequence.

Note:To convert a single channel, program a sequence with a length of 1.


It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to
set both bits DISCEN=1 and CONT=1.

13.4.9. Starting conversions(ADSTART)

Software starts ADC conversions by setting ADSTART=1


When ADSTART is set, the conversion:
 Starts immediately if EXTMOD=0 and EXTEN=00 (software trigger)
 At the next active edge of the selected hardware trigger if EXTMOD=1 or EXTEN≠00
The ADSTART bit is also used to indicate whether an ADC operation is currently ongoing. It is possible to
re-configure the ADC while ADSTART=0, indicating that the ADC is idle.
The ADSTART bit is cleared by hardware:
 In single mode with software trigger(CONT=0,EXTMOD=0,EXTEN=00)
─ At any end of conversion sequence(EOSEQ=1)
 In discontinuous mode triggered by software(CONT=0,DISCEN=1,EXTMOD=0,EXTEN=00)
─ At the end of conversion(ECO=1)
 In all cases(CONT=X,EXTMOD=X,EXTEN=XX)
─ After execution of the ADSTP procedure invoked by software(See section 13.4.11:stopping an
ongoing conversion(ADSTP))
Note: In continuous mode (CONT=1), the ADSTART bit is not cleared by hardware when the EOSEQ flag is
set because the sequence is automatically relaunched.
When hardware trigger is selected in single mode(CONT=0,EXTMOD=1 or EXTEN≠00), ADSTART is not
cleared by hardware when the EOSEQ flag is set. This avoids the need for software having to set the
ADSTART bit again and ensures the next trigger event is not missed.

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13.4.10. Timing

The elapsed time between the start of a conversion and the end of conversion is the sum of the configured
sampling time plus the successive approximation time depending on data resolution:
tADC = tSMPL + tSAR = [1.5 |min + 12.5 |12bit] × tADC_CLK
tADC = tSMPL + tSAR = [107.1 ns |min + 892.8 ns |12bit] = 1 μs |min (fADC_CLK = 14 MHz)

ADC state RDY SAMPLING CH(N) CONVERTING CH(N) SAMPLING CH(N+1)

Analog channel CH(N) CH(N+1)

Internal S/H Sample AIN(N) Hold AIN(N) Sample AIN(N+1)

tSMPL(1) tSAR(2)

ADSTART set by SW

EOSMP set by HW cleared by SW

EOC set by HW cleared by SW

ADC_DR DATA(N-1) DATA(N)

(1) tSMPL depends on SMP[2:0]


(2) tSAR depends on RES[2:0]

Figure 13-5 Analog to digital conversion time

ADSTART(1)

tLATENCY(2)

ADC state Ready S0 Conversion 0 S1 Conversion 1 S2 Conversion 2 S3 Conversion 3

WLATENCY(3) WLATENCY(3) WLATENCY(3)

ADC_DR Data 0 Data 1 Data 2

(1) TRGDISSMP=0
(2) Trigger latency（Refer to datasheet for more details）
(3)ADC_DR register write latency（Refer to datasheet for more details）

Figure 13-6 ADC conversion timings

13.4.11. Stopping an ongoing conversion(ADSTP)

The software can decide to stop any ongoing conversions by setting ADSTP=1 in the ADC_CR register.
This will reset the ADC operation and the ADC will be idle, ready for a new operation.

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When the ADSTP bit is set by software, any ongoing conversion is aborted and the result is discarded
(ADC_DR register is not updated with the current conversion).
The scan sequence is also aborted and reset (meaning that restarting the ADC would re- start a new
sequence).
Once this procedure is complete, the ADSTP and ADSTART bits are both cleared by hardware and the
software must wait until ADSTART=0 before starting new conversions.

ADC state RDY SAMPLING CH(N) CONVERTING CH(N) RDY

ADSTART set by SW cleared by HW

ADSTP set by SW cleared by HW

ADC_DR DATA N-1

Figure 13-7 Stopping an ongoing conversion

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13.4.12. I/O Sample and hold


circuits(IOSHx_SMPEN,IOSHx_AMPEN)

The I/O Sample and hold circuits mainly for measure the coefficient of the voltage divider circuit because the
ADC cannot measure immediately.
The I/O Sample and hold circuits need to built a connection between measured voltage source and
embedded smaple capacitance before starting holding(IOSHx_SMPEN=1,IOSHx_AMPEN=1). The sample
time should be enough to charge the sample and hold capacitance to the input voltage level according to the
input resistance. The sampled voltage will be held until the next sampling, and the conversion should be
proceed during this time.

Note: The input voltage of I/O Sample and hold circuit is limited, for more details please refer to the
characteristic table in datasheet.

The coefficient of the voltage divider circuit as shown below

IO_SMPEN IO_AMPEN ADC1


EOSMP

IOSH EOC

PB1 VIOSH
Sample Hold ADC_IN18
VIN VSAMPLE ADC_DR
R1 Sample/Hold Convert
PB0
VIN ADC_IN8

R2

Figure 13-8 Voltage divider circuit

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ADEN
tSTAB(1)

ADRDY set by HW cleared by SW

EXTEN 00

CONT

DISCEN

WAIT

AUTOFF

CHSEL 0x00040100

IOSH_AMPEN
tIOSH_SAMP(2) tIOSH_HOLD(3)

IOSH_SMPEN set by SW cleared by SW

VIOSH SAMPLING HOLDING

ADSTART

EOSMP set by HW cleared by SW

EOC set by HW cleared by SW

EOSEQ
tS(5) 12.5 * TAD tS_iosh(4) 12.5 * TAD

ADC state OFF Startup RDY SAMPLING (CH8) CONVERTING (CH8) SAMPLING (CH18) CONVERTING (CH18) RDY

Analog channel ADC_IN8 ADC_IN18 ADC_IN8

ADC_DR DATA8 DATA18

1. ADC stable time


2. IO sample and hold circuit output sample time
3. IO sample and hold circuit hold time (after sampling)
4. IO sample and hold circuit output to ADC sample time
5. ADC_VIN8 (PB0) output to ADC sample time
（For more details please refer to datasheet）

Figure 13-9 IO Sample and hold circuit timing

Procedure of I/O Sample and hold circuit:

Configure
1. Configure PB0, PB1 as analog input port;
2. Set ADC_CR.ADEN=1, and wait the ADC start stable time (tSTAB);
3. Configure ADC in single mode, no wait state, no auto shutdown, store the old data when the data is
overflow, scan sequence is CH8->CH18, configure ADC_CFGR1 &= ~(0x0001EC04)、 ADC_CHSELR
= 0x00040100;
4. ADC clock and ADC sample time should accord to application requirement and should satisfied 3
sample time which are defined in datasheet: sample time of ADC channel(PB0) (t S), IO(PB1) voltage
sample time(tIOSH_SAMP), ADC sample time of I/O Sample and hold circuit output (tS_iosh);
5. Set ADC_CR2 |= 0x00000300 to initiate I/O Sample and hold circuit and IO(PB1) voltage sample;
6. Set ADC_CR.ADSTART=1 to initiate ADC single mode (CH7->CH20->CH21);
7. Then should wait ADC_ISR.EOSMP=1, set ADC_CR2.IOSH_SMPEN=0 to hold PB1 voltage;

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8. Wait ADC_ISR.EOC=1,read ADC result of PB0(CH8) from ADC_DR;


9. Wait ADC_ISR.EOC=1 again, read ADC result of PB1(CH18) from ADC_DR;
Note: The time of I/O Sample and hold circuit stop sampling(ADC_CR2.IOSHx_SMPEN=0) to
ADC_VIN18 stop sample should smaller than I/O Sample and hold circuit hold time (tIOSH_HOLD);
10. The coefficient of the voltage divider circuit can be calculated by two ADC result;
11. If the coefficient of the voltage divider needed to update, EOSMP, EOC should be cleared, and repeat
procedure 5-10;
Note: software can polling the EOSMP or EOSEQ bit or by using the ADC interrupt.

13.5. Conversion on external trigger and trigger polarity


(EXTEN, EXTSEL)

A conversion or a sequence of conversion can be triggered either by software or by an external event (for
example timer capture). If the EXTEN[1:0] control bits are not equal to “00”, then external events are able to
trigger a conversion with the selected polarity. The trigger selection is effective once software has set bit
ADSTART=1.
Any hardware triggers which occur while a conversion is ongoing are ignored.
If bit ADSTART=0, any hardware triggers which occur are ignored.

Table 13-4 provides the correspondence between the EXTEN[1:0] values and the trigger polarity.
Table 13-4 Configuring the trigger polarity
Source EXTEN[1:0]
Trigger detection disabled 00
Detection on rising edge 01
Detection on falling edge 10
Detection on both rising and falling edges 11
Note: The polarity of the external trigger can be changed only when the ADC is not converting

The EXTSEL[2:0] control bits are used to select which of 8 possible events can trigger conversions.
Table 13-5 gives the possible external trigger for regular conversion.
Table 13-5 External triggers(EXTMOD=0)
Name Source EXTSEL[2:0]
TRG0 TIM1_TRGO 000
TRG1 TIM1_CC4 001
TRG2 Reserved 010
TRG3 TIM3_TRGO 011
TRG4 TIM15_TRGO 100
TRG5 Reserved 101
TRG6 Reserved 110
TRG7 Reserved 111
Note: The trigger selection can be changed only when the ADC is not converting

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13.5.1. Discontinuous mode(DISCEN)

This mode is enabled by setting the DISCEN bit in the ADC_CFGR1 register.
In this mode (DISCEN=1), a hardware or software trigger event is required to start each conversion defined
in the sequence. On the contrary, if DISCEN=0, a single hardware or software trigger event successively
starts all the conversions defined in the sequence.
Example:
 DISCEN=1,channels to be converted = 0, 3, 7, 10
─ 1st trigger: channel 0 is converted and an EOC event is generated
─ 2nd trigger: channel 3 is converted and an EOC event is generated
─ 3rd trigger: channel 7 is converted and an EOC event is generated
─ 4th trigger: channel 10 is converted and both EOC and EOSEQ events are generated.
─ 5th trigger: channel 0 is converted an EOC event is generated
─ 6th trigger: channel 3 is converted and an EOC event is generated
─ ...
 DISCEN=0, channels to be converted = 0, 3, 7, 10
─ 1st trigger: the complete sequence is converted: channel 0, then 3, 7 and 10. Each conversion
generates an EOC event and the last one also generates an EOSEQ event.
─ Any subsequent trigger events will restart the complete sequence
Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set
both bits DISCEN=1 and CONT=1.

13.5.2. Programmable resolution(RES)- fast conversion mode

It is possible to obtain faster conversion times (tSAR) by reducing the ADC resolution.
The resolution can be configured to be either 12, 10, 8, or 6 bits by programming the RES[1:0] bits in the
ADC_CFGR1 register. Lower resolution allows faster conversion times for applications where high data
precision is not required.
Note: The RES[1:0] bit must only be changed when the ADEN bit is reset.
The result of the conversion is always 12 bits wide and any unused LSB bits are read as zeros.
Lower resolution reduces the conversion time needed for the successive approximation steps as shown in
Table 13-6
Table 13-6 tSAR timings depending on resolution
tSAR tSMPL(min) tCONV
RES[1:0] tSAR(ns)@ tCONV@
(ADC clock (ADC clock (ADC clock cycles)
bits fADC=14MHz fADC=14MHz
cycles) cycles) (with min. tSMPL)
12 12.5 893 ns 1.5 14 1000 ns
10 11.5 821 ns 1.5 13 928 ns
8 9.5 678 ns 1.5 11 785 ns
6 7.5 535 ns 1.5 9 643 ns

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13.5.3. End of conversion, end of sampling


phase(EOC,EOSMP flags)

The ADC indicates each end of conversion (EOC) event


The ADC sets the EOC flag in the ADC_ISR register as soon as a new conversion data result is available in
the ADC_DR register. An interrupt can be generated if the EOCIE bit is set in the ADC_IER register. The
EOC flag is cleared by software either by writing 1 to it, or by reading the ADC_DR register.
The ADC also indicates the end of sampling phase by setting the EOSMP flag in the ADC_ISR register. The
EOSMP flag is cleared by software by writing1 to it. An interrupt can be generated if the EOSMPIE bit is set
in the ADC_IER register.
The aim of this interrupt is to allow the processing to be synchronized with the conversions. Typically, an
analog multiplexer can be accessed in hidden time during the conversion phase, so that the multiplexer is
positioned when the next sampling starts.
Note: As there is only a very short time left between the end of the sampling and the end of the conversion, it
is recommenced to use polling or a WFE instruction rather than an interrupt and a WFI instruction.

13.5.4. End of conversion sequence(EOSEQ flag)

The ADC notifies the application of each end of sequence (EOSEQ) event.
The ADC sets the EOSEQ flag in the ADC_ISR register as soon as the last data result of a conversion
sequence is available in the ADC_DR register. An interrupt can be generated if the EOSEQIE bit is set in the
ADC_IER register. The EOSEQ flag is cleared by software by writing 1 to it.

13.5.5. Example timing diagrams (single/continuous modes


hardware/software triggers)

ADSTART(1)

EOC

EOSEQ

SCANDIR

ADC state(2) RDY CH0 CH9 CH10 CH17 RDY CH17 CH10 CH9 CH0 RDY

ADC_DR D0 D9 D10 D17 D17 D10 D9 D0

by S/W by H/W

1. EXTMOD=0, EXTEN=00, CONT=0


2. CHSEL=0x20601, WAIT=0, AUTOFF=0

Figure 13-10 Single conversions of a sequence, software trigger

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ADSTART(1)

EOC

EOSEQ

ADSTP

SCANDIR

ADC state(2) RDY CH0 CH9 CH10 CH17 CH0 CH9 CH10 STP RDY CH17 CH10

ADC_DR D0 D9 D10 D17 D0 D9 D17 D10

by S/W by H/W

1. EXTMOD=0, EXTEN=00, CONT=1


2. CHSEL=0x20601, WAIT=0, AUTOFF=0

Figure 13-11 Continuous conversion of a sequence, software trigger

ADSTART(1)

EOC

EOSEQ

TRGx(1)
Χ

Χ
ADC state(2) RDY CH0 CH1 CH2 CH3 RDY CH0 CH1 CH2 CH3 RDY

ADC_DR D0 D1 D2 D3 D0 D1 D2 D3

by S/W by H/W

triggered ignored
Χ

1. EXTMOD=0, EXTSEL=TRGx(Overhigh frequency), EXTEN=01(Rising edge), CONT=0


2. CHSEL=0xF, SCANDIR=0, WAIT=0, AUTOFF=0

Figure 13-12 Single conversions of a sequence, hardware trigger

ADSTART(1)

EOC

EOSEQ

ADSTP

TRGx(1)

ADC state(2) RDY CH0 CH1 CH2 CH3 CH0 CH1 CH2 CH3 CH0 STOP RDY

ADC_DR D0 D1 D2 D3 D0 D1 D2 D3

by S/W by H/W

triggered ignored
Χ

1. EXTMOD=0, EXTSEL=TRGx, EXTEN=10(Falling edge), CONT=1


2. CHSEL=0xF, SCANDIR=0, WAIT=0, AUTOFF=0

Figure 13-13 Continuous conversions of a sequence, hardware trigger

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13.6. Data management

13.6.1. Data register and data alignment(ADC_DR, ALIGN,


ADC_IOSHxDR)

ADC_IOSHxDR 中.At the end of each conversion (when an EOC event occurs), the result of the converted
data is stored in the ADC_DR data register which is 16-bit wide.
The format of the ADC_DR and ADC_IOSHxDR depends on the configured data alignment and resolution.
The ALIGN bit in the ADC_CFGR1 register selects the alignment of the data stored after conversion. Data
can be right-aligned (ALIGN=0) or left-aligned (ALIGN=1) as shown in Figure 13-14

A L IG N RES 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0x 0 0x 0 D R [11:0]

0x 1 0x 00 D R [9:0]
0
0x 2 0x 00 D R [7:0]

0x 3 0x 000 D R [5:0]

0x 0 D R [11:0] 0x 0

0x 1 D R [9:0] 0x 00
1
0x 2 D R [7:0] 0x 00

0x 3 0x 00 D R [5:0] 0x 0

Figure 13-14 Data alignment and resolution

13.6.2. ADC overrun(OVR,OVRMOD)

The overrun flag (OVR) indicates a data overrun event, when the converted data was not read in time by the
CPU or the DMA, before the data from a new conversion is available. The OVR flag will not affected by the
converted data of ADC_IOSHxDR register
The OVR flag is set in the ADC_ISR register if the EOC flag is still at ‘1’ at the time when a new conversion
completes. An interrupt can be generated if the OVRIE bit is set in the ADC_IER register.
When an overrun condition occurs, the ADC keeps operating and can continue to convert unless the
software decides to stop and reset the sequence by setting the ADSTP bit in the ADC_CR register.
The OVR flag is cleared by software by writing 1 to it.
It is possible to configure if the data is preserved or overwritten when an overrun event occurs by
programming the OVRMOD bit in the ADC_CFGR1 register, it is only effected for ADC_DR register and the
ADC_IOSHxDR is always store the last converted data.
 OVRMOD=0
─ An overrun event preserves the data register from being overwritten: the old data is maintained
and the new conversion is discarded. If OVR remains at 1, further conversions can be performed
but the resulting data is discarded.
 OVRMOD=1
─ The data register is overwritten with the last conversion result and the previous unread data is lost.

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If OVR remains at 1, further conversions can be performed and the ADC_DR register always
contains the data from the latest conversion.
ADSTART(1)

EOC

EOSEQ

OVR

ADSTP

TRGx(1)

ADC state(2) RDY CH0 CH1 CH2 CH0 CH1 CH2 CH0 STOP RDY

OVERRUN
ADC_DR
Read Access

ADC_DR
D0 D1 D2 D0
(OVRMOD=0)

ADC_DR
D0 D1 D2 D0 D1 D2
(OVRMOD=1)

by S/W by H/W

triggered ignored
Χ

Figure 13-15 Example of overrun(OVR)

13.6.3. Managing a sequence of data converted without using


the DMA

If the conversions are slow enough, the conversion sequence can be handled by software. In this case the
software must use the EOC flag and its associated interrupt to handle each data result. Each time a
conversion is complete, the EOC bit is set in the ADC_ISR register and the ADC_DR register can be read.
The OVRMOD bit in the ADC_CFGR1 register should be configured to 0 to manage overrun events as an
error.

13.6.4. Managing converted data without using the DMA


without overrun

It may be useful to let the ADC convert one or more channels without reading the data after each conversion.
In this case, the OVRMOD bit must be configured at 1 and the OVR flag should be ignored by the software.
When OVRMOD=1, an overrun event does not prevent the ADC from continuing to convert and the
ADC_DR register always contains the latest conversion data.

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13.6.5. Managing converted data using the DMA

Since all converted channel values are stored in a single data register, it is efficient to use DMA when
converting more than one channel. This avoids losing the conversion data results stored in the ADC_DR
register.
When DMA mode is enabled (DMAEN bit set to 1 in the ADC_CFGR1 register), a DMA request is generated
after the conversion of each channel. This allows the transfer of the converted data from the ADC_DR
register to the destination ___location selected by the software.
Note: The DMAEN bit in the ADC_CFGR1 register must be set after the ADC calibration phase.
Despite this, if an overrun occurs (OVR=1) because the DMA could not serve the DMA transfer request in
time, the ADC stops generating DMA requests and the data corresponding to the new conversion is not
transferred by the DMA. Which means that all the data transferred to the RAM can be considered as valid.
Depending on the configuration of OVRMOD bit, the data is either preserved or overwritten(Refer to
13.6.2:ADC overrun(OVR,OVRMOD)).
The DMA transfer requests are blocked until the software clears the OVR bit.
Two different DMA modes are proposed depending on the application use and are configured with bit
DMACFG in the ADC_CFGR1 register:
 DMA one shot mode(DMACFG=0)
This mode should be selected when the DMA is programmed to transfer a fixed number of data words.
 DMA circular mode(DMACFG=1)
This mode should be selected when programming the DMA in circular mode or double buffer mode.

DMA one shot mode(DMACFG=0)


In this mode, the ADC generates a DMA transfer request each time a new conversion data word is available
and stops generating DMA requests once the DMA has reached the last DMA transfer (when a DMA_EOT
interrupt occurs, see section 11 DMA) even if a conversion has been started again.

When the DMA transfer is complete (all the transfers configured in the DMA controller have been done):
 The content of the ADC data register is frozen.
 Any ongoing conversion is aborted and its partial result discarded
 No new DMA request is issued to the DMA controller. This avoids generating an overrun error if there
are still conversions which are started.
 The scan sequence is stopped and reset
 The DMA is stopped

DMA circular mode(DMACFG=1)


In this mode, the ADC generates a DMA transfer request each time a new conversion data word is available
in the data register, even if the DMA has reached the last DMA transfer. This allows the DMA to be
configured in circular mode to handle a continuous analog input data stream.

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13.7. Low-power features

13.7.1. Wait mode conversion

Wait mode conversion can be used to simplify the software as well as optimizing the performance of
applications clocked at low frequency where there might be a risk of ADC overrun occurring.
When the WAIT bit is set to 1 in the ADC_CFGR1 register, a new conversion can start only if the previous
data has been treated, once the ADC_DR register has been read or if the EOC bit has been cleared.
This is a way to automatically adapt the speed of the ADC to the speed of the system that reads the data.
Note:Any hardware triggers which occur while a conversion is ongoing or during the wait time preceding the
read access are ignored.
ADSTART

EOC

EOSEQ

ADSTP

ADC_DR
Read Access

ADC state RDY CH0 DLY CH1 DLY CH2 DLY CH0 DLY STOP RDY

ADC_DR D0 D1 D2 D0

by S/W by H/W

1. EXTMOD=0, EXTEN=00, CONT=1


2. CHSEL=0x7, SCANDIR=0, WAIT=1, AUTOFF=0

Figure 13-16 Wait mode conversion (continuous mode, software trigger)

13.7.2. Auto-off mode(AUTOFF)

The ADC has an automatic power management feature which is called auto-off mode, and is enabled by
setting AUTOFF=1 in the ADC_CFGR1 register.
When AUTOFF=1, the ADC is always powered off when not converting and automatically wakes-up when a
conversion is started (by software or hardware trigger). A startup-time is automatically inserted between the
trigger event which starts the conversion and the sampling time of the ADC. The ADC is then automatically
disabled once the sequence of conversions is complete.
Auto-off mode can cause a dramatic reduction in the power consumption of applications which need
relatively few conversions or when conversion requests are timed far enough apart (for example with a low
frequency hardware trigger) to justify the extra power and extra time used for switching the ADC on and off.
Auto-off mode can be combined with the wait mode conversion (WAIT=1) for applications clocked at low
frequency. This combination can provide significant power savings if the ADC
Note: Please refer to the section 7 RCC for the description of how to manage the dedicated 14 MHz internal
oscillator. The ADC interface can automatically switch ON/OFF the 14 MHz internal oscillator to save power.

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TRGx

EOC

EOSEQ

ADC_DR
Read Access

ADC state RDY Startup CH0 CH1 CH2 CH3 OFF Startup

ADC_DR D0 D1 D2 D3

by S/W by H/W

triggered ignored
Χ

1. EXTMOD=0, EXTSEL=TRGx, EXTEN=01(Rising edge), CONT=x, ADSTART=1, CHSEL=0xF, SCANDIR=0, WAIT=0, AUTOFF=1

Figure 13-17 Behavior with WAIT=0,AUTOFF=1

TRGx

EOC

EOSEQ

ADC_DR
Read Access
DLY DLY DLY DLY

ADC state RDY Startup CH0 OFF Startup CH1 OFF Startup CH2 OFF Startup CH0 OFF

ADC_DR D0 D1 D2 D0

by S/W by H/W

triggered ignored
Χ

1. EXTMOD=0, EXTSEL=TRGx, EXTEN=01(Rising), CONT=x, ADSTART=1, CHSEL=0x7, SCANDIR=0, WAIT=1, AUTOFF=1

Figure 13-18 Behavior with WAIT=1,AUTOFF=1

13.8. Analog window watchdog


(AWDEN,AWDSGL,AWDCH,AWD_HTR/LTR,AWD)

The AWD analog watchdog feature is enabled by setting the AWDEN bit in the ADC_CFGR1 register. It is
used to monitor that either one selected channel or all enabled channels (see Table 13-8 analog watchdog
channel selection) remain within a configured voltage range (window) as shown in Figure 13-19
The AWD analog watchdog status bit is set if the analog voltage converted by the ADC is below a lower
threshold or above a higher threshold. These thresholds are programmed in the 12 least significant bits of
the ADC_HTR and ADC_LTR 16-bit registers. An interrupt can be enabled by setting the AWDIE bit in the
ADC_IER register.
The AWD flag is cleared by software by writing 1 to it.

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When converting a data with a resolution of less than 12-bit (according to bits DRES[1:0]), the LSB of the
programmed thresholds must be kept cleared because the internal comparison is always performed on the
full 12-bit raw converted data (left aligned).
Table 13-7 describes how the comparison is performed for all the possible resolutions.
Table 13-7 Analog watchdog comparison
Resolution Analog Watchdog comparison between:
bits Raw converted data, left Comments
(1) Thresholds
RES[1:0] aligned
00: 12-bit DATA[11:0] LT[11:0] and -
HT[11:0]
01: 10-bit DATA[11:2],00 LT[11:0] and The user must configure LT[1:0] and
HT[11:0] HT[1:0] to “00”
10: 8-bit DATA[11:4],0000 LT[11:0] and The user must configure LT[3:0] and
HT[11:0] HT[3:0] to “0000”
11: 6-bit DATA[11:6],000000 LT[11:0] and The user must configure LT[5:0] and
HT[11:0] HT[5:0] to “000000”
1. The watchdog comparison is performed on the raw converted data before any alignment calculation

Table 13-8 shows how to configure the AWDSGL and AWDEN bits in the ADC_CFGR1 register to enable
the analog watchdog on one or more channels.

Analog
voltage
Higher
thershold
HTR

Guarded area

Lower
threshold
LTR

Figure 13-19 Analog watchdog guarded area

Table 13-8 Analog watchdog channel selectio


Channels guarded by the analog
AWDSGL bit AWDEN bit
watchdog
None x 0
All channels 0 1
(1)
Single channel 1 1
1. Selected by the AWDCH[4:0] bits

13.9. Temperature sensor and internal reference voltage

The temperature sensor can be used to measure the junction temperature (TJ) of the device. The
temperature sensor is internally connected to the ADC_IN16 input channel which is used to convert the

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sensor’s output voltage to a digital value. The sampling time for the temperature sensor analog pin must be
greater than the minimum TS_temp value specified in the datasheet. When not in use, the sensor can be put
in power down mode.
The temperature sensor output voltage changes linearly with temperature, however its characteristics may
vary significantly from chip to chip due to the process variations. To improve the accuracy of the temperature
sensor (especially for absolute temperature measurement), calibration values are individually measured for
each part by ST during production test and stored in the system memory area. Refer to the specific device
datasheet for additional information.
The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for the ADC and
Comparators. VREFINT is internally connected to the ADC_IN17 input channel. The precise voltage of VREFINT
is individually measured for each part by FMD during production test and stored in the system memory area.,
and access by read only mode.
Figure 13-20 shows the block diagram of connections between the temperature sensor, the internal voltage
reference and the ADC.
The TSEN bit must be set to enable the conversion of ADC_IN16 (temperature sensor) and the INTVREFEN
bit must be set to enable the conversion of ADC_IN17 (VREFINT).

TSEN control bit

Temperature VSENSE
ADC_IN16
sensor

Converted data Address/data bus


ADC1

Internal VREFINT
ADC_IN17
power block

VREFEN control bit

Figure 13-20 Temperature sensor and VREFINT channel block diagram


Reading the temperature
1. Select the ADC_IN16 input channel;
2. Select an appropriate sampling time specified in the device datasheet (TS_temp);
3. Set the TSEN bit in the ADC_CCR register to wake up the temperature sensor from power down mode
and wait for its stabilization time (tSTART);
4. Start the ADC conversion by setting the ADSTART bit in the ADC_CR register (or by external trigger);
5. Read the resulting data in the ADC_DR register;
6. Calculate the actual temperature using the following formula:

110  C - 25  C
Temperatur e(  C )    TS_DATA  TS_CAL1   25  C
TS_CAL2 - TS_CAL1

Where:
 TS_CAL2 is the temperature sensor calibration value acquired at 110°C, stored in the system

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memory area: 0x1FFF F7C2 - 0x1FFF F7C3


 TS_CAL1 is the temperature sensor calibration value acquired at 25°C, stored in the system memory
area: 0x1FFF F7B8 - 0x1FFF F7B9
 TS_DATA is the actual temperature sensor output value converted by ADC
Refer to the specific device datasheet for more information about TS_CAL1 and TS_CAL2
calibration points.

Note: The sensor has a startup time after waking from power down mode before it can output V SENSE at the
correct level. The ADC also has a startup time after power-on, so to minimize the delay, the ADEN and TSEN
bits should be set at the same time.

Calculating the actual VDDA voltage using the internal reference voltage
The VDDA power supply voltage applied to the microcontroller may be subject to variation or not precisely
known. The embedded internal voltage reference (V REFINT) and its calibration data acquired by the ADC
during the manufacturing process at VDDA = 3.3 V can be used to evaluate the actual VDDA voltage level.
The following formula gives the actual VDDA voltage supplying the device:

V DDA  3.3V  V REFINT_CAL /V REFINT_DAT A

Where:
 VREFINT_CAL is the VREFINT calibration value, stored in the system memory area: 0x1FFF F7BA - 0x1FFF
F7BB
 VREFINT_DATA is the actual VREFINT output value converted by ADC

Converting a supply-relative ADC measurement to an absolute voltage value


The ADC is designed to deliver a digital value corresponding to the ratio between the analog power supply
and the voltage applied on the converted channel. For most application use cases, it is necessary to convert
this ratio into a voltage independent of VDDA. For applications where VDDA is known and ADC converted
values are right-aligned you can use the following formula to get this absolute value:

V DDA
V CHANNELx   ADC_DATAx
FULL_SCALE

For applications where VDDA value is not known, you must use the internal voltage reference and V DDA can
be replaced by the expression provided in the section Calculating the actual VDDA voltage using the internal
reference voltage resulting in the following formula:
3.3V  V REFINT_CAL  ADC_DATAx
V CHANNELx 
V REFINT_DAT A
 FULL_SCALE

Where:
 VREFINT_CAL is the VREFINT calibration value, stored in the system memory area: 0x1FFF F7BA - 0x1FFF
F7BB
 ADC_DATAx is the value measured by the ADC on channel x (right-aligned)
 VREFINT_DATA is the actual VREFINT output value converted by the ADC

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 FULL_SCALE is the maximum digital value of the ADC output. For example with 12-bit resolution, it will
be 212 - 1 = 4095 or with 8-bit resolution, 28 - 1 = 255.

Note: If ADC measurements are done using an output format other than 12 bit right-aligned, all the
parameters must first be converted to a compatible format before the calculation is done.

13.10. ADC internal reference voltage

By default, ADC_CR2.VREFEN = 0, Internal reference voltage is disabled, the reference voltage of ADC is
VDDA.
Configure the VREFSEL bit to choose the level of the internal reference voltage: 0.625V, 1.5V, 2.5V.
Then set VREFEN after configured the VREFSEL bit , and ADC reference voltage will be internal reference
voltage.

Note: ADC reference voltage should be configured when the ADC is not proceeding the conversion, and it
has startup stable time, for more details please refer to ADC electrical characteristic

13.11. ADC interrupts

An interrupt can be generated by any of the following events:


 ADC power-up, when the ADC is ready (ADRDY flag)
 End of any conversion (EOC flag)
 End of a sequence of conversions (EOSEQ flag)
 When an analog watchdog detection occurs (AWD flag)
 When the end of sampling phase occurs (EOSMP flag)
 when a data overrun occurs (OVR flag)
Separate interrupt enable bits are available for flexibility.
Table 13-9 ADC interrupts
Interrupt event Event flag Enable control bit
ADC ready ADRDY ADRDYIE
End of conversion EOC EOCIE
End of sequence of conversions EOSEQ EOSEQIE
Analog watchdog status bit is
AWD AWDIE
set
End of sampling phase EOSMP EOSMPIE
Overrun OVR OVRIE

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13.12. ADC register map

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
Offset Register

9
8
AWD 7
6
5
OVR 4
EOSEQIE EOSEQ3
EOC 2
EOSMPIE EOSMP1
ADRDYIE ADRDY0
ADC_ISR –
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–

–
–
0x00
Reset x x x x x x x x x x x x x x x x x x x x x x x x 0 x x 0 0 0 0 0

AWDIE

OVRIE

EOCIE
ADC_IER
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–

–
–
0x04
Reset x x x x x x x x x x x x x x x x x x x x x x x x 0 x x 0 0 0 0 0

ADSTART
ADSTP
ADCAL

ADDIS
ADEN
ADC_CR
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–

–
0x08
Reset 0 x x x x x x x x x x x x x x x x x x x x x x x x x x 0 x 0 0 0

OVRMOD

SCANDIR
AWDSGL

DMACFG
AUTOFF
DISCEN
AWDEN

DMAEN
EXTEN

ALIGN
CONT
WAIT
EXTSEL RES

[1:0]
ADC_CFGR1 AWDCH[4:0]
–

–
–

–
–
–
–
–

–
0x0C [2:0] [1:0]

Reset x 0 0 0 0 0 x x 0 0 x x x x x 0 0 0 0 0 0 0 x 0 0 0 0 0 0 0 0 0
CKMODE

[1:0]

ADC_CFGR2
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0x10

Reset 0 0 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
SMP
ADC_SMPR
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0x14 [2:0]
Reset x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 0 0 0
ADC_TR HT[11:0] LT[1:0]
–
–
–
–

–
–
–
–
0x20
Reset x x x x 1 1 1 1 1 1 1 1 1 1 1 1 x x x x 0 0 0 0 0 0 0 0 0 0 0 0
CHSEL19
CHSEL18
CHSEL17
CHSEL16
CHSEL15
CHSEL14
CHSEL13
CHSEL12
CHSEL11
CHSEL10
CHSEL9
CHSEL8
CHSEL7
CHSEL6
CHSEL5
CHSEL4
CHSEL3
CHSEL2
CHSEL1
CHSEL0
ADC_CHSELR
–
–
–
–
–
–
–
–
–
–
–
–

0x28
Reset x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ADC_DR DATA[15:0]
–
–
–
–
–
–
–
–
–
INTVREFEN –
–
–
–
–
–
–

0x40
Reset x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TSEN

ADC_CCR
–
–
–
–
–
–
–
–

–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0x308

Reset x x x x x x x x 0 0 x x x x x x x x x x x x x x x x x x x x x x

VREF_DECIB
IO_SMPEN
IO_AMPEN

VREFSEL

VREFEN
[1:0]
ADC_CR2
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–

–
–
–

–
0x30C

Reset x x x x x x x x x x x x x x x x x x x x x x 0 0 x x x 1 0 0 0 x

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13.12.1. ADC_ISR

Address offset:0x00
Reset value:0x0000 0000

Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0


31:24 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
7:0 AWD — OVR EOSEQ EOC EOSMP ADRDY
Type RC_W1 RO-0 RO-0 RC_W1 RC_W1 RC_W1 RC_W1 RC_W1

Bit Name Function


31:8 NA Reserved
7 AWD Analog watchdog flag
This bit is set by hardware when the converted voltage crosses the values
programmed in the ADC_LTR and ADC_HTR registers. It is cleared by
software writing 1 to it.
0:No analog watchdog event occurred (or the flag event was already
acknowledged and cleared by software)
1:Analog watchdog event occurred
6:5 NA Reserved
4 OVR ADC overrun
This bit is set by hardware when an overrun occurs, meaning that a new
conversion has complete while the EOC flag was already set. It is cleared by
software writing 1 to it.
0:No overrun occurred (or the flag event was already acknowledged and
cleared by software)
1:Overrun has occurred
3 EOSEQ End of sequence flag
This bit is set by hardware at the end of the conversion of a sequence of
channels selected by the CHSEL bits. It is cleared by software writing 1 to it.
0:Conversion sequence not complete (or the flag event was already
acknowledged and cleared by software)
1:Conversion sequence complete
2 EOC End of conversion flag
This bit is set by hardware at the end of each conversion of a channel when
a new data result is available in the ADC_DR register. It is cleared by
software writing 1 to it or by reading the ADC_DR register

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0:Channel conversion not complete (or the flag event was already
acknowledged and cleared by software)
1:Channel conversion complete
1 EOSMP End of sampling flag
This bit is set by hardware during the conversion, at the end of the sampling
phase.
0: Not at the end of the sampling phase (or the flag event was already
acknowledged and cleared by software)
1:End of sampling phase reached
0 ADRDY ADC ready
This bit is set by hardware after the ADC has been enabled (bit ADEN=1)
and when the ADC reaches a state where it is ready to accept conversion
requests. It is cleared by software writing 1 to it.
0:ADC not yet ready to start conversion (or the flag event was already
acknowledged and cleared by software)
1:ADC is ready to start conversion
Note: In auto-off mode(AUTOFF=1), ADRDY will not be set, power on/off is
executed by hardware

13.12.2. ADC_IER

Address offset: 0x04


Reset value: 0x0000 0000

Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0


31:24 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
7:0 AWDIE — OVRIE EOSEQIE EOCIE EOSMPIE ADRDYIE
Type RW RO-0 RO-0 RW RW RW RW RW

Bit Name Function


31:8 NA Reserved
7 AWDIE Analog watchdog interrupt enable
This bit is set and cleared by software to enable/disable the analog
watchdog interrupt.
0:Analog watchdog interrupt disabled
1:Analog watchdog interrupt enabled
Note: Software is allowed to write this bit only when ADSTART=0 (which

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ensures that no conversion is ongoing).


6:5 NA Reserved
4 OVRIE Overrun interrupt enable
This bit is set and cleared by software to enable/disable the overrun
interrupt.
0:Overrun interrupt disabled
1:Overrun interrupt enabled. An interrupt is generated when the OVR bit is
set.
Note: Software is allowed to write this bit only when ADSTART=0 (which
ensures that no conversion is ongoing).
3 EOSEQIE End of conversion sequence interrupt enable
This bit is set and cleared by software to enable/disable the end of sequence
of conversions interrupt
0:EOSEQ interrupt disabled
1:EOSEQ interrupt enabled. An interrupt is generated when the EOSEQ bit
is set
Note: Software is allowed to write this bit only when ADSTART=0 (which
ensures that no conversion is ongoing).
2 EOCIE End of conversion interrupt enable
This bit is set and cleared by software to enable/disable the end of
conversion interrupt
0:EOC interrupt disabled
1:EOC interrupt enabled. An interrupt is generated when the EOC bit is set
Note: Software is allowed to write this bit only when ADSTART=0 (which
ensures that no conversion is ongoing).
1 EOSMPIE End of sampling flag interrupt enable
This bit is set and cleared by software to enable/disable the end of the
sampling phase interrupt.
0:EOSMP interrupt disabled
1:EOSMP interrupt enabled. An interrupt is generated when the EOSMP bit
is set
Note: Software is allowed to write this bit only when ADSTART=0 (which
ensures that no conversion is ongoing).
0 ADRDYIE ADC ready interrupt enable
This bit is set and cleared by software to enable/disable the ADC Ready
interrupt.
0:ADRDY interrupt disabled
1:ADRDY interrupt enabled. An interrupt is generated when the ADRDY bit
is set.
Note: Software is allowed to write this bit only when ADSTART=0 (which
ensures that no conversion is ongoing).

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13.12.3. ADC_CR

Address offset: 0x08


Reset value: 0x0000 0000

Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0


31:24 ADCAL —
Type RS RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
7:0 — ADSTP — ADSTART ADDIS ADEN
Type RO-0 RO-0 RO-0 RS RO-0 RS RS RS

Bit Name Function


31 ADCAL ADC calibration
This bit is set by software to start the calibration of the ADC.
It is cleared by hardware after calibration is complete
0:Calibration complete
1:Write 1 to calibrate the ADC. Read at 1 means that a calibration is in
progress.
Note: Software is allowed to set ADCAL only when the ADC is disabled
(ADCAL=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0).
30:5 NA Reserved
4 ADSTP ADC stop conversion command
This bit is set by software to stop and discard an ongoing conversion
(ADSTP Command).
It is cleared by hardware when the conversion is effectively discarded and
the ADC is ready to accept a new start conversion command.
0:No ADC stop conversion command ongoing
1:Write 1 to stop the ADC. Read 1 means that an ADSTP command is in
progress.
Note: Software is allowed to set ADSTP only when ADSTART=1 and
ADDIS=0 (ADC is enabled and may be converting and there is no pending
request to disable the ADC)
3 NA Reserved
2 ADSTART ADC start conversion command
This bit is set by software to start ADC conversion. Depending on the EXTEN
[1:0] configuration bits, a conversion either starts immediately (software
trigger configuration) or once a hardware trigger event occurs (hardware
trigger configuration).

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─ In single conversion mode(CONT=0,DISCEN=0) when software trigger


is selected (EXTMOD=0,EXTEN=00): at the assertion of the End of
Conversion Sequence (EOSEQ) flag.
─ In discontinuous mode(CONT=0,DISCEN=1): when software trigger is
selected (EXTMOD=0,EXTEN=00): at the assertion of the End of
Conversion (EOC) flag
─ In all cases: after the execution of the ADSTP command, at the same
time as the ADSTP bit is cleared by hardware.
0:No ADC conversion is ongoing.
1:Write 1 to start the ADC. Read 1 means that the ADC is operating and may
be converting.
Note: Software is allowed to set ADSTART only when ADEN=1 and
ADDIS=0 (ADC is enabled and there is no pending request to disable the
ADC)
1 ADDIS ADC disable command
This bit is set by software to disable the ADC (ADDIS command) and put it
into power-down state (OFF state).
It is cleared by hardware once the ADC is effectively disabled (ADEN is also
cleared by hardware at this time).
0:No ADDIS command ongoing
1:Write 1 to disable the ADC. Read 1 means that an ADDIS command is in
progress.
Note: Software is allowed to set ADDIS only when ADEN=1 and
ADSTART=0 (which ensures that no conversion is ongoing)
0 ADEN ADC enable command
This bit is set by software to enable the ADC. The ADC will be effectively
ready to operate once the ADRDY flag has been set.
It is cleared by hardware when the ADC is disabled, after the execution of
the ADDIS command
0:ADC is disabled (OFF state)
1:ADC Write 1 to enable the ADC
Note: Software is allowed to set ADEN only when all bits of ADC_CR
registers are 0 (ADCAL=0, ADSTP=0, ADSTART=0, ADDIS=0 and
ADEN=0)

13.12.4. ADC_CFGR1

Address offset: 0x0C


Reset value: 0x0000 0000

Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0


31:24 — AWDCH[4:0] —

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Type RO-0 RW RW RW RW RW RO-0 RO-0


23:16 AWDEN AWDSGL — DISCEN
Type RW RW RO-0 RO-0 RO-0 RO-0 RO-0 RW
15:8 AUTOFF WAIT CONT OVRMOD EXTEN[1:0] — EXTSEL[
2]
Type RW RW RW RW RW RW RO-0 RW
7:0 EXTSEL[1:0] ALIGN RES[1:0] SCANDIR DMACFG DMAEN
Type RW RW RW RW RW RW RW RW

Bit Name Function


31 NA Reserved
30:26 AWDCH[4:0] Analog watchdog channel selection
These bits are set and cleared by software. They select the input channel to
be guarded by the analog watchdog
00000:ADC analog input Channel 0 monitored by AWD
00001:ADC analog input Channel 1 monitored by AWD
.....
10101:ADC analog input Channel 21 monitored by AWD
other values: Reserved, must not be used
Note: The channel selected by the AWDCH[4:0] bits must be also set into
the CHSELR register
Software is allowed to write these bits only when ADSTART=0 (which
ensures that no conversion is ongoing).
25:24 NA Reserved
23 AWDEN Analog watchdog enable
This bit is set and cleared by software.
0:Analog watchdog disabled
1:Analog watchdog enabled
Note: Software is allowed to write these bits only when ADSTART=0 (which
ensures that no conversion is ongoing).
22 AWDSGL Enable the watchdog on a single channel or on all channels
This bit is set and cleared by software to enable the analog watchdog on the
channel identified by the AWDCH[4:0] bits or on all the channels
0:Analog watchdog enabled on all channels
1:Analog watchdog enabled on a single channel
Note: Software is allowed to write these bits only when ADSTART=0 (which
ensures that no conversion is ongoing).
21:17 NA Reserved
16 DISCEN Discontinuous mode
This bit is set and cleared by software to enable/disable discontinuous
mode.
0:Discontinuous mode disabled
1:Discontinuous mode enabled

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Note: It is not possible to have both discontinuous mode and continuous


mode enabled: it is forbidden to set both bits DISCEN=1 and CONT=1.
Software is allowed to write this bit only when ADSTART=0 (which
ensures that no conversion is ongoing).
15 AUTOFF Auto-off mode
This bit is set and cleared by software to enable/disable auto-off mode.
0:Auto-off mode disabled
1:Auto-off mode enabled
Note: Software is allowed to write these bits only when ADSTART=0 (which
ensures that no conversion is ongoing).
14 WAIT Wait conversion mode
This bit is set and cleared by software to enable/disable wait conversion
mode.
0:Wait conversion mode off
1:Wait conversion mode on
Note: Software is allowed to write these bits only when ADSTART=0 (which
ensures that no conversion is ongoing).
13 CONT Single / continuous conversion mode
This bit is set and cleared by software. If it is set, conversion takes place
continuously until it is cleared.
0:Single conversion mode
1:Continuous conversion mode
Note: It is not possible to have both discontinuous mode and continuous
mode enabled: it is forbidden to set both bits DISCEN=1 and CONT=1.
Software is allowed to write this bit only when ADSTART=0 (which
ensures that no conversion is ongoing).
12 OVRMOD Overrun management mode
This bit is set and cleared by software and configure the way data overruns
are managed.
0:ADC_DR register is preserved with the old data when an overrun is
detected.
1:ADC_DR register is overwritten with the last conversion result when an
overrun is detected
Note: Software is allowed to write these bits only when ADSTART=0 (which
ensures that no conversion is ongoing).
11:10 EXTEN[1:0] External trigger enable and polarity selection
These bits are set and cleared by software to select the external trigger
polarity and enable the trigger
00:Hardware trigger detection disabled (conversions can be started by
software)
01:Hardware trigger detection on the rising edge
10:Hardware trigger detection on the falling edge
11:Hardware trigger detection on both the rising and falling edges

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Note: Software is allowed to write these bits only when ADSTART=0 (which
ensures that no conversion is ongoing). Only effected when EXTMOD=0
9 NA Reserved
8:6 EXTSEL[2:0] External trigger selection
These bits select the external event used to trigger the start of conversion
(Refer to Table 13-5. External trigger selection(EXTMOD=0))
Note: Software is allowed to write these bits only when ADSTART=0 (which
ensures that no conversion is ongoing). Only effected when EXTMOD=0 and
EXTEN≠00.
5 ALIGN Data alignment
This bit is set and cleared by software to select right or left alignment. Refer
to Figure 13-14. Data alignment and resolution
0:Right alignment
1:Left alignment
Note: Software is allowed to write these bits only when ADSTART=0 (which
ensures that no conversion is ongoing).
4:3 RES[1:0] Data resolution
These bits are written by software to select the resolution of the conversion.
00:12 bits
01:10 bits
10:8 bits
11:6 bits
Note: Software is allowed to write these bits only when ADEN=0
2 SCANDIR Scan sequence direction
This bit is set and cleared by software to select the direction in which the
channels will be scanned in the sequence.
0:Upward scan(from CHSEL0 to CHSEL21)
1:Backward scan(from CHSEL21 to CHSEL0)
Note: Software is allowed to write these bits only when ADSTART=0 (which
ensures that no conversion is ongoing).
1 DMACFG Direct memory access configuration
This bit is set and cleared by software to select between two DMA modes of
operation and is effective only when DMAEN=1.
0:DMA one shot mode selected
1:DMA circular mode selected
For more details, refer to section 13.6.5:Managing converted data using the
DMA
Note: Software is allowed to write these bits only when ADSTART=0 (which
ensures that no conversion is ongoing).
0 DMAEN Direct memory access enable
This bit is set and cleared by software to enable the generation of DMA
requests. This allows to use the DMA controller to manage automatically the
converted data. For more details, refer to section 13.6.5:Managing

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converted data using the DMA


0:DMA disabled
1:DMA enabled
Note: Software is allowed to write these bits only when ADSTART=0 (which
ensures that no conversion is ongoing).

13.12.5. ADC_CFGR2

Address offset: 0x10


Reset value: 0x0000 0000

Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0


31:24 CKMODE[1:0] —
Type RW RW RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
7:0 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0

Bit Name Function


31:30 CKMODE[1:0] ADC clock mode
These bits are set and cleared by software to define how the analog ADC is
clocked:
00:ADCCLK (Asynchronous clock mode), generated at product level (refer
to RCC section)
01:PCLK/2 (Synchronous clock mode)
10:PCLK/4 (Synchronous clock mode)
11:Reserved
Note: Software is allowed to write these bits only when the ADC is disabled
(ADCAL=0, ADSTART=0, ADSTP=0, ADDIS=0, ADEN=0).
29:0 NA Reserved

13.12.6. ADC_SMPR

Address: 0x14
Reset value: 0x0000 0000

Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0


31:24 —

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Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0


23:16 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
7:0 — SMP[2:0]
Type RO-0 RO-0 RO-0 RO-0 RO-0 RW RW RW

Bit Name Function


31:3 NA Reserved
2:0 SMP[2:0] Sampling time selection
These bits are written by software to select the sampling time that applies to
all channels.
000:1.5 ADC clock cycles
001:7.5 ADC clock cycles
010:13.5 ADC clock cycles
011:28.5 ADC clock cycles
100:41.5 ADC clock cycles
101:55.5 ADC clock cycles
110:71.5 ADC clock cycles
111:239.5 ADC clock cycles
Note: Software is allowed to write these bits only when ADSTART=0 (which
ensures that no conversion is ongoing).

13.12.7. ADC_TR

Address offset: 0x20


Reset value: 0x0FFF 0000

Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0


31:24 — HT[11:8]
Type RO-0 RO-0 RO-0 RO-0 RW RW RW RW
23:16 HT[7:0]
Type RW RW RW RW RW RW RW RW
15:8 — LT[11:8]
Type RO-0 RO-0 RO-0 RO-0 RW RW RW RW
7:0 LT[7:0]
Type RW RW RW RW RW RW RW RW

Bit Name Function


31:28 NA Reserved
27:16 HT[11:0] Analog watchdog higher threshold

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These bits are written by software to define the higher threshold for the
analog watchdog. Refer to section 13.8:Analog window watchdog
(AWDEN,AWDSGL, AWDCH, AWD_HTR/AWD_LTR, AWD).
Note: Software is allowed to write these bits only when ADSTART=0 (which
ensures that no conversion is ongoing).
15:12 NA Reserved
11:0 LT[11:0] Analog watchdog lower threshold
These bits are written by software to define the lower threshold for the
analog watchdog. Refer to section 13.8:Analog window watchdog
(AWDEN,AWDSGL, AWDCH, AWD_HTR/AWD_LTR, AWD).
Note: Software is allowed to write these bits only when ADSTART=0 (which
ensures that no conversion is ongoing).

13.12.8. ADC_CHSELR

Address offset: 0x28


Reset value: 0x0000 0000

Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0


31:24 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 — CHSEL21 CHSEL20 CHSEL19 CHSEL18 CHSEL17 CHSEL16
Type RO-0 RO-0 RW RW RW RW RW RW
15:8 CHSEL15 CHSEL14 CHSEL13 CHSEL12 CHSEL11 CHSEL10 CHSEL9 CHSEL8
Type RW RW RW RW RW RW RW RW
7:0 CHSEL7 CHSEL6 CHSEL5 CHSEL4 CHSEL3 CHSEL2 CHSEL1 CHSEL0
Type RW RW RW RW RW RW RW RW

Bit Name Function


31:22 NA Reserved
21:0 CHSELx Channel-x selection
These bits are written by software and define which channels are part of the
sequence of channels to be converted.
0:Input Channel-x is not selected for conversion
1:Input Channel-x is selected for conversion
Note: Software is allowed to write these bits only when ADSTART=0 (which
ensures that no conversion is ongoing).

13.12.9. ADC_DR

Address offset: 0x40

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Reset value: 0x0000 0000

Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0


31:24 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 DATA[15:8]
Type RW RW RW RW RW RW RW RW
7:0 DATA[7:0]
Type RW RW RW RW RW RW RW RW

Bit Name Function


31:16 NA Reserved
15:0 DATA[15:0] Converted data
These bits are read-only. They contain the conversion result from the last
converted channel. The data are left- or right-aligned as shown in figure
13.14: Data alignment and resolution
Just after a calibration is complete, DATA[6:0] contains the calibration factor.

13.12.10. ADC_CCR

Address offset: 0x308


Reset value: 0x0000 0000

Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0


31:24 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 TSEN INTVREFE —
N
Type RW RW RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
7:0 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0

Bit Name Function


31:24 NA Reserved
23 TSEN Temperature sensor enable
This bit is set and cleared by software to enable/disable the temperature
sensor.
0: Temperature sensor disabled

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1: Temperature sensor enabled


Note: Software is allowed to write these bits only when ADSTART=0 (which
ensures that no conversion is ongoing).
22 INTVREFEN VREFINT enable
This bit is set and cleared by software to enable/disable the VREFINT.
0:VREFINT disabled
1:VREFINT enabled
Note: Software is allowed to write these bits only when ADSTART=0 (which
ensures that no conversion is ongoing).
21:0 NA Reserved

13.12.11. ADC_CR2

Address offset: 0x30C


Reset value: 0x0000 0010

Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0


31:24 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 IOSH_SM IOSH_AM
—
PEN PEN
Type RW RW RW RW RW RW RW RW
7:0 — VREF_DE VREFSEL[1:0] VREFEN —
CIB
Type RO-0 RO-0 RO-0 RW RW RW RW RO-0

Bit Name Function


31:10 NA Reserved
9 IOSH1_SMPEN IO sample and hold circuit sample function enable
This bit is set and cleared by hardware to to enable/disable IO sample and
hold circuit sample function, and read by software to indiacte IO sample and
hold circuit sample status
0: IO sample and hold circuit sample function disabled
1: IO sample and hold circuit sample function enabled
Note: Software is allowed to write these bits only when ADSTART=0 (which
ensures that no conversion is ongoing).
8 IOSH_AMPEN IO sample and hold circuit hold function enable
This bit is set and cleared by software to enable/disable IO sample and hold
circuit hold function.
0:IO sample and hold circuit hold function disabled

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1:IO sample and hold circuit hold function enabled


Note: Software is allowed to write these bits only when ADSTART=0 (which
ensures that no conversion is ongoing).
7:5 NA Reserved
4 VREF_DECIB ADC reference voltage circuit Bias current halved control
This bit is set and cleared by software to halve ADC reference voltage circuit
Bias current which can make the output of the ADC reference voltage more
precise
0: Standard ADC reference voltage circuit
1: Halved ADC reference voltage circuit
Note: Software is allowed to write these bits only when ADSTART=0 (which
ensures that no conversion is ongoing).
3:2 VREFSEL[1:0] ADC reference voltage output level select
These bits are set and cleared by software to select the level of the ADC
reference voltage output
00:Reserved
01: Reserved
10:2.5 V
11: Reserved
Note: Software is allowed to write these bits only when ADSTART=0 (which
ensures that no conversion is ongoing).
1 VREFEN ADC reference voltage circuit enable
This bit is set and cleared by software to enable the output of the ADC
reference voltage circuit.
0: Disable ADC reference voltage output
1: Enable ADC reference voltage output
Note: Software is allowed to write these bits only when ADSTART=0 (which
ensures that no conversion is ongoing).
0 NA Reserved

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Fremont Micro Devices FT32F0xxx8 RM

14. Comparator

14.1. Introduction

The FT32F0xxx8 device embed two general purpose comparators COMP1, COMP2, that can be used
either as standalone devices (all terminal are available on I/Os) or combined with the timers. The
comparators can be used for a variety of functions including:
- Wake-up from low-power mode triggered by an analog signal
- Analog signal conditioning
- Cycle-by-cycle current control loop when combined with the DAC and a PWM output from a timer.

14.2. Main features

 Each comparator has flexible voltage selection:


- 8 I/O pins
- DAC output
 The outputs can be redirected to an I/O or to timer inputs for triggering:
- Capture event
- OCref_clr event
- Input break event
 COMP1 and COMP2 can be combined in a window comparator.
 Each comparator has interrupt generation capability with wake-up from Sleep and Stop modes (through
the EXTI controller)

14.3. COMP functional description

14.3.1. Introduction

The block diagram of the comparators is shown in Figure 14-1:

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COMP1VIPSEL <2:0>= 000 && COMP1EN ==1'b1


(in 1wire)
1wire tim1_brkin
COMP1VIPSEL <2:0>= 001&& COMP1EN ==1'b1 tim1_ch1in
PAD_PA1 tim1_clrocrf
COMP1VIPSEL <2:0>= 010&& COMP1EN ==1'b1 tim3_ch1in
PAD_PA4 tim3_clrocrf
COMP1VIPSEL <2:0>= 011&& COMP1EN ==1'b1

PAD_PA13
COMP inetrrupt request (to EXTI)
COMP1VIPSEL <2:0>= 100&& COMP1EN ==1'b1
PAD_PB12
COMP1OUT( VDDL )
COMP1VINSEL<1:0> = 11&& COMP1EN ==1'b1 COMP1 D
SE
T
Q D
SE
T
Q PRDATA

PAD_PA5 CLK CL
R Q CL
R Q

COMP1VINSEL<1:0> = 10&& COMP1EN ==1'b1

COMP1VINSEL<1:0> = 01&& COMP1EN ==1'b1 PAD


PAD_PA0 PAX
COMP1VINSEL<1:0> = 00 && COMP1EN ==1'b1
DAC1_out ( in DAC )
AF_AFR
GPIO TOP

DAC
tim1_brkin
COMP2VINSEL<1:0> = 00&&COMP2EN ==1'b1 tim1_ch1in

DAC2_out ( in DAC) tim1_clrocrf

tim3_ch1in
COMP2VINSEL<1:0> = 01&&COMP2EN ==1'b1
tim3_clrocrf
PAD_PA2
COMP2VINSEL<1:0> = 10&&COMP2EN ==1'b1

COMP inetrrupt request (to EXTI)


COMP2VINSEL<1:0> = 11 &&COMP2EN ==1'b1

COMP2OUT( VDDL )
COMP2 D
SE
T
Q D
SE
T
Q PRDATA

CLK
CL
R Q CL
R Q

WNDWEN == 1
COMP2VIPSEL <1:0>= 00&COMP2EN ==1'b1
PAD_PA3

COMP2VIPSEL <1:0>= 01&COMP2EN ==1'b1 PAD


PAX

COMP2VIPSEL <1:0>= 10 &COMP2EN ==1'b1


GPIO TOP AF_AFR

COMP2VIPSEL <1:0>= 11 &COMP2EN ==1'b1

Figure 14-1 Comparator block diagram

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14.3.2. COMP pins and internal signals

The I/Os used as comparators inputs must be configured in analog mode in the GPIOs registers.
The comparator output can be connected to the I/Os using the alternate function channel given in “Alternate
function mapping” table in the datasheet.
The output can also be internally redirected to a variety of timer input for the following purposes:
 Capture event
 OCref_clr event
 Input break event

14.3.3. COMP reset and clocks

The COMP clock provided by the clock controller is synchronous with the PCLK (APB clock).
There is no clock enable control bit provided in the RCC controller. clock enable bit is common for COMP
and SYSCFG.
There is no clock reset control bit provided in the RCC controller. COMP can only reset by system reset .
Note: The polarity selection logic and the output redirection to the port works independently from the PCLK
clock. This allows the comparator to work even in Stop mode.

14.3.4. Comparator LOCK mechanism

The comparators can be used for safety purposes, such as over-current or thermal protection. For
applications having specific functional safety requirements, it is necessary to insure that the comparator
programming cannot be altered in case of spurious register access or program counter corruption. For this
purpose, the comparator control and status registers can be read- only and cnnot be wrote.
Once the programming is completed, if the COMPxLOCK bit be set to 1. this causes the whole COMP
register to become read-only until the next MCU reset

14.3.5. COMP interrupts

The comparator outputs are internally connected to the EXTI controller, Each comparator has its own EXTI
line and can generate either interrupts or events. The same mechanism is used to exit from low-power
modes.

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14.3.6. DAC output

Digital inputs are converted to the analog output voltages on each DAC channel pin are determined by the
following equation:
DAC1_out=VDACREF* (DAC1DATA<6:0>+1)/128 (0x20 ≤ DAC1DATA<6:0> ≤ 0x7F)
DAC2_out=VDACREF * (DAC2DATA<6:0>)/128 (0x00 ≤ DAC2DATA<6:0> ≤ 0x5F)

14.4. Comparator register map


31

30

29

28

27

26

COMP2OUTSEL 25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10
Offset Register

COMP1OUTSEL 9

0
COMP2VINSEL

COMP2VIPSEL

COMP1VINSEL

COMP1VIPSEL
COMP2LOCK

COMP1LOCK
COMP2OUT

COMP1OUT
COMP2POL

COMP1POL
COMP2EN

COMP1EN
COMPCSR
WNDWEN
–

–
0x1C

Reset 0 0 x x 0 0 0 0 0 x x 0 1 0 0 0 0 0 x x 0 0 0 0 x x 0 1 0 0 1 0

DACREFSEL
DACCTRL
–

–
0x20

DACEN
Reset x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 0 0 0

DAC1DATA DAC1DATA
–

–
0x24

Reset x x x x x x x x x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0

DAC2DATA DAC2DATA
–

–
0x28

Reset x x x x x x x x x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0

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14.4.1. COMPCSR

Address offset: 0x01C


Reset value: 0x00080012
Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 COMP2LO COMP2OU — COMP2PO COMP2OUTSEL
CK T L
Type RW RO RO-0 RO-0 RW RW RW RW
23:16 WNDWEN — COMP2VINSEL COMP2VIPSEL COMP2E
N
Type RW RO-0 RW RW RW RW RW RW
15:8 COMP1LO COMP1OU — COMP1PO COMP1OUTSEL —
CK T L
Type RW RO RO-0 RO-0 RO-0 RW RW RO-0
7:0 — — COMP1VINSEL COMP1VIPSEL COMP1E
N
Type RO-0 RO-0 RW RW RW RW RW RW

Bit Name Function


31 COMP2LOCK Comparator 2 lock
It can only be cleared by a system reset.
0: COMP_CSR[31:16] bits are read-write
1: COMP_CSR[31:16] bits are read-only.
30 COMP2OUT Comparator 2 output
0: Output is low
1: Output is high
29:28 NA Reserved
27 COMP2POL Comparator 2 output polarity
0: Output is not inverted
1: Output is inverted
26:24 COMP2OUTSEL Comparator 2 output selection
These bits select the destination of the comparator output.
000 :no selection
001 :timer1 break input
010 :timer1 input capture 1
011 :timer1 OCrefclear input
100 :no selection
101 :no selection
110 :timer3 input capture 1
111 :timer3 Ocrefclear input
23 WNDWEN Window mode enable,window compare mode is controlled by the NCMP

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0 : disable
1 : enable
22 NA Reserved
21:20 COMP2VINSEL Comparator 2 negative input selection (default: 01)
00: DAC2_OUT
01: PAD PA2
10: PAD PA4
11: PAD PA5
19:17 COMP2VIPSEL Comparator 2 positive input selection, preferential select window mode
when the window comparator is enabled
000: PAD PA3
001: PAD PA4
010: PAD PA15
011: PAD PB1
100: Operational amplifier output 2 output
101: PAD PA1
110: Operational amplifier output 1 output
16 COMP2EN Comparator 2 enable
0 : disable
1 : enable
15 COMP1LOCK Comparator 1 lock
It can only be cleared by a system reset.
0: COMP_CSR[15:0] bits are read-write
1: COMP_CSR[15:0] bits are read-only.
14 COMP1OUT Comparator 1 output polarity
0: Output is not inverted
1: Output is inverted
13:12 NA Reserved
11 COMP1POL Comparator 1 output polarity
0: Output is not inverted
1: Output is inverted
10:8 COMP1OUTSEL Comparator 1 output selection
000: no selection
001: timer1 break input
010: timer1 input capture 1
011: timer1 Ocrefclear input
100: no selection
101: no selection
110: timer3 input capture 1
111: timer3 Ocrefclear input
7:6 NA Reserved
5:4 COMP1VINSEL Comparator 1 negative input selection (default: 01)
00: DAC1_OUT

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01: PAD PA0


10: PAD PA4
11: PAD PA5
3:1 COMP1VIPSEL Comparator 1 positive input selection (default: 01)
000: 1wire
001: PAD PA1
010: PAD PA4
011: PAD PA15
100: PAD PB1
101: Operational amplifier output 1 output
0 COMP1EN Comparator 2 enable
1: enable
0: disable

14.4.2. DACCTRL

Address offset: 0x020


Reset value: 0x00000000
Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
7:0 — DAC2BOE DAC1BOE DACREFSEL DACEN
Type RO-0 RO-0 RO-0 WR WR WR WR

Bit Name Function


31:5 NA Reserved
4 DAC2BOE DAC2 channel output buff enable
3 DAC1BOE DAC1 channel output buff enable
2:1 DACREFSEL DAC reference voltage VDACREF selection
11: VDDA
10: 4V
01: 3V
00: 2V
0 DACEN DAC enable
1: enable
0: disable

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14.4.3. DAC1DATA

Address offset: 0x24


Reset value: 0x00000000
Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
7:0 — DAC1DATA
Type RO-0 WR

Bit Name Function


31:7 NA Reserved
6:0 DAC1DATA DAC1 7bit digital input data

14.4.4. DAC2DATA

Address offset: 0x28


Reset value: 0x00000000
Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
7:0 — DAC2DATA
Type RO-0 WR

Bit Name Function


31:7 NA Reserved
6:0 DAC2DATA DAC2 7bit digital input data

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15. Operational amplifier


The FT32F032 and FT32F072 device intergrated two operational amplifiers which is used to processing
analog signal

15.1. Operational amplifier 1/2 description

Operational amplifier 1/2 main features are the following:


1. Calibrate input offset voltage;
2. 2.49MHz gain bandwidth;
3. Operational amplifier reverse gain is -10/-20/-40/-80，non-reverse gain is 11/21/41/81
4. Output can connect to adc channel;
5. Ouput can connect to external pin.

RF(selectable)

PA2 Rin

Rin

OP0TM
ADC

VSSA

PA0
PA1

OP0OUT

Figure 15-1 Operational amplifier block diagram

15.1.1. Calibrate input offset voltage

Input offset voltage can be calibrated by software and the procedure is:
1. Set OpxON to 1, turn on the Operational amplifier;
2. Set OpxTM to 1, Operational amplifier in input offset calibration mode;
3. Set OPxNSEL<1:0> to 2’b00, Negative input connect to GND;
4. Set OPxFCAPE to 1;

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5. Set OPxTODIG to 1, Operational amplifier output to register;


6. Set OpxFR<2:0> to 3’b000, Operational amplifier will not have feedback network;
7. Float negative input (PA2);
8. Set OPxCOF<4:0> to 0x00, delay at least 300μs;
9. Set OPxCOF=OPxCOF+1, delay at least 300μs;
10. If OPxOUT toggle then store the current OPxCOF data as A, and modify OPxCOF to 0x1F, delay at
least 300μs, execute procedure 12, otherwise execute procedure 10;
11. If OPxCOF = 0x1F, then calibrate fail and quit calibration procedure, otherwise execute procedure 9;
12. If OPxOUT toggle then store the current OPxCOF data as B, and modify OPxCOF to (A+B)/2 integer,
calibrate succeed and calibration end, otherwise execute procedure 13;
13. Set OPxCOF = OPxCOF-1, delay at least 300μs;
14. If OPxCOF = 0x00, then calibrate fail and quit calibration procedure, otherwise execute procedure 12

RF(selectable)

PA2 Rin

Rin
OP0TM
ADC

VSSA

PA0
PA1

OP0OUT

Figure 15-2 Operational amplifier in calibration mode

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Fremont Micro Devices FT32F0xxx8 RM

15.2. Operational amplifier register map

offset Register
31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

OP0FCAPE 9

0
OP0PSEL

OPTODIG

OPTOIO
OP0OUT

OP0ON
OP0TM
OP0NSEL
OP_CR OP0FR[2:0] OP0COF[4:0]
-

-
0x30 [1:0]

Reset x x x x x x x x x x x x x x x 0 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0

Note:
1. The base address is common for Operational amplifier and SYSCFG, SYSCFG clock should be enabled
if Operational amplifier is need to use.
2. Operational amplifier can only reset by system reset

15.2.1. OP_CR

Address offset: 0x30


Reset value:0x0000 D8xx
Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 — OP1OUT
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO
15:8 OP1PSEL OP1NSEL OP1FR OP1FCAPE OP1TM
Type RW RW RW RW RW RW RW RW
7:0 OP1TODIG OP1TOIO OP1COF OP1ON
Type RW RW RW RW RW RW RW RW
31:17 NA Reserved
16 OP0OUT OP0 output
15 OP0PSEL OP0 positive input selection
0: PA1
1: GND
14:13 OP0NSEL OP0 negative input selection
2’b00: GND
2’b01: PA2
2’b10: PA2 cascade Rin resistor
2’b11: GND cascade Rin resistor
12:10 OP0FR OP0 gian
3’b0xx: gain
3’b100：-10/ 11
3’b101：-20/ 21
3’b110：-40/41
3’b111：-80/ 81
9 OP0FCAPE OP0 as comparator

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1: OP0 as comparator
0: OP0 as not comparator
8 OP0TM OP0 input offset calibration
1: Input offset calibration mode
0: Normal mode
7 OPTODIG OP0 output to register
1: Enables
0: Disables
6 OPTOIO OP0 output to PA0
1: Enables
0: Disables
5:1 OP0COF OP0 input offset calibration
0 OP0ON OP0 enable
1: Enables
0: Disables

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16. Advanced-control timers(TIM1)

16.1. TIM1 introduction

The advanced-control timers (TIM1) consist of a 16-bit auto-reload counter driven by a programmable
prescaler.

It may be used for a variety of purposes, including measuring the pulse lengths of input signals (input
capture) or generating output waveforms (output compare, PWM, complementary PWM with dead-time
insertion).

Pulse lengths and waveform periods can be modulated from a few microseconds to several milliseconds
using the timer prescaler and the RCC clock controller prescalers.
The advanced-control (TIM1) and general-purpose (TIMx) timers are completely independent, and do not
share any resources. They can be synchronized together as described in Section 16.3.20.

16.2. TIM1 main features

TIM1 timer features include:

 16-bit up, down, up/down auto-reload counter.


 16-bit programmable prescaler allowing dividing (also “on the fly”) the counter clock frequency either by
any factor between 1 and 65535.
 Up to 4 independent channels for:
− Input Capture
− Output Compare
− PWM generation (Edge- and Center-aligned modes)
− One-pulse mode output
 Complementary outputs with programmable dead-time
 Synchronization circuit to control the timer with external signals and to interconnect several timers
together.
 Repetition counter to update the timer registers only after a given number of cycles of the counter.
 Break input to put the timer’s output signals in reset state or in a known state.
 Interrupt/DMA generation on the following events:
− Update: counter overflow/underflow, counter initialization (by software or internal/external trigger)
− Trigger event (counter start, stop, initialization or count by internal/external trigger)
− Input capture
− Output compare
− Break input
 Supports incremental (quadrature) encoder and hall-sensor circuitry for positioning purposes
 Trigger input for external clock or cycle-by-cycle current management

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Internal Clock(CK_INT)
CK_TIM from RCC
ETRP Trigger
ETR Polarity Selection & Edge ETRF Controller TRGO
TIM1_ETR Input Filter
Detector & Prescaler to other timers
to ADC
ITR0
ITR1 ITR TGI Reset, Enable, Up/Down, Count
ITR2 Slave
ITR3 TRC TRGI Mode
Controller
TI1F_ED

TI1FP1 Encoder
TI1FP2 Interface
REP register

Auto-reload register
Repetition
Stop,clear or up/down counter
CK_PSC PSC CK_CNT
+/- CNT counter
prescaler
DTG registers
CC1I UEV
XOR CC1I
TI1FP1 OC1 TIM1_CH1
TIM1_CH1 TI1 Input Filter &
TI1FP2 IC1 IC1PS OC1REF output
Edge Prescaler Capture/Compare 1 Register DTG
control OC1N TIM1_CH1N
detector TRC
CC2I UEV
CC2I
OC2 TIM1_CH2
TIM1_CH2 TI2 Input Filter & TI2FP1 IC2 OC2REF output
Edge TI2FP2 Prescaler IC2PS Capture/Compare 2 Register DTG
control OC2N TIM1_CH2N
detector TRC
CC3I UEV
CC3I
TI3FP3 OC3 TIM1_CH3
TIM1_CH3 TI3 Input Filter & IC3 OC3REF output
Prescaler IC3PS
TI3FP4 DTG
Edge Capture/Compare 3 Register
control OC3N TIM1_CH3N
detector
TRC
CC4I UEV
CC4I
OC4 TIM1_CH4
TIM1_CH4 TI4 Input Filter & TI4FP3 IC4 IC4PS OC4REF output
Edge TI4FP4 Prescaler Capture/Compare 4 Register control
detector TRC
ETRF
TIM1_BKIN BRK Polarity BI
Selection

Interal break event sources

Notes:
Preload registers transferred
Reg
to active registers on UEV event
according to control bit

event

interrupt & DMA output

Figure 16-1 Advanced-control timer block diagram

16.3. TIM1 functional description

16.3.1. Time-base unit

The main block of the programmable advanced-control timer is a 16-bit counter with its related auto-reload
register. The counter can count up, down or both up and down. The counter clock can be divided by a
prescaler.
The counter, the auto-reload register and the prescaler register can be written or read by software. This is
true even when the counter is running.
The time-base unit includes:
 Counter register(TIMx_CNT)
 Prescaler register(TIMx_PSC)

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 Auto-reload register(TIMx_ARR)
 Repetition counter register(TIMx_RCR)
The auto-reload register is preloaded. Writing to or reading from the auto-reload register accesses the
preload register. The content of the preload register are transferred into the shadow register permanently or
at each update event (UEV), depending on the auto-reload preload enable bit (ARPE) in TIMx_CR1 register.
The update event is sent when the counter reaches the overflow (or underflow when downcounting) and if
the UDIS bit equals 0 in the TIMx_CR1 register. It can also be generated by software. The generation of the
update event is described in detailed for each configuration.
The counter is clocked by the prescaler output CK_CNT, which is enabled only when the counter enable bit
(CEN) in TIMx_CR1 register is set (refer also to the slave mode controller description to get more details on
counter enabling).
Note that the counter starts counting 1 clock cycle after setting the CEN bit in the TIMx_CR1 register.

Prescaler description
The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It is based on a
16-bit counter controlled through a 16-bit register (in the TIMx_PSC register). It can be changed on the fly as
this control register is buffered. The new prescaler ratio is taken into account at the next update event.
Figure 16-2 and Figure 16-3 give some examples of the counter behavior when the prescaler ratio is
changed on the fly:
CK_PSC

CEN

CK_CNT

Counter register F7 F8 F9 FA FB FC 00 01 02 03

UEV

Prescaler control register 0 1

Write a new value in TIMx_PSC

Prescaler buffer 0 1

Prescaler counter 0 0 1 0 1 0 1 0 1

Figure 16-2 Counter timing diagram with prescaler division change from 1 to 2
CK_PSC

CEN

CK_CNT

Counter register F7 F8 F9 FA FB FC 00 01

UEV

Prescaler control register 0 3

Write a new value in TIMx_PSC

Prescaler buffer 0 3

Prescaler counter 0 0 1 2 3 0 1 2 3

Figure 16-3 Counter timing diagram with prescaler division change from 1 to 4

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16.3.2. Counter modes

Upcounting mode
In upcounting mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register),
then restarts from 0 and generates a counter overflow event.

If the repetition counter is used, the update event (UEV) is generated after upcounting is repeated for the
number of times programmed in the repetition counter register (TIMx_RCR). Else the update event is
generated at each counter overflow.

Setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller) also
generates an update event.
The UEV event can be disabled by software by setting the UDIS bit in the TIMx_CR1 register. This is to
avoid updating the shadow registers while writing new values in the preload registers. Then no update event
occurs until the UDIS bit has been written to 0. However, the counter restarts from 0, as well as the counter
of the prescaler (but the prescale rate does not change). In addition, if the URS bit (update request selection)
in TIMx_CR1 register is set, setting the UG bit generates an update event UEV but without setting the UIF
flag (thus no interrupt or DMA request is sent). This is to avoid generating both update and capture interrupts
when clearing the counter on the capture event.
When an update event occurs, all the registers are updated and the update flag (UIF bit in TIMx_SR register)
is set (depending on the URS bit):
 The repetition counter is reloaded with the content of TIMx_RCR register,
 The auto-reload shadow register is updated with the preload value (TIMx_ARR),
 The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC register).
The following figures show some examples of the counter behavior for different clock frequencies when
TIMx_ARR=0x36.

CK_PSC

CNT_EN

CK_CNT

Counter register 31 32 33 34 35 36 00 01 02 03 04 05 06 07

Counter overflow

UEV

UIF

Figure 16-4 Counter timing diagram, internal clock divided by 1

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CK_PSC

CNT_EN

CK_CNT

Counter register 34 35 36 00 01 02 03

Counter overflow

UEV

UIF

Figure 16-5 Counter timing diagram, internal clock divided by 2

CK_PSC

CNT_EN

CK_CNT

Counter register 35 36 00 01

Counter overflow

UEV

UIF

Figure 16-6 Counter timing diagram, internal clock divided by 4

CK_PSC

CK_CNT

Counter register 35 36 00 01

Counter overflow

UEV

UIF

Figure 16-7 Counter timing diagram, internal clock divided by N


CK_PSC

CEN

CK_CNT

Counter register 31 32 33 34 35 36 00 01 02 03 04 05 06 07

Counter overflow

UEV

UIF

Auto-reload preload register FF 36

Write a new value in TIMx_ARR

Figure 16-8 Counter timing diagram, update event when ARPE=0

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CK_PSC

CEN

CK_CNT

Counter register F0 F1 F2 F3 F4 F5 00 01 02 03 04 05 06 07

Counter overflow

UEV

UIF

Auto-reload preload register F5 36

Auto-reload shadow register F5 36

Write a new value in TIMx_ARR

Figure 16-9 Counter timing diagram, update event when ARPE=1

Downcounting mode
In downcounting mode, the counter counts from the auto-reload value (content of the TIMx_ARR register)
down to 0, then restarts from the auto-reload value and generates a counter underflow event.

If the repetition counter is used, the update event (UEV) is generated after downcounting is repeated for the
number of times programmed in the repetition counter register (TIMx_RCR). Else the update event is
generated at each counter underflow.

Setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller) also
generates an update event.

The UEV update event can be disabled by software by setting the UDIS bit in TIMx_CR1 register. This is to
avoid updating the shadow registers while writing new values in the preload registers. Then no update event
occurs until UDIS bit has been written to 0. However, the counter restarts from the current auto-reload value,
whereas the counter of the prescaler restarts from 0 (but the prescale rate doesn’t change). In addition, if the
URS bit (update request selection) in TIMx_CR1 register is set, setting the UG bit generates an update
event UEV but without setting the UIF flag (thus no interrupt or DMA request is sent). This is to avoid
generating both update and capture interrupts when clearing the counter on the capture event.
When an update event occurs, all the registers are updated and the update flag (UIF bit in TIMx_SR register)
is set (depending on the URS bit):
 The repetition counter is reloaded with the content of TIMx_RCR register
 The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC register)
 The auto-reload active register is updated with the preload value (content of the TIMx_ARR register).
Note that the auto-reload is updated before the counter is reloaded, so that the next period is the
expected one
The following figures show some examples of the counter behavior for different clock frequencies when
TIMx_ARR=0x36.

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CK_PSC

CNT_EN

CK_CNT

Counter register 05 04 03 02 01 00 36 35 34 33 32 31 30 2F

Counter underflow

UEV

UIF

Figure 16-10 Counter timing diagram, internal clock divided by 1

CK_PSC

CNT_EN

CK_CNT

Counter register 02 01 00 36 35 34 33

Counter underflow

UEV

UIF

Figure 16-11 Counter timing diagram, internal clock divided by 2

CK_PSC

CNT_EN

CK_CNT

Counter register 01 00 36 35

Counter underflow

UEV

UIF

Figure 16-12 Counter timing diagram, internal clock divided by 4

CK_PSC

CK_CNT

Counter register 20 1F 00 36 01

Counter underflow

UEV

UIF

Figure 16-13 Counter timing diagram, internal clock divided by N

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CK_PSC

CEN

CK_CNT

Counter register 05 04 03 02 01 00 36 35 34 33 32 31 30 2F

Counter underflow

UEV

UIF

Auto-reload preload register FF 36

Write a new value in TIMx_ARR

Figure 16-14 Counter timing diagram, update event when repetition counter is not used

Center-aligned mode
In center-aligned mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR
register) – 1, generates a counter overflow event, then counts from the auto-reload value down to 1 and
generates a counter underflow event. Then it restarts counting from 0.

Center-aligned mode is active when the CMS bits in TIMx_CR1 register are not equal to ‘00’. The Output
compare interrupt flag of channels configured in output is set when: the counter counts down (Center
aligned mode 1, CMS = “01”), the counter counts up (Center aligned mode 2, CMS = “10”) the counter
counts up and down (Center aligned mode 3, CMS = “11”).

In this mode, the DIR direction bit in the TIMx_CR1 register cannot be written. It is updated by hardware and
gives the current direction of the counter.

The update event can be generated at each counter overflow and at each counter underflow or by setting
the UG bit in the TIMx_EGR register (by software or by using the slave mode controller) also generates an
update event. In this case, the counter restarts counting from 0, as well as the counter of the prescaler.

The UEV update event can be disabled by software by setting the UDIS bit in the TIMx_CR1 register. This is
to avoid updating the shadow registers while writing new values in the preload registers. Then no update
event occurs until UDIS bit has been written to 0. However, the counter continues counting up and down,
based on the current auto-reload value.
In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the UG bit
generates an UEV update event but without setting the UIF flag (thus no interrupt or DMA request is sent).
This is to avoid generating both update and capture interrupts when clearing the counter on the capture
event.
When an update event occurs, all the registers are updated and the update flag (UIF bit in TIMx_SR register)
is set (depending on the URS bit):
 The repetition counter is reloaded with the content of TIMx_RCR register
 The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC register)
 The auto-reload active register is updated with the preload value (content of the TIMx_ARR register).
Note that if the update source is a counter overflow, the autoreload is updated before the counter is
reloaded, so that the next period is the expected one (the counter is loaded with the new value).
The following figures show some examples of the counter behavior for different clock frequencies.

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CK_PSC

CNT_EN

CK_CNT

Counter register 04 03 02 01 00 01 02 03 04 05 06 05 04 03

Counter underflow

Counter overflow

UEV

UIF

Figure 16-15 Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

CK_PSC

CNT_EN

CK_CNT

Counter register 02 01 00 36 35 34 33

Counter underflow

UEV

UIF

Figure 16-16 Counter timing diagram, internal clock divided by 2

CK_PSC

CNT_EN

CK_CNT

Counter register 35 36 36 35

Counter overflow

UEV

UIF

Figure 16-17 Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36

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CK_PSC

CK_CNT

Counter register 20 1F 01 00 01

Counter underflow

UEV

UIF

Figure 16-18 Counter timing diagram, internal clock divided by N


CK_PSC

CEN

CK_CNT

Counter register 06 05 04 03 02 01 00 01 02 03 04 05 06 07

Counter underflow

UEV

UIF

Auto-reload preload register FD 36

Auto-reload shadow register FD 36

Write a new value in TIMx_ARR

Figure 16-19 Counter timing diagram, update event with ARPE=1 (counter underflow)
CK_PSC

CEN

CK_CNT

Counter register F7 F8 F9 FA FB FC 36 35 34 33 32 31 30 2F

Counter overflow

UEV

UIF

Auto-reload preload register FD 36

Auto-reload shadow register FD 36

Write a new value in TIMx_ARR

Figure 16-20 Counter timing diagram, Update event with ARPE=1 (counter overflow)

16.3.3. Repetition counter

Section 16.3.1: Time-base unit describes how the update event (UEV) is generated with respect to the
counter overflows/underflows. It is actually generated only when the repetition counter has reached zero.
This can be useful when generating PWM signals.
This means that data are transferred from the preload registers to the shadow registers (TIMx_ARR

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Fremont Micro Devices FT32F0xxx8 RM

auto-reload register, TIMx_PSC prescaler register, but also TIMx_CCRx capture/compare registers in
compare mode) every N counter overflows or underflows, where N is the value in the TIMx_RCR repetition
counter register.
The repetition counter is decremented:
 At each counter overflow in upcounting mode,
 At each counter underflow in downcounting mode,
 At each counter overflow and at each counter underflow in center-aligned mode. Although this limits the
maximum number of repetition to 128 PWM cycles, it makes it possible to update the duty cycle twice
per PWM period. When refreshing compare registers only once per PWM period in center-aligned
mode, maximum resolution is 2xT ck, due to the symmetry of the pattern.
The repetition counter is an auto-reload type; the repetition rate is maintained as defined by the TIMx_RCR
register value. When the update event is generated by software (by setting the UG bit in TIMx_EGR register)
or by hardware through the slave mode controller, it occurs immediately whatever the value of the repetition
counter is and the repetition counter is reloaded with the content of the TIMx_RCR register.

Counter-aligned
Edge-aligned mode
mode
Upcounting Downcounting

TIMx_RCR=0 UEV

TIMx_RCR=1 UEV

TIMx_RCR=2 UEV

TIMx_RCR=3 UEV

TIMx_RCR=3
and UEV
re-synchronization
(by SW) (by SW) (by SW)
Update event: Preload registers transferred to active registers and update interrupt
UEV
generated

Figure 16-21 Update rate examples depending on mode and TIMx_RCR register settings

16.3.4. Clock sources

The counter clock can be provided by the following clock sources:


 Internal clock (CK_INT)
 External clock mode1: external input pin
 External clock mode2: external trigger input ETR
 Internal trigger inputs (ITRx): using one timer as prescaler for another timer, for example, you can
configure Timer 1 to act as a prescaler for Timer 2.
Internal clock source(CK_INT)
If the slave mode controller is disabled (SMS=000), then the CEN, DIR (in the TIMx_CR1 register) and UG

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bits (in the TIMx_EGR register) are actual control bits and can be changed only by software (except UG
which remains cleared automatically). As soon as the CEN bit is written to 1, the prescaler is clocked by the
internal clock CK_INT.
Figure 16-22 shows the behavior of the control circuit and the upcounter in normal mode, without prescaler.
Interal clock

CNT_EN

UG

CNT_INIT

CK_CNT=CK_PSC

Counter register 31 32 33 34 35 36 00 01 02 03 04 05 06 07

Figure 16-22 Control circuit in normal mode, internal clock divided by 1


External clock source mode1
This mode is selected when SMS=111 in the TIMx_SMCR register. The counter can count at each rising or
falling edge on a selected input.

TIMx_SMCR
TS[2:0]
T12F or
TI1F or Encoder
ITRx mode
0xx
TI1_ED
100
TRGI External
TI1FP1 clock mode 1
101 CK_PSC
TI2F_rising
TI2 Edge 0 TI2FP2
Filter TI2F_falling 1 110
Detector
ETRF External
111 ETRF
clock mode 2
ICF[3:0] CC2P
TIMx_CCMR1 TIMx_CCER
CK_INT Internal clock
(internal clock) mode

ECE SMS[2:0]
TIMx_SMCR

Figure 16-23 TI2 external clock connection example

For example, to configure the upcounter to count in response to a rising edge on the TI2 input, use the
following procedure:
1. Configure channel 2 to detect rising edges on the TI2 input by writing CC2S = ‘01’ in the TIMx_CCMR1
register.
2. Configure the input filter duration by writing the IC2F[3:0] bits in the TIMx_CCMR1 register (if no filter is
needed, keep IC2F=0000).
3. Select rising edge polarity by writing CC2P=0 in the TIMx_CCER register.
4. Configure the timer in external clock mode 1 by writing SMS=111 in the TIMx_SMCR register.

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5. Select TI2 as the trigger input source by writing TS=110 in the TIMx_SMCR register.
6. Enable the counter by writing CEN=1 in the TIMx_CR1 register.
The capture prescaler is not used for triggering, so you don’t need to configure it.
When a rising edge occurs on TI2, the counter counts once and the TIF flag is set.
The delay between the rising edge on TI2 and the actual clock of the counter is due to the resynchronization
circuit on TI2 input.

TI2

CEN

CK_CNT=CK_PSC

Counter register 34 35 36 0

TIF

Write TIF=0

Figure 16-24 Control circuit in external clock mode 1

External clock source mode 2


This mode is selected by writing ECE=1 in the TIMx_SMCR register.The counter can count at each rising or
falling edge on the external trigger input ETR.

T12F or
TI1F or Encoder
mode

TRGI External
clock mode 1 CK_PSC
fDTS
ETR Filter ETRF External
0 Divider
ETRP down-counter clock mode 2
1 /1,/2,/4,/8

CK_INT Internal clock


ETP ETPS[1:0] ETF[3:0] mode
internal clock
TIMx_SMCR TIMx_SMCR TIMx_SMCR
ECE SMS[2:0]
TIMx_SMCR

Figure 16-25 External trigger input block


For example, to configure the upcounter to count each 2 rising edges on ETR, use the following procedure:
1. As no filter is needed in this example, write ETF[3:0]=0000 in the TIMx_SMCR register.
2. Set the prescaler by writing ETPS[1:0]=01 in the TIMx_SMCR register

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3. Select rising edge detection on the ETR pin by writing ETP=0 in the TIMx_SMCR register.
4. Enable external clock mode 2 by writing ECE=1 in the TIMx_SMCR register.
5. Enable the counter by writing CEN=1 in the TIMx_CR1 register.
The counter counts once each 2 ETR rising edges.
The delay between the rising edge on ETR and the actual clock of the counter is due to the
resynchronization circuit on the ETRP signal.

fCK_INT

CNT_EN
del ay
del ay

ETR

ETRP

ETRF

CK_INT=CK_PSC

COUNTER 34 35 36

Figure 16-26 Control circuit in external clock mode 2

16.3.5. Capture/compare channels

Each Capture/Compare channel is built around a capture/compare register (including a shadow register), a
input stage for capture (with digital filter, multiplexing and prescaler) and an output stage (with comparator
and output control).
Figure 16-27 to Figure 16-30 give an overview of one Capture/Compare channel.
The input stage samples the corresponding Tix input to generate a filtered signal TixF. Then, an edge
detector with polarity selection generates a signal (TixFPx) which can be used as trigger input by the slave
mode controller or as the capture command. It is prescaled before the capture register (IcxPS).

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TI1F_ED
To the slave mode controller

TI1 TI1F_Rising
Filter Edge 0 TI1FP1
fDTS
downcounter detector TI1F_Falling 1
01
TI2FP1 IC1 Divider IC1PS
10
ICF[3:0] /1,/2,/4,/8
CC1P/CC1NP TRC
TIMx_CCMR1 11
TIMx_CCER (from slave mode
controller)

TI2F_Rising
(from channel 2) 0
CC1S[1:0] ICPS[1:0] CCIE
TI2F_Falling 1
TIMx_CCMR1 TIMx_CCER
(from channel 2)

Figure 16-27 Capture/compare channel (example: channel 1 input stage)


The output stage generates an intermediate waveform which is then used for reference: OcxRef (active
high). The polarity acts at the end of the chain.

APB Bus

MCU-peripheral interface
high 8
if 16-bit

low 8

write_in_progress S write CCR1H


Read CCR1H
S read_in_progress
Capture/Compare Preload Register R write CCR1L
Read CCR1L R CC1S[1]
capture_transfer compare_transfer output
CC1S[0]
CC1S[1] mode
OC1PE OC1PE
CC1S[0] Capture/Compare Shadow Register UEV
from time TIMx_CCMR1
IC1PS capture base unit
CC1E CNT>CCR1
Counter CNT=CCR1
CC1G
TIMx_EGR

Figure 16-28 Capture/compare channel 1 main circuit

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Fremont Micro Devices FT32F0xxx8 RM

TIMx_SMCR
OCCS

OCREF_CLR 0 Output OC1


0
enable
ETRF ‘0’ 1
1 x0 circuit
10
ocref_clr_int CC1P
OC1_DT 11
CNT>CCR1 TIMx_CCER
Output Dead-
OC1REF
mode time
CNT=CCR1
controller generator
11
OC1N_DT 0 Output OC1N
10 enable
‘0’ 1 circuit
0x

OC1CE OC1M[2:0] DTG[7:0] CC1NP


TIMx_CCMR1 TIMx_BDTR CC1NE CC1E TIMx_CCER
TIMx_CCER
MOE OSSI OSSR TIMx_BDTR
CC1NE CC1E
TIMx_CCER

Figure 16-29 Output stage of capture/compare channel (channel 1 to 3)

TIMx_SMCR
OCCS

OCREF_CLR
0
ETRF To the master
1 mode
controller
ocref_clr_int
‘0’
0
CNT>CCR4 Output 0 Output OC4
mode OC4REF enable
CNT=CCR4 1 1 circuit
controller

CC4P
TIMx_CCER CC4E TIMx_CCER
MOE OSSI TIMx_BDTR
OC2M[2:0] CC4E OIS4 TIMx_CR2
TIMx_CCMR1 TIMx_CCER

Figure 16-30 Output stage of capture/compare channel (channel 4)


The capture/compare block is made of one preload register and one shadow register. Write and read always
access the preload register.
In capture mode, captures are actually done in the shadow register, which is copied into the preload register.
In compare mode, the content of the preload register is copied into the shadow register which is compared
to the counter.

16.3.6. Input capture mode

In Input capture mode, the Capture/Compare Registers (TIMx_CCRx) are used to latch the value of the
counter after a transition detected by the corresponding Icx signal. When a capture occurs, the

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corresponding CCXIF flag (TIMx_SR register) is set and an interrupt or a DMA request can be sent if they
are enabled. If a capture occurs while the CcxIF flag was already high, then the over-capture flag CcxOF
(TIMx_SR register) is set. CcxIF can be cleared by software by writing it to ‘0’ or by reading the captured
data stored in the TIMx_CCRx register. CcxOF is cleared when you write it to ‘0’.
The following example shows how to capture the counter value in TIMx_CCR1 when TI1 input rises. To do
this, use the following procedure:
 Select the active input: TIMx_CCR1 must be linked to the TI1 input, so write the CC1S bits to 01 in the
TIMx_CCMR1 register. As soon as CC1S becomes different from 00, the channel is configured in input
and the TIMx_CCR1 register becomes read-only.
 Program the input filter duration you need with respect to the signal you connect to the timer when the
input is one of the Tix (IcxF bits in the TIMx_CCMRx register). Let’s imagine that, when toggling, the
input signal is not stable during at must 5 internal clock cycles. We must program a filter duration longer
than these 5 clock cycles. We can validate a transition on TI1 when 8 consecutive samples with the
new level have been detected (sampled at f DTS frequency). Then write IC1F bits to 0011 in the
TIMx_CCMR1 register.
 Program the input prescaler. In our example, we wish the capture to be performed at each valid
transition, so the prescaler is disabled (write IC1PS bits to ‘00’ in the TIMx_CCMR1 register).
 Enable capture from the counter into the capture register by setting the CC1E bit in the TIMx_CCER
register.
 If needed, enable the related interrupt request by setting the CC1IE bit in the TIMx_DIER register,
and/or the DMA request by setting the CC1DE bit in the TIMx_DIER register.
When an input capture occurs:
 The TIMx_CCR1 register gets the value of the counter on the active transition.
 CC1IF flag is set (interrupt flag). CC1OF is also set if at least two consecutive captures occurred
whereas the flag was not cleared.
 An interrupt is generated depending on the CC1IE bit.
 A DMA request is generated depending on the CC1DE bit.
In order to handle the overcapture, it is recommended to read the data before the overcapture flag. This is to
avoid missing an overcapture which could happen after reading the flag and before reading the data.
Note: IC interrupt and/or DMA requests can be generated by software by setting the corresponding CCxG
bit in the TIMx_EGR register.

16.3.7. PWM input mode

This mode is a particular case of input capture mode. The procedure is the same except:
 Two Icx signals are mapped on the same Tix input.
 These 2 Icx signals are active on edges with opposite polarity.
 One of the two TixFP signals is selected as trigger input and the slave mode controller is configured in
reset mode.
For example, you can measure the period (in TIMx_CCR1 register) and the duty cycle (in TIMx_CCR2
register) of the PWM applied on TI1 using the following procedure (depending on CK_INT frequency and
prescaler value):
 Select the active input for TIMx_CCR1: write the CC1S bits to 01 in the TIMx_CCMR1 register (TI1

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selected).
 Select the active polarity for TI1FP1 (used both for capture in TIMx_CCR1 and counter clear): write the
CC1P and CC1NP bits to ‘0’ (active on rising edge).
 Select the active input for TIMx_CCR2: write the CC2S bits to 10 in the TIMx_CCMR1 register (TI1
selected).
 Select the active polarity for TI1FP2 (used for capture in TIMx_CCR2): write the CC2P bit to ‘1’ (active
on falling edge).
 Select the valid trigger input: write the TS bits to 101 in the TIMx_SMCR register (TI1FP1 selected).
 Configure the slave mode controller in reset mode: write the SMS bits to 100 in the TIMx_SMCR
register.
 Enable the captures: write the CC1E and CC2E bits to ‘1’ in the TIMx_CCER register.

TI1

IC1/IC2

COUNTER
5 0 1 2 3 4 5 0

T1CCR1 5

T1CCR2 3

IC1: IC2: IC1:


reset counter m easure m easure
pulse width pulse period

Figure 16-31 PWM input mode timing

16.3.8. Forced output mode

In output mode (CCxS bits = 00 in the TIMx_CCMRx register), each output compare signal (OCxREF and
then Ocx/OcxN) can be forced to active or inactive level directly by software, independently of any
comparison between the output compare register and the counter.
To force an output compare signal (OCXREF/Ocx) to its active level, you just need to write 101 in the OcxM
bits in the corresponding TIMx_CCMRx register. Thus OCXREF is forced high (OCxREF is always active
high) and Ocx get opposite value to CCxP polarity bit.
For example: CCxP=0 (Ocx active high) => Ocx is forced to high level.
The OCxREF signal can be forced low by writing the OcxM bits to 100 in the TIMx_CCMRx register.
Anyway, the comparison between the TIMx_CCRx shadow register and the counter is still performed and
allows the flag to be set. Interrupt and DMA requests can be sent accordingly. This is described in the output
compare mode section below.

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16.3.9. Output compare mode

This function is used to control an output waveform or indicating when a period of time has elapsed.
When a match is found between the capture/compare register and the counter, the output compare function:
 Assigns the corresponding output pin to a programmable value defined by the output compare mode
(OcxM bits in the TIMx_CCMRx register) and the output polarity (CCxP bit in the TIMx_CCER register).
The output pin can keep its level (OCXM=000), be set active (OcxM=001), be set inactive (OcxM=010)
or can toggle (OcxM=011) on match.
 Sets a flag in the interrupt status register (CcxIF bit in the TIMx_SR register).
 Generates an interrupt if the corresponding interrupt mask is set (CCXIE bit in the TIMx_DIER register).
 Sends a DMA request if the corresponding enable bit is set (CcxDE bit in the TIMx_DIER register,
CCDS bit in the TIMx_CR2 register for the DMA request selection).
The TIMx_CCRx registers can be programmed with or without preload registers using the OcxPE bit in the
TIMx_CCMRx register.
In output compare mode, the update event UEV has no effect on OCxREF and Ocx output. The timing
resolution is one count of the counter. Output compare mode can also be used to output a single pulse (in
One Pulse mode).
Output compare mode procedure:
1. Select the counter clock (internal, external, prescaler).
2. Write the desired data in the TIMx_ARR and TIMx_CCRx registers.
3. Set the CcxIE bit if an interrupt request is to be generated.
4. Select the output mode. For example:
− Write OcxM = 011 to toggle Ocx output pin when CNT matches CCRx
− Write OcxPE = 0 to disable preload register
− Write CCxP = 0 to select active high polarity
− Write CcxE = 1 to enable the output
5. Enable the counter by setting the CEN bit in the TIMx_CR1 register.
The TIMx_CCRx register can be updated at any time by software to control the output waveform, provided
that the preload register is not enabled (OcxPE=’0’, else TIMx_CCRx shadow register is updated only at the
next update event UEV). An example is given in Figure 16-32.

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Write B201h in the CC1R register

TIM1_CNT 0039 003A 003B B200 B201 B202 03

TIM1_CCR1 003A B201

oc1ref=OC1

Match detected on CCR1


Interrupt generated if enabled

Figure 16-32 Output compare mode, toggle on OC1

16.3.10. PWM mode

Pulse Width Modulation mode allows you to generate a signal with a frequency determined by the value of
the TIMx_ARR register and a duty cycle determined by the value of the TIMx_CCRx register.
The PWM mode can be selected independently on each channel (one PWM per Ocx output) by writing ‘110’
(PWM mode 1) or ‘111’ (PWM mode 2) in the OcxM bits in the TIMx_CCMRx register. You must enable the
corresponding preload register by setting the OcxPE bit in the TIMx_CCMRx register, and eventually the
auto-reload preload register (in upcounting or center-aligned modes) by setting the ARPE bit in the
TIMx_CR1 register.
As the preload registers are transferred to the shadow registers only when an update event occurs, before
starting the counter, you have to initialize all the registers by setting the UG bit in the TIMx_EGR register.
Ocx polarity is software programmable using the CCxP bit in the TIMx_CCER register. It can be
programmed as active high or active low. Ocx output is enabled by a combination of the CcxE, CcxNE, MOE,
OSSI and OSSR bits (TIMx_CCER and TIMx_BDTR registers).
In PWM mode (1 or 2), TIMx_CNT and TIMx_CCRx are always compared to determine whether
TIMx_CCRx ≤ TIMx_CNT or TIMx_CNT ≤ TIMx_CCRx (depending on the direction of the counter).The timer
is able to generate PWM in edge-aligned mode or center-aligned mode depending on the CMS bits in the
TIMx_CR1 register.

PWM edge-aligned mode


 Upcounting configuration
Upcounting is active when the DIR bit in the TIMx_CR1 register is low. In the following example, we consider
PWM mode 1. The reference PWM signal OCxREF is high as long as TIMx_CNT < TIMx_CCRx else it
becomes low. If the compare value in TIMx_CCRx is greater than the auto-reload value (in TIMx_ARR) then
OCxREF is held at ‘1’. If the compare value is 0 then OcxRef is held at ‘0’. Figure 16-33 shows some
edge-aligned PWM waveforms in an example where TIMx_ARR=8.

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Counter register 0 1 2 3 4 5 6 7 8 0 1

OCxREF
CCRx=4
CCxIF

OCxREF
CCRx=8
CCxIF

OCxREF ‘1’
CCRx>8
CCxIF

OCxREF
‘0’
CCRx=0
CCxIF

Figure 16-33 Edge-aligned PWM waveforms (ARR=8)


 Downcounting configuration
Downcounting is active when DIR bit in TIMx_CR1 register is high. In PWM mode 1, the reference signal
OcxRef is low as long as TIMx_CNT > TIMx_CCRx else it becomes high. If the compare value in
TIMx_CCRx is greater than the auto-reload value in TIMx_ARR, then OCxREF is held at ‘1’. 0% PWM is not
possible in this mode.

PWM center-aligned mode


Center-aligned mode is active when the CMS bits in TIMx_CR1 register are different from ‘00’ (all the
remaining configurations having the same effect on the OcxRef/Ocx signals). The compare flag is set when
the counter counts up, when it counts down or both when it counts up and down depending on the CMS bits
configuration. The direction bit (DIR) in the TIMx_CR1 register is updated by hardware and must not be
changed by software.
Figure 16-34 shows some center-aligned PWM waveforms in an example where:
 TIMx_ARR=8
 PWM mode 1
The flag is set when the counter counts down corresponding to the center-aligned mode 1 selected for
CMS=01 in TIMx_CR1 register.

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Counter register 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1 0 1 2

OCxREF
CCRx=4 CMS=01
CCxIF CMS=10
CMS=11

OCxREF
CCRx=7
CCxIF CMS=10 or 11

OCxREF
CCRx=8 CMS=01
CCxIF CMS=10
CMS=11

OCxREF
CCRx>8
CMS=01
CCxIF CMS=10
CMS=11

OCxREF
CCRx=0
CMS=01
CCxIF CMS=10
CMS=11

Figure 16-34 Center-aligned PWM waveforms (ARR=8)


Hints on using center-aligned mode:
 When starting in center-aligned mode, the current up-down configuration is used. It means that the
counter counts up or down depending on the value written in the DIR bit in the TIMx_CR1 register.
Moreover, the DIR and CMS bits must not be changed at the same time by the software.
 Writing to the counter while running in center-aligned mode is not recommended as it can lead to
unexpected results. In particular:
− The direction is not updated if you write a value in the counter that is greater than the auto-reload
value (TIMx_CNT>TIMx_ARR). For example, if the counter was counting up, it continues to count
up.
− The direction is updated if you write 0 or write the TIMx_ARR value in the counter but no Update
Event UEV is generated.
 The safest way to use center-aligned mode is to generate an update by software (setting the UG bit in
the TIMx_EGR register) just before starting the counter and not to write the counter while it is running.

16.3.11. Complementary outputs and dead-time insertion

The advanced-control timers (TIM1) can output two complementary signals and manage the switching-off
and the switching-on instants of the outputs.
This time is generally known as dead-time and you have to adjust it depending on the devices you have
connected to the outputs and their characteristics (intrinsic delays of level-shifters, delays due to power
switches...)

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You can select the polarity of the outputs (main output Ocx or complementary OcxN) independently for each
output. This is done by writing to the CCxP and CCxNP bits in the TIMx_CCER register.
The complementary signals Ocx and OcxN are activated by a combination of several control bits: the CcxE
and CcxNE bits in the TIMx_CCER register and the MOE, OISx, OISxN, OSSI and OSSR bits in the
TIMx_BDTR and TIMx_CR2 registers. Refer to table:Output control bits for complementary Ocx and OcxN
channels with break feature for more details. In particular, the dead-time is activated when switching to the
IDLE state (MOE falling down to 0).
Dead-time insertion is enabled by setting both CcxE and CcxNE bits, and the MOE bit if the break circuit is
present. There is one 10-bit dead-time generator for each channel. From a reference waveform OCxREF, it
generates 2 outputs Ocx and OcxN. If Ocx and OcxN are active high:
 The Ocx output signal is the same as the reference signal except for the rising edge, which is delayed
relative to the reference rising edge.
 The OcxN output signal is the opposite of the reference signal except for the rising edge, which is
delayed relative to the reference falling edge.
If the delay is greater than the width of the active output (Ocx or OcxN) then the corresponding pulse is not
generated.
The following figures show the relationships between the output signals of the dead-time generator and the
reference signal OCxREF. (we suppose CCxP=0, CCxNP=0, MOE=1, CcxE=1 and CcxNE=1 in these
examples)

OCxREF

delay
OCx

OCxN

delay

Figure 16-35 Complementary output with dead-time insertion

OCxREF

delay
OCx

OCxN

Figure 16-36 Dead-time waveforms with delay greater than the negative pulse.

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OCxREF

OCx

delay
OCxN

Figure 16-37 Dead-time waveforms with delay greater than the positive pulse
The dead-time delay is the same for each of the channels and is programmable with the DTG bits in the
TIMx_BDTR register. Refer to Section: TIM1 break and dead-time register (TIM1_BDTR) for delay
calculation.

Re-directing OCxREF to Ocx or OcxN


In output mode (forced, output compare or PWM), OCxREF can be re-directed to the Ocx output or to OcxN
output by configuring the CcxE and CcxNE bits in the TIMx_CCER register.
This allows you to send a specific waveform (such as PWM or static active level) on one output while the
complementary remains at its inactive level. Other alternative possibilities are to have both outputs at
inactive level or both outputs active and complementary with dead-time.
Note: When only OcxN is enabled (CcxE=0, CcxNE=1), it is not complemented and becomes active as soon
as OCxREF is high. For example, if CCxNP=0 then OcxN=OcxRef. On the other hand, when both Ocx and
OcxN are enabled (CcxE=CcxNE=1) Ocx becomes active when OCxREF is high whereas OcxN is
complemented and becomes active when OCxREF is low.

16.3.12. Using the break function

When using the break function, the output enable signals and inactive levels are modified according to
additional control bits (MOE, OSSI and OSSR bits in the TIMx_BDTR register, OISx and OISxN bits in the
TIMx_CR2 register). In any case, the Ocx and OcxN outputs cannot be set both to active level at a given
time. Refer to Table: Output control bits for complementary Ocx and OcxN channels with break feature for
more details.
Break source can be BKIN input pin or the internal break source:
 Core LOCKUP output
 PVD output
 Failure is detected by the CSS
 Comparator output
When exiting from reset, the break circuit is disabled and the MOE bit is low. You can enable the break
function by setting the BKE bit in the TIMx_BDTR register. The break input polarity can be selected by
configuring the BKP bit in the same register. BKE and BKP can be modified at the same time. When the BKE
and BKP bits are written, a delay of 1 APB clock cycle is applied before the writing is effective. Consequently,
it is necessary to wait 1 APB clock period to correctly read back the bit after the write operation.
Because MOE falling edge can be asynchronous, a resynchronization circuit has been inserted between the
actual signal (acting on the outputs) and the synchronous control bit (accessed in the TIMx_BDTR register).

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It results in some delays between the asynchronous and the synchronous signals. In particular, if you write
MOE to 1 whereas it was low, you must insert a delay (dummy instruction) before reading it correctly. This is
because you write the asynchronous signal and read the synchronous signal.
When a break occurs (selected level on the break input):
 The MOE bit is cleared asynchronously, putting the outputs in inactive state, idle state or in reset state
(selected by the OSSI bit). This feature functions even if the MCU oscillator is off.
 Each output channel is driven with the level programmed in the OISx bit in the TIMx_CR2 register as
soon as MOE=0. If OSSI=0 then the timer releases the enable output else the enable output remains
high.
 When complementary outputs are used:
− The outputs are first put in reset state inactive state (depending on the polarity). This is done
asynchronously so that it works even if no clock is provided to the timer.
− If the timer clock is still present, then the dead-time generator is reactivated in order to drive the
outputs with the level programmed in the OISx and OISxN bits after a dead-time. Even in this case,
Ocx and OcxN cannot be driven to their active level together. Note that because of the
resynchronization on MOE, the dead-time duration is a bit longer than usual (around 2 ck_tim
clock cycles).
− If OSSI=0 then the timer releases the enable outputs else the enable outputs remain or become
high as soon as one of the CcxE or CcxNE bits is high.
 The break status flag (BIF bit in the TIMx_SR register) is set. An interrupt can be generated if the BIE
bit in the TIMx_DIER register is set.
 If the AOE bit in the TIMx_BDTR register is set, the MOE bit is automatically set again at the next
update event UEV. This can be used to perform a regulation, for instance. Else, MOE remains low until
you write it to ‘1’ again. In this case, it can be used for security and you can connect the break input to
an alarm from power drivers, thermal sensors or any security components.
Note: The break inputs is acting on level. Thus, the MOE cannot be set while the break input is active
(neither automatically nor by software). In the meantime, the status flag BIF cannot be cleared.
The break can be generated by the BRK input which has a programmable polarity and an enable bit BKE in
the TIMx_BDTR Register.
In addition to the break input and the output management, a write protection has been implemented inside
the break circuit to safeguard the application. It allows you to freeze the configuration of several parameters
(dead-time duration, Ocx/OcxN polarities and state when disabled, OcxM configurations, break enable and
polarity). You can choose from 3 levels of protection selected by the LOCK bits in the TIMx_BDTR register.
Refer to Section 16.4.18: TIM1 break and dead-time register (TIM1_BDTR). The LOCK bits can be written
only once after an MCU reset.
The Figure 16-38 shows an example of behavior of the outputs in response to a break.

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OCxREF

OCx
(OCxN not implemented,CCxP=0,OISx=1)

OCx
(OCxN not implemented,CCxP=0,OISx=0)

OCx
(OCxN not implemented,CCxP=1,OISx=1)

OCx
(OCxN not implemented,CCxP=1,OISx=0)

OCx

OCxN delay delay delay


(CCxE=1,CCxP=0,OISx=0,CCxNE=1,CCxNP=0,OISxN=1)

OCx

OCxN delay delay delay


(CCxE=1,CCxP=0,OISx=0,CCxNE=1,CCxNP=0,OISxN=1)

OCx

OCxN delay
(CCxE=1,CCxP=0,OISx=1,CCxNE=1,CCxNP=1,OISxN=1)

OCx
OCxN delay
(CCxE=1,CCxP=0,OISx=0,CCxNE=0,CCxNP=0,OISxN=1)

OCx
OCxN
(CCxE=1,CCxP=0,CCxNE=0,CCxNP=0,OISx=OISxN=0 or OISx=OISxN=1)

Figure 16-38 Output behavior in response to a break

16.3.13. Clearing the OCxREF signal on an external event

The OCxREF signal of a given channel can be cleared when a high level is applied on the
OCREF_CLR_INPUT (OcxCE enable bit in the corresponding TIMx_CCMRx register set to 1). OCxREF
remains low until the next update event (UEV) occurs. This function can only be used in Output compare
and PWM modes. It does not work in Forced mode.
OCREF_CLR_INPUT can be selected between the OCREF_CLR input and ETRF (ETR after the filter) by
configuring the OCCS bit in the TIMx_SMCR register.
For example, the OCxREF signal can be connected to the output of a comparator to be used for current

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handling. In this case, the ETR must be configured as follow:


1. The External Trigger Prescaler should be kept off: bits ETPS[1:0] of the TIMx_SMCR register set to ‘00’.
2. The external clock mode 2 must be disabled: bit ECE of the TIMx_SMCR register set to ‘0’.
3. The External Trigger Polarity (ETP) and the External Trigger Filter (ETF) can be configured according to
the user needs.
Figure 16-39 shows the behavior of the OCxREF signal when the ETRF Input becomes High, for both
values of the enable bit OcxCE. In this example, the timer TIMx is programmed in PWM mode.

CCRx

Counter

ETRF

OCxREF
(OCxCE=0)

OCxREF
(OCxCE=0)

OCxREF_CLR OCxREF_CLR
become high still high

Figure 16-39 Clearing TIMx OCxREF


Note: In case of a PWM with a 100% duty cycle (if CCRx>ARR), then OCxREF is enabled again at the next
counter overflow.

16.3.14. 6-step PWM generation

When complementary outputs are used on a channel, preload bits are available on the OcxM, CcxE and
CcxNE bits. The preload bits are transferred to the shadow bits at the COM commutation event. Thus you
can program in advance the configuration for the next step and change the configuration of all the channels
at the same time. COM can be generated by software by setting the COM bit in the TIMx_EGR register or by
hardware (on TRGI rising edge).
A flag is set when the COM event occurs (COMIF bit in the TIMx_SR register), which can generate an
interrupt (if the COMIE bit is set in the TIMx_DIER register) or a DMA request (if the COMDE bit is set in the
TIMx_DIER register).
The Figure 16-40 describes the behavior of the Ocx and OcxN outputs when a COM event occurs, in 3
different examples of programmed configurations.

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CCRx

Counter

OCxREF

Write COM to 1

COM event

CCxE=1 Write OCxM to 100 CCxE=1


CCxNE=0 CCxNE=0
OCxM=100 OCxM=100
OCx
Example 1
OCxN
CCxE=1 Write CCxNE to 1 CCxE=0
CCxNE=0 and OCxM to 101 CCxNE=1
OCx OCxM=100 OCxM=101
Example 2
OCxN
CCxE=1 Write CCxNE to 0 CCxE=1
CCxNE=0 and OCxM to 100 CCxNE=0
OCxM=100 OCxM=100
OCx
Example 3
OCxN

Figure 16-40 6-step generation, COM example (OSSR=1)

16.3.15. One-pulse mode

One-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to be started in
response to a stimulus and to generate a pulse with a programmable length after a programmable delay.
Starting the counter can be controlled through the slave mode controller. Generating the waveform can be
done in output compare mode or PWM mode. You select One-pulse mode by setting the OPM bit in the
TIMx_CR1 register. This makes the counter stop automatically at the next update event UEV.
A pulse can be correctly generated only if the compare value is different from the counter initial value. Before
starting (when the timer is waiting for the trigger), the configuration must be:
 In upcounting: CNT ＜ CCRx ≤ ARR (in particular, 0 < CCRx).
 In downcounting: CNT > CCRx

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TI2

OC1REF

OC1

TIM1_ARR

TIM1_CCR1

0 Tdelay TIME
Tpulse

Figure 16-41 Example of one pulse mode


For example you may want to generate a positive pulse on OC1 with a length of 𝑇𝑝𝑢𝑙𝑠𝑒 and after a delay of
𝑇𝑑𝑒𝑙𝑎𝑦 as soon as a positive edge is detected on the TI2 input pin.
Let’s use TI2FP2 as trigger 1:
 Map TI2FP2 to TI2 by writing CC2S=’01’ in the TIMx_CCMR1 register.
 TI2FP2 must detect a rising edge, write CC2P=’0’ and CC2NP=’0’ in the TIMx_CCER register.
 Configure TI2FP2 as trigger for the slave mode controller (TRGI) by writing TS=’110’ in the
TIMx_SMCR register.
 TI2FP2 is used to start the counter by writing SMS to ‘110’ in the TIMx_SMCR register (trigger mode).
The OPM waveform is defined by writing the compare registers (taking into account the clock frequency and
the counter prescaler).
 The 𝑇𝑑𝑒𝑙a𝑦 is defined by the value written in the TIMx_CCR1 register.
 The 𝑇𝑝𝑢𝑙𝑠𝑒 is defined by the difference between the auto-reload value and the compare value
(TIMx_ARR-TIMx_CCR1+1)
 Let’s say you want to build a waveform with a transition from ‘0’ to ‘1’ when a compare match occurs
and a transition from ‘1’ to ‘0’ when the counter reaches the auto-reload value. To do this you enable
PWM mode 2 by writing OC1M=111 in the TIMx_CCMR1 register. You can optionally enable the
preload registers by writing OC1PE=’1’ in the TIMx_CCMR1 register and ARPE in the TIMx_CR1
register. In this case you have to write the compare value in the TIMx_CCR1 register, the auto-reload
value in the TIMx_ARR register, generate an update by setting the UG bit and wait for external trigger
event on TI2. CC1P is written to ‘0’ in this example.
In our example, the DIR and CMS bits in the TIMx_CR1 register should be low.
You only want 1 pulse (Single mode), so you write ‘1’ in the OPM bit in the TIMx_CR1 register to stop the
counter at the next update event (when the counter rolls over from the auto-reload value back to 0). When
OPM bit in the TIMx_CR1 register is set to ‘0’, so the Repetitive Mode is selected.

Particular case: Ocx fast enable


In One-pulse mode, the edge detection on Tix input set the CEN bit which enables the counter. Then the
comparison between the counter and the compare value makes the output toggle. But several clock cycles

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are needed for these operations and it limits the minimum delay 𝑇𝑑𝑒𝑙𝑎𝑦 min we can get.
If you want to output a waveform with the minimum delay, you can set the OcxFE bit in the TIMx_CCMRx
register. Then OcxRef (and Ocx) are forced in response to the stimulus, without taking in account the
comparison. Its new level is the same as if a compare match had occurred. OcxFE acts only if the channel is
configured in PWM1 or PWM2 mode.

16.3.16. Encoder interface mode

To select Encoder Interface mode write SMS=‘001’ in the TIMx_SMCR register if the counter is counting on
TI2 edges only, SMS=’010’ if it is counting on TI1 edges only and SMS=’011’ if it is counting on both TI1 and
TI2 edges.
Select the TI1 and TI2 polarity by programming the CC1P and CC2P bits in the TIMx_CCER register. When
needed, you can program the input filter as well. CC1NP and CC2NP must be kept low.
The two inputs TI1 and TI2 are used to interface to an incremental encoder. Refer to Table 16-1. The
counter is clocked by each valid transition on TI1FP1 or TI2FP2 (TI1 and TI2 after input filter and polarity
selection, TI1FP1=TI1 if not filtered and not inverted, TI2FP2=TI2 if not filtered and not inverted) assuming
that it is enabled (CEN bit in TIMx_CR1 register written to ‘1’). The sequence of transitions of the two inputs
is evaluated and generates count pulses as well as the direction signal. Depending on the sequence the
counter counts up or down, the DIR bit in the TIMx_CR1 register is modified by hardware accordingly. The
DIR bit is calculated at each transition on any input (TI1 or TI2), whatever the counter is counting on TI1 only,
TI2 only or both TI1 and TI2.
Encoder interface mode acts simply as an external clock with direction selection. This means that the
counter just counts continuously between 0 and the auto-reload value in the TIMx_ARR register (0 to ARR
or ARR down to 0 depending on the direction). So you must configure TIMx_ARR before starting. In the
same way, the capture, compare, prescaler, repetition counter, trigger output features continue to work as
normal. Encoder mode and External clock mode 2 are not compatible and must not be selected together.
In this mode, the counter is modified automatically following the speed and the direction of the incremental
encoder and its content, therefore, always represents the encoder’s position. The count direction
correspond to the rotation direction of the connected sensor. The table summarizes the possible
combinations, assuming TI1 and TI2 don’t switch at the same time.
Table 16-1 Counting direction versus encoder signals

Level on opposite TI1FP1 signal TI2FP2 signal

Active edge signal (TI1FP1 for TI2)


Rising Falling Rising Falling
(TI2FP2 for TI1)

High Down Up —— ——
TI1
Low Up Down —— ——
High —— —— Up Down
TI2
Low —— —— Down Up
High Down Up Up Down
TI1 or TI2
Low Up Down Down Up
An external incremental encoder can be connected directly to the MCU without external interface logic.
However, comparators are normally be used to convert the encoder’s differential outputs to digital signals.

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This greatly increases noise immunity. The third encoder output which indicate the mechanical zero position,
may be connected to an external interrupt input and trigger a counter reset.
Figure 16-42 gives an example of counter operation, showing count signal generation and direction control.
It also shows how input jitter is compensated where both edges are selected. This might occur if the sensor
is positioned near to one of the switching points. For this example we assume that the configuration is the
following:
 CC1S=01 (TIMx_CCMR1 register, TI1FP1 mapped on TI1).
 CC2S=01 (TIMx_CCMR2 register, TI1FP2 mapped on TI2).
 CC1P=0 (TIMx_CCER register, TI1FP1 non-inverted, TI1FP1=TI1).
 CC2P=0 (TIMx_CCER register, TI1FP2 non-inverted, TI1FP2= TI2).
 SMS=011 (TIMx_SMCR register, both inputs are active on both rising and falling edges).
 CEN=1 (TIMx_CR1 register, Counter enabled).

forward jitter backward jitter forward

TI1

TI2

Counter

UP DOWN UP

Figure 16-42 Example of counter operation in encoder interface mode


Figure 16-43 gives an example of counter behavior when TI1FP1 polarity is inverted (same configuration
as above except CC1P=’1’).

forward jitter backward jitter forward

TI1

TI2

Counter

DOWN UP DOWN

Figure 16-43 Example of encoder interface mode with TI1FP1 polarity inverted
The timer, when configured in Encoder Interface mode provides information on the sensor’s current position.
You can obtain dynamic information (speed, acceleration, deceleration) by measuring the period between
two encoder events using a second timer configured in capture mode. The output of the encoder which
indicates the mechanical zero can be used for this purpose. Depending on the time between two events, the

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counter can also be read at regular times. You can do this by latching the counter value into a third input
capture register if available (then the capture signal must be periodic and can be generated by another
timer). When available, it is also possible to read its value through a DMA request generated by a real-time
clock.

16.3.17. Timer input XOR function

The TI1S bit in the TIMx_CR2 register, allows the input filter of channel 1 to be connected to the output of a
XOR gate, combining the four input pins TIMx_CH1, TIMx_CH2 , TIMx_CH3 and TIMx_CH4.
The XOR output can be used with all the timer input functions such as trigger or input capture.

16.3.18. Interfacing with Hall sensors

This is done using the advanced-control timers (TIM1) to generate PWM signals to drive the motor and
another timer TIMx (TIM3) referred to as “interfacing timer”. The “interfacing timer” captures the 3 timer input
pins (CC1, CC2, CC3, CC4) connected through a XOR to the TI1 input channel (selected by setting the TI1S
bit in the TIMx_CR2 register).
The slave mode controller is configured in reset mode; the slave input is TI1F_ED. Thus, each time one of
the 4 inputs toggles, the counter restarts counting from 0. This creates a time base triggered by any change
on the Hall inputs.
On the “interfacing timer”, capture/compare channel 1 is configured in capture mode, capture signal is TRC
The captured value, which corresponds to the time elapsed between 2 changes on the inputs, gives
information about motor speed.
The “interfacing timer” can be used in output mode to generate a pulse which changes the configuration of
the channels of the advanced-control timer (TIM1) (by triggering a COM event). The TIM1 timer is used to
generate PWM signals to drive the motor. To do this, the interfacing timer channel must be programmed so
that a positive pulse is generated after a programmed delay (in output compare or PWM mode). This pulse
is sent to the advanced-control timer (TIM1) through the TRGO output.
Example: you want to change the PWM configuration of your advanced-control timer TIM1 after a
programmed delay each time a change occurs on the Hall inputs connected to one of the TIMx timers.
 Configure 4 timer inputs XORed to the TI1 input channel by writing the TI1S bit in the TIMx_CR2
register to ‘1’,
 Program the time base: write the TIMx_ARR to the max value (the counter must be cleared by the TI1
change. Set the prescaler to get a maximum counter period longer than the time between 2 changes on
the sensors,
 Program channel 1 in capture mode (TRC selected): write the CC1S bits in the TIMx_CCMR1 register
to ‘01’. You can also program the digital filter if needed,
 Program channel 2 in PWM 2 mode with the desired delay: write the OC2M bits to ‘111’ and the CC2S
bits to ‘00’ in the TIMx_CCMR1 register,
 Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2 register to ‘101’,
In the advanced-control timer TIM1, the right ITR input must be selected as trigger input, the timer is
programmed to generate PWM signals, the capture/compare control signals are preloaded (CCPC=1 in the

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TIMx_CR2 register) and the COM event is controlled by the trigger input (CCUS=1 in the TIMx_CR2
register). The PWM control bits (CcxE, OcxM) are written after a COM event for the next step (this can be
done in an interrupt subroutine generated by the rising edge of OC2REF).

TIH1

TIH2

TIH3

Counter
CCR2

CCR1 C7A3 C7A8 C794 C7A5 C7AB C796

TRGO=
OC2REF

COM

OC1

OC1N

OC2

OC2N

OC3

OC3N

Write CCxE, CCxNE and


OCxM for next step

Figure 16-44 Example of hall sensor interface

16.3.19. TIMx and external trigger synchronization

The TIMx timer can be synchronized with an external trigger in several modes: Reset mode, Gated mode
and Trigger mode.

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Slave mode: Reset mode


The counter and its prescaler can be reinitialized in response to an event on a trigger input. Moreover, if the
URS bit from the TIMx_CR1 register is low, an update event UEV is generated. Then all the preloaded
registers (TIMx_ARR, TIMx_CCRx) are updated.
In the following example, the upcounter is cleared in response to a rising edge on TI1 input:
 Configure the channel 1 to detect rising edges on TI1. Configure the input filter duration (in this example,
we don’t need any filter, so we keep IC1F=0000). The capture prescaler is not used for triggering, so
you don’t need to configure it. The CC1S bits select the input capture source only, CC1S = 01 in the
TIMx_CCMR1 register. Write CC1P=0 and CC1NP=’0’ in TIMx_CCER register to validate the polarity
(and detect rising edges only).
 Configure the timer in reset mode by writing SMS=100 in TIMx_SMCR register. Select TI1 as the input
source by writing TS=101 in TIMx_SMCR register.
 Start the counter by writing CEN=1 in the TIMx_CR1 register.
The counter starts counting on the internal clock, then behaves normally until TI1 rising edge. When TI1
rises, the counter is cleared and restarts from 0. In the meantime, the trigger flag is set (TIF bit in the
TIMx_SR register) and an interrupt request, or a DMA request can be sent if enabled (depending on the TIE
and TDE bits in TIMx_DIER register).
The following figure shows this behavior when the auto-reload register TIMx_ARR=0x36. The delay
between the rising edge on TI1 and the actual reset of the counter is due to the resynchronization circuit on
TI1 input.

TI1

UG

ck_cnt=ck_psc

Counter register 30 31 32 33 34 35 36 0 1 2 3 0 1 2 3

TIF

Figure 16-45 Control circuit in reset mode

Slave mode: Gated mode


The counter can be enabled depending on the level of a selected input.
In the following example, the upcounter counts only when TI1 input is low:
 Configure the channel 1 to detect low levels on TI1. Configure the input filter duration (in this example,
we don’t need any filter, so we keep IC1F=0000). The capture prescaler is not used for triggering, so
you don’t need to configure it. The CC1S bits select the input capture source only, CC1S=01 in
TIMx_CCMR1 register. Write CC1P=1 and CC1NP=’0’ in TIMx_CCER register to validate the polarity
(and detect low level only).
 Configure the timer in gated mode by writing SMS=101 in TIMx_SMCR register. Select TI1 as the input
source by writing TS=101 in TIMx_SMCR register.

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 Enable the counter by writing CEN=1 in the TIMx_CR1 register (in gated mode, the counter doesn’t
start if CEN=0, whatever is the trigger input level).
The counter starts counting on the internal clock as long as TI1 is low and stops as soon as TI1 becomes
high. The TIF flag in the TIMx_SR register is set both when the counter starts or stops.
The delay between the rising edge on TI1 and the actual stop of the counter is due to the resynchronization
circuit on TI1 input.

Figure 16-46 Control circuit in gated mode

Slave mode: Trigger mode


The counter can start in response to an event on a selected input.
In the following example, the upcounter starts in response to a rising edge on TI2 input:
 Configure the channel 2 to detect rising edges on TI2. Configure the input filter duration (in this example,
we don’t need any filter, so we keep IC2F=0000). The capture prescaler is not used for triggering, so
you don’t need to configure it. The CC2S bits are configured to select the input capture source only,
CC2S=01 in TIMx_CCMR1 register. Write CC2P=1 and CC2NP=0 in TIMx_CCER register to validate
the polarity (and detect low level only).
 Configure the timer in trigger mode by writing SMS=110 in TIMx_SMCR register. Select TI2 as the input
source by writing TS=110 in TIMx_SMCR register.
When a rising edge occurs on TI2, the counter starts counting on the internal clock and the TIF flag is set.
The delay between the rising edge on TI2 and the actual start of the counter is due to the resynchronization
circuit on TI2 input.

Figure 16-47 Control circuit in trigger mode

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Slave mode: external clock mode 2 + trigger mode


The external clock mode 2 can be used in addition to another slave mode (except external clock mode 1 and
encoder mode). In this case, the ETR signal is used as external clock input, and another input can be
selected as trigger input (in reset mode, gated mode or trigger mode). It is recommended not to select ETR
as TRGI through the TS bits of TIMx_SMCR register.
In the following example, the upcounter is incremented at each rising edge of the ETR signal as soon as a
rising edge of TI1 occurs:
1. Configure the external trigger input circuit by programming the TIMx_SMCR register as follows:
− ETF=0000:no filter
− ETPS=00:prescaler disabled
− ETP=0:detection of rising edges on ETR and ECE=1 to enable the external clock mode 2.
2. Configure the channel 1 as follows, to detect rising edges on TI:
− IC1F=0000:no filter.
− The capture prescaler is not used for triggering and does not need to be configured.
− CC1S=01in TIMx_CCMR1 register to select only the input capture source
− CC1P=0 and CC1NP=’0’ in TIMx_CCER register to validate the polarity (and detect rising edge
only).
3. Configure the timer in trigger mode by writing SMS=110 in TIMx_SMCR register. Select TI1 as the input
source by writing TS=101 in TIMx_SMCR register.
A rising edge on TI1 enables the counter and sets the TIF flag. The counter then counts on ETR rising
edges.
The delay between the rising edge of the ETR signal and the actual reset of the counter is due to the
resynchronization circuit on ETRP input.

TI1

CNT_EN

ETR

CK_CNT=CK_PSC

Counter register 34 35 36

TIF

Figure 16-48 Control circuit in external clock mode 2 + trigger mode

16.3.20. Timer synchronization

The TIM timers are linked together internally for timer synchronization or chaining. Refer to Section 17.3.15:
Timer synchronization for details.

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16.3.21. Debug mode

When the microcontroller enters debug mode (Cortex™-M0 core halted), the TIMx counter either continues
to work normally or stops, depending on DBG_TIMx_STOP configuration bit in DBG module.

16.4. TIM1 register map

The following table shows the TIM1 register map and reset values.
31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10
Address offset Name

0
CMS[1:0]
CKD[1:0]

ARPE

UDIS
OPM

URS

CEN
DIR
TIM1_CR1
–

–
0x00

Reset x x x x x x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0

OIS3N

OIS2N

OIS1N

CCDS

CCUS

CCPC
OIS4

OIS3

OIS2

OIS1

TI1S
TIM1_CR2 MMS[2:0]
–

–
0x04

Reset x x x x x x x x x x x x x x x x x 0 0 0 0 1 1 1 0 0 0 0 0 0 x 0

ETPS[1:0]

MSM
ECE
ETP
TIM1_SMCR ETF[3:0] TS[2:0] SMS[2:0]
–

–
0x08

Reset x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 x 0 0 0
COMDE

CC4DE

CC3DE

CC2DE

CC1DE

COMIE

CC4IE

CC3IE

CC2IE

CC1IE
UDE
TDE

UIE
BIE

TIE
TIM1_DIER
–

0x0C

Reset x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CC4OF

CC3OF

CC2OF

CC1OF

COMIF

CC4IF

CC3IF

CC2IF

CC1IF

UIF
BIF

TIF
TIM1_SR
–

0x10 –

Reset x x x x x x x x x x x x x x x x x x x 0 0 0 0 x 0 0 0 0 0 0 0 0

COMG

CC4G

CC3G

CC2G

CC1G
BG

TG

UG
TIM1_EGR
–

0x14

Reset x x x x x x x x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0
CC2S[1:0]

CC1S[1:0]
OC2CE

TIM1_CCMR
CC2PE

CC2FE

CC1CE

CC1PE

CC1FE
1 OC2M[2:0] OC1M[2:0]
–

(output mode)

Reset x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x18
CC2S[1:0]

CC1S[1:0]
IC2F[3:0]

IC1F[3:0]

TIM1_CCMR
IC2PSC IC1PSC
1
–

[1:0] [1:0]
(input mode)

Reset x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

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CC4S[1:0]

CC3S[1:0]
OC4CE
TIM1_CCMR

CC4PE

CC4FE

CC3CE

CC3PE

CC3FE
2 OC4M[2:0] OC3M[2:0]

–
(output mode)

Reset x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x1C

CC4S[1:0]

CC3S[1:0]
IC4F[3:0]

IC3F[3:0]
TIM1_CCMR
IC4PSC IC3PSC
2
–

–
[1:0] [1:0]
(input mode)

Reset x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CC3NP

CC3NE

CC2NP

CC2NE

CC1NP

CC1NE
CC4P

CC4E

CC3P

CC3E

CC2P

CC2E

CC1P

CC1E
TIM1_CCER
–

–
0x20

Reset x x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TIM1_CNT CNT[15:0]
–

–
0x24

Reset x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TIM1_PSC PSC[15:0]
–

–
0x28

Reset x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TIM1_ARR ARR[15:0]
–

–
0x2C

Reset x x x x x x x x x x x x x x x x 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

TIM1_RCR REP[7:0]
–

–
0x30

Reset x x x x x x x x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0

TIM1_CCR1 CCR1[15:0]
–

0x34

Reset x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TIM1_CCR2 CCR2[15:0]
–

0x38

Reset x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TIM1_CCR3 CCR3[15:0]
–

0x3C

Reset x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TIM1_CCR4 CCR4[15:0]
–

0x40

Reset x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
LOCK[1:0]
OSSR
MOE

OSSI
AOE

BKP

BKE

TIM1_BDTR DTG[7:0]
–

0x44

Reset x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TIM1_DCR DBL[4:0] DBA[4:0]


–

0x48

Reset x x x x x x x x x x x x x x x x x x x 0 0 0 0 0 x x x 0 0 0 0 0

TIM1_DMAR DMAB[15:0]
–

0x4C

Reset x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

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16.4.1. TIM1 control register 1(TIM1_CR1)

Address offset: 0x00


Reset value: 0x0000
bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 — CKD[1:0]
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RW RW
7:0 ARPE CMS[1:0] DIR OPM URS UDIS CEN
type RW RW RW RW RW RW RW RW

Bit Name Function


31:10 NA Reserved, undefined
9:8 CKD[1:0] Clock division
This bit-field indicates the division ratio between the timer clock (CK_INT)
frequency and the dead-time and sampling clock (𝑡𝐷𝑇𝑆 ) used by the
dead-time generators and the digital filters(ETR, Tix)
00: 𝑡𝐷𝑇𝑆 = 𝑡𝐶𝐾_𝐼𝑁𝑇
01: 𝑡𝐷𝑇𝑆 = 2 ∗ 𝑡𝐶𝐾_𝐼𝑁𝑇
10: 𝑡𝐷𝑇𝑆 = 4 ∗ 𝑡𝐶𝐾_𝐼𝑁𝑇
11: Reserved, do not program this value
7 ARPE Auto-reload preload enable
0: TIMx_ARR register is not buffered and it can be written directly
1: TIMx_ARR register is buffered
6:5 CMS[1:0] Center-aligned mode selection
00: Edge-aligned mode. The counter counts up or down depending on the
direction bit (DIR).
01: Center-aligned mode 1. The counter counts up and down alternatively.
Output compare interrupt flags of channels configured in output (CCxS=00 in
TIMx_CCMRx register) are set only when the counter is counting down.
10: Center-aligned mode 2. The counter counts up and down alternatively.
Output compare interrupt flags of channels configured in output (CCxS=00 in
TIMx_CCMRx register) are set only when the counter is counting up.
11:Center-aligned mode 3. The counter counts up and down alternatively.
Output compare interrupt flags of channels configured in output (CCxS=00 in
TIMx_CCMRx register) are set both when the counter is counting up or
down.
Note: It is not allowed to switch from edge-aligned mode to center-aligned
mode as long as the counter is enabled (CEN=1).
4 DIR Direction
0: Counter used as upcounter

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1: Counter used as downcounter


Note: This bit is read only when the timer is configured in Center-aligned
mode or Encoder mode.
3 OPM One pulse mode
0: Counter is not stopped at update event
1: Counter stops counting at the next update event (clearing the bit CEN)
2 URS Update request source This bit is set and cleared by software to select the
UEV event sources.
0: if UDIS allows to generate an update event, Any of the following events
generate an update interrupt or DMA request if enabled.
– Counter overflow/underflow
– Setting the UG bit
– Update generation by the reset trigger event
1: Only counter overflow/underflow generates an update interrupt or DMA
request if enabled.
1 UDIS Update disable
This bit is set and cleared by software to enable/disable UEV event
generation.
0: UEV enabled. The Update (UEV) event is generated by one of the
following events:
− Counter overflow/underflow
− Setting the UG bit by software
− Update generation through the slave mode controller
1: UEV disabled. The Update event is not generated, shadow registers keep
their value (ARR, PSC, CCRx). However the counter and the prescaler are
reinitialized if the UG bit is set or if a hardware reset is received from the
slave mode controller.
0 CEN Counter enable
0: Counter disabled
1: Counter enabled
Note: External clock, gated mode and encoder mode can work only if the
CEN bit has been previously set by software. However trigger mode can set
the CEN bit automatically by hardware.

16.4.2. TIM1 control register 2(TIM1_CR2)

Address offset: 0x04


Reset value: 0x0000
bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 — OIS4 OIS3N OIS3 OIS2N OIS2 OIS1N OIS1
type RO-0 RW RW RW RW RW RW RW
7:0 TI1S MMS[2:0] CCDS CCUS — CCPC

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type RW RW RW RW RW RW RO-0 RW

Bit Name Function


31:15 NA Reserved, undefined.
14 OIS4 Output Idle state 4 (OC4 output) .refer to OIS1 bit
13 OIS3N Output Idle state 3 (OC3N output). Refer to OIS1N bit
12 OIS3 Output Idle state 3 (OC3 output). Refer to OIS1 bit
11 OIS2N Output Idle state 2 (OC2N output). Refer to OIS1N bit
10 OIS2 Output Idle state 2 (OC2 output) . refer to OIS1 bit
9 OIS1N Output Idle state 1 (OC1N output)
0: OC1N=0 after a dead-time when MOE=0
1: OC1N=1 after a dead-time when MOE=0
Note: This bit cannot be modified as long as LOCK level 1, 2 or 3 has been
programmed (LOCK bits in TIMx_BDTR register).
8 OIS1 Output Idle state 1 (OC1 output)
0: OC1=0 (after a dead-time if OC1N is implemented) when MOE=0
1: OC1=1 (after a dead-time if OC1N is implemented) when MOE=0
Note: This bit cannot be modified as long as LOCK level 1, 2 or 3 has been
programmed (LOCK bits in TIMx_BDTR register).
7 TI1S TI1 selection
0: The TIMx_CH1 pin is connected to TI1 input
1: The TIMx_CH1, CH2, CH3 and CH4 pins are connected to the TI1 input
(XOR combination)
6:4 MMS[2:0] Master mode selection
These bits allow to select the information to be sent in master mode to slave
timers for synchronization (TRGO). The combination is as follows:
000: Reset – the UG bit from the TIMx_EGR register is used as trigger
output (TRGO). If the reset is generated by the trigger input (slave mode
controller configured in reset mode) then the signal on TRGO is delayed
compared to the actual reset.
001: Enable – the Counter Enable signal CNT_EN is used as trigger output
(TRGO). It is useful to start several timers at the same time or to control a
window in which a slave timer is enable. The Counter Enable signal is
generated by a logic OR between CEN control bit and the trigger input when
configured in gated mode. When the Counter Enable signal is controlled by
the trigger input, there is a delay on TRGO, except if the master/slave mode
is selected (see the MSM bit description in TIMx_SMCR register).
010: Update – The update event is selected as trigger output (TRGO). For
instance a master timer can then be used as a prescaler for a slave timer.
011: Compare Pulse – The trigger output (TRGO)send a positive pulse when
the CC1IF flag is to be set (even if it was already high), as soon as a capture
or a compare match occurred.
100: Compare – OC1REF signal is used as trigger output (TRGO)
101: Compare – OC2REF signal is used as trigger output (TRGO)
110: Compare – OC3REF signal is used as trigger output (TRGO)
111: Compare – OC4REF signal is used as trigger output (TRGO)
3 CCDS Capture/compare DMA selection

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0: CCx DMA request sent when CCx event occurs


1: CCx DMA requests sent when update event occurs
2 CCUS Capture/compare control update selection
0: When capture/compare control bits are preloaded (CCPC=1), they are
updated by setting the COMG bit only
1: When capture/compare control bits are preloaded (CCPC=1), they are
updated by setting the COMG bit or when an rising edge occurs on TRGI
Note: This bit acts only on channels that have a complementary output
1 NA Reserved, undefined
0 CCPC Capture/compare preloaded control
0: CcxE,CcxNE,CCxP,CCxNP and OcxM bits are not preloaded
1: CcxE,CcxNE,CCxP,CCxNP and OcxM bits are preloaded; they are
updated only when COMG bit set or rising edge detected on TRGI,
depending on the CCUS bit.
Note: This bit acts only on channels that have a complementary output.

16.4.3. TIM1 slave mode control register(TIM1_SMCR)

Address offset: 0x08


Reset value: 0x0000
bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 ETP ECE ETPS[1:0] ETF[3:0]
type RW RW RW RW RW RW RW RW
7:0 MSM TS[2:0] OCCS SMS[2:0]
type RW RW RW RW RW RW RW RW

Bit Name Function


31:16 NA Reserved,undefined
15 ETP External trigger polarity
This bit selects whether ETR or ETR is used for trigger operations
0: ETR is non-inverted, active at high level or rising edge.
1: ETR is inverted, active at low level or falling edge.
14 ECE External clock enable
This bit enables External clock mode 2.
0: External clock mode 2 disabled
1: External clock mode 2 enabled. The counter is clocked by any active edge
on the ETRF signal.
Note1: Setting the ECE bit has the same effect as selecting external clock
mode 1 with TRGI connected to ETRF (SMS=111 and TS=111).
Note2: It is possible to simultaneously use external clock mode 2 with the
following slave modes: reset mode, gated mode and trigger mode.

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Nevertheless, TRGI must not be connected to ETRF in this case (TS bits
must not be 111).
Note3: If external clock mode 1 and external clock mode 2 are enabled at
the same time, the external clock input is ETRF.
13:12 ETPS[1:0] External trigger prescaler
External trigger signal ETRP frequency must be at most 1/4 of TIMxCLK
frequency. A prescaler can be enabled to reduce ETRP frequency. It is
useful when inputting fast external clocks.
00: Prescaler OFF
01: ETRP frequency divided by 2
10: ETRP frequency divided by 4
11: ETRP frequency divided by 8
11:8 ETF[3:0] External trigger filter This bit-field then defines the frequency used to sample
ETRP signal and the length of the digital filter applied to ETRP. The digital
filter is made of an event counter in which N consecutive events are needed
to validate a transition on the output:
0000: No filter, sampling is done at 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐷𝑇𝑆
0001: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐶𝐾_𝐼𝑁𝑇 , N=2
0010: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐶𝐾_𝐼𝑁𝑇 , N=4
0011: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐶𝐾_𝐼𝑁𝑇 , N=8
0100: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐷𝑇𝑆 /2, N=6
0101: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐷𝑇𝑆 /2, N=8
0110: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐷𝑇𝑆 /4, N=6
0111: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐷𝑇𝑆 /4, N=8
1000: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐷𝑇𝑆 /8, N=6
1001: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐷𝑇𝑆 /8, N=8
1010: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐷𝑇𝑆 /16, N=5
1011: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐷𝑇𝑆 /16, N=6
1100: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐷𝑇𝑆 /16, N=8
1101: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐷𝑇𝑆 /32, N=5
1110: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐷𝑇𝑆 /32, N=6
1111: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐷𝑇𝑆 /32, N=8
7 MSM Master/slave mode
0: No action
1: The effect of an event on the trigger input (TRGI) is delayed to allow a
perfect synchronization between the current timer and its slaves (through
TRGO). It is useful if we want to synchronize several timers on a single
external event.
6:4 TS[2:0] Trigger selection This bit-field selects the trigger input to be used to
synchronize the counter.
000: Internal Trigger 0 (ITR0)
001: Reserved
010: Internal Trigger 2 (ITR2)
011: Internal Trigger 3 (ITR3)
100: TI1 Edge Detector (TI1F_ED)
101: Filtered Timer Input 1 (TI1FP1)
110: Filtered Timer Input 2 (TI2FP2)
111: External Trigger input (ETRF)
Note: These bits must be changed only when they are not used (e.g. when

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Fremont Micro Devices FT32F0xxx8 RM

SMS=000) to avoid wrong edge detections at the transition.


3 OCCS OCREF clear selection.
This bit is used to select the OCREF clear source.
0:OCREF_CLR_INT is connected to the OCREF_CLR input
1: OCREF_CLR_INT is connected to ETRF
2:0 SMS[2:0] Slave mode selection
When external signals are selected the active edge of the trigger signal
(TRGI) is linked to the polarity selected on the external input (see Input
Control register and Control Register description.
000: Clock/trigger control disabled
–if CEN = ‘1’ then the prescaler is clocked directly by the internal
clock.
001: Encoder mode 1
–Counter counts up/down on the TI2FP2 edges depending on the TI1FP1
level,
010: Encoder mode 2
–Counter counts up/down on the TI1FP1 edges depending on the TI2FP2
level,
011: Encoder mode 3 – Counter counts up/down on both TI1FP1 and
TI2FP2 edges depending on the level of the other input.
100: Reset Mode – Rising edge of the selected trigger input (TRGI)
reinitializes the counter and generates an update of the registers.
101: Gated Mode – The counter clock is enabled when the trigger input
(TRGI) is high. The counter stops (but is not reset) as soon as the trigger
becomes low. Both start and stop of the counter are controlled.
110: Trigger Mode – The counter starts at a rising edge of the trigger TRGI
(but it is not reset). Only the start of the counter is controlled.
111: External Clock Mode 1 – Rising edges of the selected trigger (TRGI)
clock the counter.
Note: The gated mode must not be used if TI1F_ED is selected as the
trigger input (TS=’100’). Indeed, TI1F_ED outputs 1 pulse for each transition
on TI1F, whereas the gated mode checks the level of the trigger signal.
Table 16-2 TIMx Internal trigger connection
Slave TIM ITR0(TS=000) ITR2(TS=010) ITR3(TS=011)
TIM1 TIM15 TIM3 TIM17

16.4.4. TIM1 DMA/interrupt enable register(TIM1_DIER)

Address offset: 0x0C


Reset value: 0x0000
bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 — TDE COMDE CC4DE CC3DE CC2DE CC1DE UDE

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type RO-0 RW RW RW RW RW RW RW
7:0 BIE TIE COMIE CC4IE CC3IE CC2IE CC1IE UIE
type RW RW RW RW RW RW RW RW

Bit Name Function


31:15 NA Reserved, undefined
14 TDE Trigger DMA request enable
0: Trigger DMA request disabled
1: Trigger DMA request enabled
13 COMDE COM DMA request enable
0: COM DMA request disabled
1: COM DMA request enabled
12 CC4DE Capture/Compare 4 DMA request enable
0: CC4 DMA request disabled
1: CC4 DMA request enabled
11 CC3DE Capture/Compare 3 DMA request enable
0: CC3 DMA request disabled
1: CC3 DMA request enabled
10 CC2DE Capture/Compare 2 DMA request enable
0: CC2 DMA request disabled
1: CC2 DMA request enabled
9 CC1DE Capture/Compare 1 DMA request enable
0: CC1 DMA request disabled
1: CC1 DMA request enabled
8 UDE Update DMA request enable
0: Update DMA request disabled
1: Update DMA request enabled
7 BIE Break interrupt enable
0: Break interrupt disabled
1: Break interrupt enabled
6 TIE Trigger interrupt enable
0: Trigger interrupt disabled
1: Trigger interrupt enabled
5 COMIE COM interrupt enable
0: COM interrupt disabled
1: COM interrupt enabled
4 CC4IE Capture/Compare 4 interrupt enable
0: CC4 interrupt disabled
1: CC4 interrupt enabled
3 CC3IE Capture/Compare 3 interrupt enable
0: CC3 interrupt disabled
1: CC3 interrupt enabled

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2 CC2IE Capture/Compare 2 interrupt enable


0: CC2 interrupt disabled
1: CC2 interrupt enabled
1 CC1IE Capture/Compare 1 interrupt enable
0: CC1 interrupt disabled
1: CC1 interrupt enabled
0 UIE Update interrupt enable
0: Update interrupt disabled
1: Update interrupt enabled

16.4.5. TIM1 status register(TIM1_SR)

Address offset: 0x10


Reset value: 0x0000
bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 — CC4OF CC3OF CC2OF CC1OF —
type RO-0 RO-0 RO-0 RC_W0 RC_W0 RC_W0 RC_W0 RO-0
7:0 BIF TIF COMIF CC4IF CC3IF CC2IF CC1IF UIF
type RC_W0 RC_W0 RC_W0 RC_W0 RC_W0 RC_W0 RC_W0 RC_W0

Bit Name Function


31:13 NA Reserved, undefined
12 CC4OF Capture/Compare 4 overcapture flag refer to CC1OF description
11 CC3OF Capture/Compare 3 overcapture flag refer to CC1OF description
10 CC2OF Capture/Compare 2 overcapture flag refer to CC1OF description
9 CC1OF Capture/Compare 1 overcapture flag This flag is set by hardware only
when the corresponding channel is configured in input capture mode. It is
cleared by software by writing it to ‘0’.
0: No overcapture has been detected.
1: The counter value has been captured in TIMx_CCR1 register while
CC1IF flag was already set
8 NA Reserved, undefined
7 BIF Break interrupt flag This flag is set by hardware as soon as the break input
goes active. It can be cleared by software if the break input is not active.
0: No break event occurred.
1: An active level has been detected on the break input.
6 TIF Trigger interrupt flag This flag is set by hardware on trigger event (active
edge detected on TRGI input when the slave mode controller is enabled in
all modes but gated mode.It is cleared by software.

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0: No trigger event occurred.


1: Trigger interrupt pending.
5 COMIF COM interrupt flag This flag is set by hardware on COM event (when
Capture/compare Control bits – CcxE, CcxNE, OcxM – have been updated).
It is cleared by software.
0: No COM event occurred.
1: COM interrupt pending.
4 CC4IF Capture/Compare 4 interrupt flag refer to CC1IF description
3 CC3IF Capture/Compare 3 interrupt flag refer to CC1IF description
2 CC2IF Capture/Compare 2 interrupt flag refer to CC1IF description
1 CC1IF Capture/Compare 1 interrupt flag
If channel CC1 is configured as output:
This flag is set by hardware when the counter matches the compare value,
with some exception in center-aligned mode (refer to the CMS bits in the
TIMx_CR1 register description). It is cleared by software.
0: No match.
1: The content of the counter TIMx_CNT matches the content of the
TIMx_CCR1 register.
When the contents of TIMx_CCR1 are greater than the contents of
TIMx_ARR, the CC1IF bit goes high on the counter overflow (in upcounting
and up/down-counting modes) or underflow (in downcounting mode)
If channel CC1 is configured as input:
This bit is set by hardware on a capture. It is cleared by software or by
reading the TIMx_CCR1 register.
0: No input capture occurred
1: The counter value has been captured in TIMx_CCR1 register (An edge
has been detected on IC1 which matches the selected polarity)
0 UIF Update interrupt flag
This bit is set by hardware on an update event. It is cleared by software.
0: No update occurred.
1: Update interrupt pending. This bit is set by hardware when the registers
are updated:
–At overflow or underflow regarding the repetition counter value (update if
repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register.
–When CNT is reinitialized by software using the UG bit in TIMx_EGR
register, if URS=0 and UDIS=0 in the TIMx_CR1 register.
–When CNT is reinitialized by a trigger event (refer to Section 16.4.3: TIM1
slave mode control register (TIM1_SMCR)), if URS=0 and UDIS=0 in the
TIMx_CR1 register.

16.4.6. TIM1 event generation register(TIM1_EGR)

Address offset: 0x14


Reset value: 0x0000
bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0

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23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
7:0 BG TG COMG CC4G CC3G CC2G CC1G UG
type W W W W W W W W

Bit Name Function


31:8 NA Reserved, undefined
7 BG Break generation
This bit is set by software in order to generate an event, it is automatically
cleared by hardware.
0: No action
1: A break event is generated. MOE bit is cleared and BIF flag is set. Related
interrupt or DMA transfer can occur if enabled.
6 TG Trigger generation
This bit is set by software in order to generate an event, it is automatically
cleared by hardware.
0: No action
1: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer
can occur if enabled.
5 COMG Capture/Compare control update generation This bit can be set by software,
it is automatically cleared by hardware
0: No action
1: When CCPC bit is set, it allows to update CcxE、CcxNE、CCxP、CCxNP、
OCIM bits
Note: This bit acts only on channels having a complementary output
4 CC4G Capture/Compare 4 generation Refer to CC1G description
3 CC3G Capture/Compare 3 generation Refer to CC1G description
2 CC2G Capture/Compare 2 generation Refer to CC1G description
1 CC1G Capture/Compare 1 generation
This bit is set by software in order to generate an event, it is automatically
cleared by hardware.
0: No action
1: A capture/compare event is generated on CC1
If channel CC1 is configured as output:
CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled.
If channel CC1 is configured as input:
The current value of the counter is captured in TIMx_CCR1 register. The
CC1IF flag is set, the corresponding interrupt or DMA request is sent if
enabled. The CC1OF flag is set if the CC1IF flag was already high.
0 UG Update generation
This bit can be set by software, it is automatically cleared by hardware.
0: No action
1: Reinitialize the counter and generates an update of the registers. Note
that the prescaler counter is cleared too (anyway the prescaler ratio is not
affected). The counter is cleared if the center-aligned mode is selected or if

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DIR=0 (upcounting), else it takes the auto-reload value (TIMx_ARR) if


DIR=1 (downcounting).

16.4.7. TIM1 capture/compare mode register 1(TIM1_CCMR1)

Address offset: 0x18


Reset value: 0x0000
The channels can be used in input (capture mode) or in output (compare mode). The direction of a channel
is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different
function in input and in output mode. For a given bit, Ocxx describes its function when the channel is
configured in output, Icxx describes its function when the channel is configured in input. So you must take
care that the same bit can have a different meaning for the input stage and for the output stage.
Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
OC2CE OC2M[2:0] OC2PE OC2FE
15:8 CC2S[1:0]
IC2F[3:0] IC2PSC[1:0]
type RW RW RW RW RW RW RW RW
OC1CE OC1M[2:0] OC1PE OC1FE
7:0 CC1S[1:0]
IC1F[3:0] IC1PSC[1:0]
type RW RW RW RW RW RW RW RW

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Output compare mode


Bit Name Function
31:16 NA Reserved, undefined
15 OC2CE Output Compare 2 clear enable
14:12 OC2M[2:0] Output Compare 2 mode
11 OC2PE Output Compare 2 preload enable
10 OC2FE Output Compare 2 fast enable
9:8 CC2S Capture/Compare 2 selection
This bit-field defines the direction of the channel (input/output) as well as the
used input. 00: CC2 channel is configured as output
01: CC2 channel is configured as input, IC2 is mapped on TI2
10: CC2 channel is configured as input, IC2 is mapped on TI1
11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode
is working only if an internal trigger input is selected through the TS bit
(TIMx_SMCR register)
Note: CC2S bits are writable only when the channel is OFF
(CC2E=0,CC2NE=0 and updated in TIMx_CCER).
7 OC1CE Output Compare 1 clear enable
OC1CE: Output Compare 1 Clear Enable
0: OC1REF is not affected by the ETRF Input
1: OC1REFis cleared as soon as a High level is detected on ETRF input
6:4 OC1M[2:0] Output Compare 1 mode
These bits define the behavior of the output reference signal OC1REF from
which OC1 and OC1N are derived. OC1REF is active high whereas OC1
and OC1N active level depends on CC1P and CC1NP bits.
000: Frozen – The comparison between the output compare register
TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs (this
mode is used to generate a timing base).
001: Set channel 1 to active level on match. OC1REF signal is forced high
when the counter TIMx_CNT matches the capture/compare register 1
(TIMx_CCR1).
010: Set channel 1 to inactive level on match. OC1REF signal is forced low
when the counter TIMx_CNT matches the capture/compare register 1
(TIMx_CCR1).
011: Toggle – OC1REF toggles when TIMx_CNT=TIMx_CCR1.
100: Force inactive level – OC1REF is forced low.
101: Force active level – OC1REF is forced high.
110: PWM mode 1 – In upcounting, channel 1 is active as long as
TIMx_CNT<TIMx_CCR1 else inactive. In downcounting, channel 1 is
inactive (OC1REF=‘0’) as long as TIMx_CNT>TIMx_CCR1 else active
(OC1REF=’1’).
111: PWM mode 2 – In upcounting, channel 1 is inactive as long as
TIMx_CNT<TIMx_CCR1 else active. In downcounting, channel 1 is active as
long as TIMx_CNT>TIMx_CCR1 else inactive.
Note1: These bits can not be modified as long as LOCK level 3 has been
programmed (LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the
channel is configured in output).
Note2: In PWM mode 1 or 2, the OCREF level changes only when the result

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of the comparison changes or when the output compare mode switches from
“frozen” mode to “PWM” mode.
Note3: On channels having a complementary output, this bit field is
preloaded. If the CCPC bit is set in the TIMx_CR2 register then the OC1M
active bits take the new value from the preloaded bits only when a COM
event is generated.
3 OC1PE Output Compare 1 preload enable
0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at
anytime, the new value is taken in account immediately.
1: Preload register on TIMx_CCR1 enabled. Read/Write operations access
the preload register. TIMx_CCR1 preload value is loaded in the active
register at each update event.
Note1: These bits can not be modified as long as LOCK level 3 has been
programmed (LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the
channel is configured in output).
Note2: The PWM mode can be used without validating the preload register
only in one pulse mode (OPM bit set in TIMx_CR1 register). Else the
behavior is not guaranteed.
2 OC1FE Output Compare 1 fast enable
This bit is used to accelerate the effect of an event on the trigger in input on
the CC output.
0: CC1 behaves normally depending on counter and CCR1 values even
when the trigger is ON. The minimum delay to activate CC1 output when an
edge occurs on the trigger input is 5 clock cycles.
1: An active edge on the trigger input acts like a compare match on CC1
output. Then, OC is set to the compare level independently from the result of
the comparison. Delay to sample the trigger input and to activate CC1 output
is reduced to 3 clock cycles.
Note:OCFE acts only if the channel is configured in PWM1 or PWM2 mode.
1:0 CC1S[1:0] Capture/Compare 1 selection
This bit-field defines the direction of the channel (input/output) as well as the
used input.
00: CC1 channel is configured as output
01: CC1 channel is configured as input, IC1 is mapped on TI1
10: CC1 channel is configured as input, IC1 is mapped on TI2
11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode
is working only if an internal trigger input is selected through TS bit
(TIMx_SMCR register)
Note: CC1S bits are writable only when the channel is OFF (CC1E = ‘0’ in
TIMx_CCER).

Input capture mode


Bit Name Function
31:16 NA Reserved, undefined
15:12 IC2F[3:0] Input capture 2 filter
11:10 IC2PSC[1:0] Input capture 2 prescaler
9:8 CC2S[1:0] Capture/Compare 2 selection
This bit-field defines the direction of the channel (input/output) as well as the

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used input.
00: CC2 channel is configured as output
01: CC2 channel is configured as input, IC2 is mapped on TI2
10: CC2 channel is configured as input, IC2 is mapped on TI1
11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode
is working only if an internal trigger input is selected through TS bit
(TIMx_SMCR register)
Note: CC2S bits are writable only when the channel is OFF (CC2E = 0,
CC2NE=0 and updated in TIMx_CCER).
7:4 IC1F[3:0] Input capture 1 filter
This bit-field defines the frequency used to sample TI1 input and the length
of the digital filter applied to TI1. The digital filter is made of an event counter
in which N consecutive events are needed to validate a transition on the
output:
0000:No filter, sampling is done at 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐶𝐾_𝐼𝑁𝑇
0001: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐶𝐾_𝐼𝑁𝑇 , N=2
0010: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐶𝐾_𝐼𝑁𝑇 , N=4
0011: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐶𝐾_𝐼𝑁𝑇 , N=8
0100: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐷𝑇𝑆 /2, N=6
0101: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐷𝑇𝑆 /2, N=8
0110: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐷𝑇𝑆 /4, N=6
0111: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐷𝑇𝑆 /4, N=8
1000: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐷𝑇𝑆 /8, N=6
1001: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐷𝑇𝑆 /8, N=8
1010: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐷𝑇𝑆 /16, N=5
1011: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐷𝑇𝑆 /16, N=6
1100: 𝑓𝑆𝐴𝑀𝑃𝐿I𝑁𝐺 = 𝑓𝐷𝑇𝑆 /16, N=8
1101: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐷𝑇𝑆 /32, N=5
1110: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐷𝑇𝑆 /32, N=6
1111: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐷𝑇𝑆 /32, N=8
3:2 IC1PSC[1:0] Input capture 1 prescaler
This bit-field defines the ratio of the prescaler acting on CC1 input (IC1).
The prescaler is reset as soon as CC1E=’0’ (TIMx_CCER register).
00: no prescaler, capture is done each time an edge is detected on the
capture input
01: capture is done once every 2 events
10: capture is done once every 4 events
11: capture is done once every 8 events
1:0 CC1S[1:0] Capture/Compare 1
Selection This bit-field defines the direction of the channel (input/output) as
well as the used input.
00: CC1 channel is configured as output
01: CC1 channel is configured as input, IC1 is mapped on TI1
10: CC1 channel is configured as input, IC1 is mapped on TI2
11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode
is working only if an internal trigger input is selected through TS bit
(TIMx_SMCR register) Note: CC1S bits are writable only when the channel
is OFF (CC1E = ‘0’ in TIMx_CCER).

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16.4.8. TIM1 capture/compare mode register 2(TIM1_CCMR2)

Address offset: 0x1C


Reset value: 0x0000
Refer to the above CCMR1 register description.
Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
OC4CE OC4M[2:0] OC4PE OC4FE
15:8 CC4S[1:0]
IC4F[3:0] IC4PSC[1:0]
type RW RW RW RW RW RW RW RW
OC3CE OC3M[2:0] OC3PE OC3FE
7:0 CC3S[1:0]
IC3F[3:0] IC3PSC[1:0]
type RW RW RW RW RW RW RW RW

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Output compare mode


Bit Name Function
31:16 NA Reserved, undefined
15 OC4CE Output compare 4 clear enable
14:12 OC4M[2:0] Output compare 4 mode
11 OC4PE Output compare 4 preload enable
10 OC4FE Output compare 4 fast enable
9:8 CC4S Capture/Compare 4 selection
This bit-field defines the direction of the channel (input/output) as well as the
used input. 00: CC4 channel is configured as output
01: CC4 channel is configured as input, IC4 is mapped on TI4
10: CC4 channel is configured as input, IC4 is mapped on TI3
11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode
is working only if an internal trigger input is selected through TS bit
(TIMx_SMCR register)
Note: CC4S bits are writable only when the channel is OFF (CC4E = ‘0’ in
TIMx_CCER).
7 OC3CE Output compare 3 clear enable
6:4 OC3M[2:0] Output compare 3 mode
3 OC3PE Output compare 3 preload enable
2 OC3FE Output compare 3 fast enable
1:0 CC3S Capture/Compare 3 selection This bit-field defines the direction of the
channel (input/output) as well as the used input.
00: CC3 channel is configured as output
01: CC3 channel is configured as input, IC3 is mapped on TI3
10: CC3 channel is configured as input, IC3 is mapped on TI4
11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode
is working only if an internal trigger input is selected through TS bit
(TIMx_SMCR register)
Note: CC3S bits are writable only when the channel is OFF (CC3E=0,
CC3NE=0 in TIMx_CCER and update already)

Input capture mode


Bit Name Function
31:16 NA Reserved, undefined
15:12 IC4F[3:0] Input capture 4 filter
11:10 IC4PSC[1:0] Input capture 4 prescaler
9:8 CC4S[1:0] Capture/Compare 4 selection
This bit-field defines the direction of the channel (input/output) as well as the
used input.
00: CC4 channel is configured as output
01: CC4 channel is configured as input, IC4 is mapped on TI4
10: CC4 channel is configured as input, IC4 is mapped on TI3
11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode
is working only if an internal trigger input is selected through TS bit
(TIMx_SMCR register)

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Note: CC4S bits are writable only when the channel is OFF (CC4E=0 in
TIMx_CCER and update already
7:4 IC3F[3:0] Input capture 3 filter
3:2 IC3PSC[1:0] Input capture 3 prescaler
1:0 CC3S[1:0] Capture/compare 3 selection
This bit-field defines the direction of the channel (input/output) as well as the
used input.
00: CC3 channel is configured as output
01: CC3 channel is configured as input, IC3 is mapped on TI3
10: CC3 channel is configured as input, IC3 is mapped on TI4
11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode
is working only if an internal trigger input is selected through TS bit
(TIMx_SMCR register)
Note: CC3S bits are writable only when the channel is OFF (CC3E=0,
CC3NE=0 in TIMx_CCER and update already)

16.4.9. TIM1 capture/compare enable register(TIM1_CCER)

Address offset: 0x20


Reset value: 0x0000
bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 — CC4P CC4E CC3NP CC3NE CC3P CC3E
type RO-0 RO-0 RW RW RW RW RW RW
7:0 CC2NP CC2NE CC2P CC2E CC1NP CC1NE CC1P CC1E
type RW RW RW RW RW RW RW RW

Bit Name Function


31:14 NA Reserved, undefined
13 CC4P Capture/Compare 4 output polarity refer to CC1P description
12 CC4E Capture/Compare 4 output enable refer to CC1E description
11 CC3NP Capture/Compare 3 complementary output polarity refer to CC1NP
description
10 CC3NE Capture/Compare 3 complementary output enable refer to CC1NE
description
9 CC3P Capture/Compare 3 output polarity refer to CC1P description
8 CC3E Capture/Compare 3 output enable refer to CC1E description
7 CC2NP Capture/Compare 2 complementary output polarity refer to CC1NP
description
6 CC2NE Capture/Compare 2 complementary output enable refer to CC1NE
description

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5 CC2P Capture/Compare 2 output polarity refer to CC1P description


4 CC2E Capture/Compare 2 output enable refer to CC1E description
3 CC1NP Capture/Compare 1 complementary output polarity
CC1 channel configuration as output:
0: OC1N active high.
1: OC1N active low.
CC1 channel configuration as input:
This bit is used in conjunction with CC1P to define the polarity of TI1FP1 and
TI2FP1. Refer to CC1P description
Note1: This bit is not writable as soon as LOCK level 2 or 3 has been
programmed (LOCK bits in TIMx_BDTR register) and CC1S=”00” (the
channel is configured in output).
Note2: On channels having a complementary output, this bit is preloaded. If
the CCPC bit is set in the TIMx_CR2 register then the CC1NP active bit
takes the new value from the preloaded bits only when a Commutation event
is generated.
2 CC1NE Capture/Compare 1 complementary output enable
0: Off – OC1N is not active. OC1N level is then function of MOE, OSSI,
OSSR, OIS1, OIS1N and CC1E bits.
1: On – OC1N signal is output on the corresponding output pin depending on
MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits.
Note: On channels having a complementary output, this bit is preloaded. If
the CCPC bit is set in the TIMx_CR2 register then the CC1NE active bit
takes the new value from the preloaded bits only when a Commutation event
is generated.
1 CC1P Capture/Compare 1 output polarity
CC1 channel configured as output:
0: OC1 active high
1: OC1 active low
CC1 channel configured as input:
CC1NP/CC1P bits select the active polarity of TI1FP1 and TI2FP1 for trigger
or capture operations.
00: non-inverted/rising edge
The circuit is sensitive to TixFP1 rising edge (capture or trigger operations in
reset, external clock or trigger mode), TixFP1 is not inverted ( in gated mode
or encoder mode).
01: inverted/falling edge
The circuit is sensitive to TixFP1 falling edge (capture or trigger operations in
reset, external clock or trigger mode), TixFP1 is inverted ( in gated mode or
encoder mode).
10: reserved, do not use this configuration.
11: non-inverted/both edges
The circuit is sensitive to both TixFP1 rising and falling edges (capture or
trigger operations in reset, external clock or trigger mode), TixFP1 is not
inverted ( in gated mode or encoder mode).
Note1: This bit is not writable as soon as LOCK level 2 or 3 has been
programmed (LOCK bits in TIMx_BDTR register).
Note2: On channels having a complementary output, this bit is preloaded. If
the CCPC bit is set in the TIMx_CR2 register then the CC1P active bit takes

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the new value from the preloaded bits only when a Commutation event is
generated.
0 CC1E Capture/Compare 1 output enable
CC1 channel configured as output:
0: Off
－ OC1 is not active. OC1 level is then function of MOE, OSSI, OSSR,
OIS1, OIS1N and CC1NE bits.
1: On
－ OC1 signal is output on the corresponding output pin depending on
MOE, OSSI, OSSR, OIS1, OIS1N and CC1NE bits.
CC1 channel configured as input:
This bit determines if a capture of the counter value can actually be done
into the input capture/compare register 1 (TIMx_CCR1) or not.
0: Capture disabled.
1: Capture enabled.
Note: On channels having a complementary output, this bit is preloaded. If
the CCPC bit is set in the TIMx_CR2 register then the CC1E active bit takes
the new value from the preloaded bits only when a Commutation event is
generated.

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Table 16-3 Output control bits for complementary Ocx and OcxN channels with break feature
Control bits Output states(1)
MOE OSSI OSSR CcxE CcxNE Ocx output state OcxN output state
Output Disabled (not driven by Output Disabled (not driven by
0 0 0 the timer) the timer)
Ocx=0, Ocx_EN=0 OcxN=0, OcxN_EN=0
Output Disabled (not driven by OCxREF + Polarity
0 0 1 the timer) OcxN=OCxREF
Ocx=0, Ocx_EN=0 xor CCxNP, OcxN_EN=1
OCxREF +Polarity Output Disabled (not driven by
0 1 0 Ocx=OCxREF ^ CCxP the timer)
Ocx_EN=1 OcxN=0, OcxN_EN=0
Complementary to OCxREF +
OCREF + Polarity +dead-time
0 1 1 Polarity +dead-time
Ocx_EN=1
OcxN_EN=1
1 X
Output Disabled (not driven by Output Disabled (not driven by
1 0 0 the timer) the timer)
Ocx=CCxP, Ocx_EN=0 OcxN=CCxNP, OcxN_EN=0
Off-State (output enabled with OCxREF + Polarity
1 0 1 inactive state) OcxN=OCxREF xor CCxNP,
Ocx=CCxP, Ocx_EN=1 OcxN_EN=1
OCxREF + Polarity Off-State (output enabled with
1 1 0 Ocx=OCxREF ^ T1CCxNP inactive state)
Ocx_EN=1 OcxN=T1CCxNP, Ocx_EN=1
Complementary to OCxREF +
OCxREF + Polarity + dead-time
1 1 1 Polarity + dead-time
Ocx_EN=1
OcxN_EN=1
Output Disabled (not driven by Output Disabled (not driven by
0 0 0 the timer) the timer)
Ocx=CCxP, Ocx_EN=0 OcxN=CCxNP, OcxN_EN=0
0 0 1 Output Disabled (not driven by the timer)
0 1 0 Asynchronously: Ocx=CCxP, Ocx_EN=0, OcxN=CCxNP,
OcxN_EN=0
Then if the clock is present: Ocx=OISx and OcxN=OISxN after a
0 1 1
dead-time, assuming that OISx and OISxN do not correspond to
0 X
Ocx and OcxN both in active state.
Output Disabled (not driven by Output Disabled (not driven by
1 0 0 the timer) the timer)
Ocx=CCxP, Ocx_EN=0 OcxN=CCxNP, OcxN_EN=0
1 0 1 Off-State (output enabled with inactive state)
1 1 0 Asynchronously: Ocx=CCxP, Ocx_EN=1, OcxN=CCxNP,
OcxN_EN=1
1 1 1
Then if the clock is present: Ocx=OISx and OcxN=OISxN after a

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dead-time, assuming that OISx and OISxN do not correspond to


OCX and OcxN both in active state.
（1） When both outputs of a channel are not used (CcxE = CcxNE = 0), the OISx, OISxN, CCxP and
CCxNP bits must be kept cleared.
Note:The state of the external I/O pins connected to the complementary Ocx and OcxN channels depends
on the Ocx and OcxN channel state and the GPIO registers.

16.4.10. TIM1 counter(TIM1_CNT)

Address offset: 0x24


Reset value: 0x0000
bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 CNT[15:8]
type RW RW RW RW RW RW RW RW
7:0 CNT[7:0]
type RW RW RW RW RW RW RW RW

Bit Name Function


31:16 NA Reserved, undefined
15:0 CNT[15:0] Counter value

16.4.11. TIM1 prescaler(TIM1_PSC)

Address offset: 0x28


Reset value: 0x0000
bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 PSC[15:8]
type RW RW RW RW RW RW RW RW
7:0 PSC[7:0]
type RW RW RW RW RW RW RW RW

Bit Name Function


31:16 NA Reserved, undefined

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15:0 PSC[15:0] Prescaler value


The counter clock frequency (CK_CNT) is equal to 𝑓𝐶𝐾_𝑃𝑆𝐶 /(PSC[15:0]+1).
PSC contains the value to be loaded in the active prescaler register at each
update event

16.4.12. TIM1 auto-reload register(TIM1_ARR)

Address offset: 0x2C


Reset value: 0xFFFF
bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 ARR[15:8]
type RW RW RW RW RW RW RW RW
7:0 ARR[7:0]
type RW RW RW RW RW RW RW RW

Bit Name Function


31:16 NA Reserved, undefined
15:0 ARR[15:0] Auto-reload value
ARR is the value to be loaded in the actual auto-reload register.
Refer to the Section 16.3.1: Time-base unit for more details about ARR
update and behavior.
The counter is blocked while the auto-reload value is null.

16.4.13. TIM1 repetition counter register(TIM1_RCR)

Address offset: 0x30


Reset value: 0x0000
bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
7:0 REP[7:0]
type RW RW RW RW RW RW RW RW

Bit Name Function

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31:8 NA Reserved, undefined


7:0 REP[7:0] Repetition counter value
These bits allow the user to set-up the update rate of the compare registers
(i.e. periodic transfers from preload to active registers) when preload
registers are enable, as well as the update interrupt generation rate, if this
interrupt is enable.
Each time the REP_CNT related downcounter reaches zero, an update
event is generated and it restarts counting from REP value. As REP_CNT is
reloaded with REP value only at the repetition update event U_RC, any write
to the TIMx_RCR register is not taken in account until the next repetition
update event.
It means in PWM mode (REP+1) corresponds to:
– the number of PWM periods in edge-aligned mode
– the number of half PWM period in center-aligned mode.

16.4.14. TIM1 capture/compare register 1(TIM1_CCR1)

Address offset: 0x34


Reset value: 0x0000
bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 CCR1[15:8]
type RW RW RW RW RW RW RW RW
7:0 CCR1[7:0]
type RW RW RW RW RW RW RW RW

Bit Name Function


31:16 NA Reserved, undefined
15:0 CCR1[15:0] Capture/Compare 1 value
If channel CC1 is configured as output:
CCR1 is the value to be loaded in the actual capture/compare 1 register
(preload value). It is loaded permanently if the preload feature is not selected
in the TIMx_CCMR1 register (bit OC1PE). Else the preload value is copied
in the active capture/compare 1 register when an update event occurs.
The active capture/compare register contains the value to be compared to
the counter TIMx_CNT and signaled on OC1 output.

If channel CC1 is configured as input:


CCR1 is the counter value transferred by the last input capture 1 event (IC1).

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16.4.15. TIM1 capture/compare register 2(TIM1_CCR2)

Address offset: 0x38


Reset value: 0x0000
bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 CCR2[15:8]
type RW RW RW RW RW RW RW RW
7:0 CCR2[7:0]
type RW RW RW RW RW RW RW RW

Bit Name Function


31:16 NA Reserved, undefined
15:0 CCR2[15:0] Capture/Compare 2 value
If channel CC2 is configured as output:
CCR2 is the value to be loaded in the actual capture/compare 2 register
(preload value).It is loaded permanently if the preload feature is not selected
in the TIMx_CCMR2 register (bit OC2PE). Else the preload value is copied
in the active capture/compare 2 register when an update event occurs.
The active capture/compare register contains the value to be compared to
the counter TIMx_CNT and 277ffectiv on OC2 output.
If channel CC2 is configured as input:
CCR2 is the counter value transferred by the last input capture 2 event (IC2).

16.4.16. TIM1 capture/compare register 3(TIM1_CCR3)

Address offset: 0x3C


Reset value: 0x0000
bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 CCR3[15:8]
type RW RW RW RW RW RW RW RW
7:0 CCR3[7:0]
type RW RW RW RW RW RW RW RW

Bit Name Function

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31:16 NA Reserved, undefined


15:0 CCR3[15:0] Capture/Compare value
If channel CC3 is configured as output:
CCR3 is the value to be loaded in the actual capture/compare 3 register
(preload value). It is loaded permanently if the preload feature is not selected
in the TIMx_CCMR3 register (bit OC3PE). Else the preload value is copied
in the active capture/compare 3 register when an update event occurs.
The active capture/compare register contains the value to be compared to
the counter TIMx_CNT and 278ffectiv on OC3 output.

If channel CC3 is configured as input:


CCR3 is the counter value transferred by the last input capture 3 event (IC3).

16.4.17. TIM1 capture/compare register 4(TIM1_CCR4)

Address offset: 0x40


Reset value: 0x0000
bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 CCR4[15:8]
type RW RW RW RW RW RW RW RW
7:0 CCR4[7:0]
type RW RW RW RW RW RW RW RW

Bit Name Function


31:16 NA Reserved, undefined
15:0 CCR4[15:0] Capture/Compare value
If channel CC4 is configured as output:
CCR4 is the value to be loaded in the actual capture/compare 4 register
(preload value). It is loaded permanently if the preload feature is not selected
in the TIMx_CCMR4 register (bit OC4PE). Else the preload value is copied
in the active capture/compare 4 register when an update event occurs.
The active capture/compare register contains the value to be compared to
the counter TIMx_CNT and 278ffectiv on OC4 output.
If channel CC4 is configured as input:
CCR4 is the counter value transferred by the last input capture 4 event (IC4).

16.4.18. TIM1 break and dead-time register(TIM1_BDTR)

Address offset: 0x44


Reset value: 0x0000

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bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0


31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 MOE AOE BKP BKE OSSR OSSI LOCK[1:0]
type RW RW RW RW RW RW RW RW
7:0 DTG[7:0]
type RW RW RW RW RW RW RW RW

Bit Name Function


31:16 NA Reserved, undefined
15 MOE Main output enable
This bit is cleared asynchronously by hardware as soon as the break input is
active. It is set by software or automatically depending on the AOE bit. It is
acting only on the channels which are configured in output.
0: Ocx and OcxN outputs are disabled or forced to idle state.
1: Ocx and OcxN outputs are enabled if their respective enable bits are set
(CcxE, CcxNE in TIMx_CCER register).
14 AOE Automatic output enable
0: MOE can be set only by software
1: MOE can be set by software or automatically at the next update event (if
the break input is not be active)
Note: This bit cannot be modified as long as LOCK level 1 has been
programmed (LOCK bits in TIMx_BDTR register).
13 BKP Break polarity
0: Break input BRK is active low
1: Break input BRK is active high
Note: This bit can not be modified as long as LOCK level 1 has been
programmed (LOCK bits in TIMx_BDTR register).
Note: Any write operation to this bit takes a delay of 1 APB clock cycle to
become effective
12 BKE Break enable
0: Break disabled(BRK and internal break source)
1: Break enabled(BRK and internal break source)
Note: This bit cannot be modified when LOCK level 1 has been programmed
(LOCK bits in TIMx_BDTR register).
Note: Any write operation to this bit takes a delay of 1 APB clock cycle to
become effective.
11 OSSR Off-state selection for Run mode
This bit is used when MOE=1 on channels having a complementary output which are
configured as outputs.
0: When inactive, Ocx/OcxN outputs are disabled (Ocx/OcxN enable output
signal=0).
1: When inactive, Ocx/OcxN outputs are enabled with their inactive level as

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soon as CcxE=1 or CcxNE=1. Then, OC/OCN enable output signal=1


Note: This bit can not be modified as soon as the LOCK level 2 has been
programmed (LOCK bits in TIMx_BDTR register).
10 OSSI Off-state selection for Idle mode
This bit is used when MOE=0 on channels configured as outputs.
0: When inactive, OC/OCN outputs are disabled (OC/OCN enable output
signal=0).
1: When inactive, OC/OCN outputs are forced first with their idle level as
soon as CcxE=1 or CcxNE=1. OC/OCN enable output signal=1)
Note: This bit can not be modified as soon as the LOCK level 2 has been
programmed (LOCK bits in TIMx_BDTR register).
9:8 LOCK Lock configuration
These bits offer a write protection against software errors.
00: LOCK OFF – No bit is write protected.
01: LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits
in TIMx_CR2 register and BKE/BKP/AOE bits in TIMx_BDTR register can no
longer be written.
10: LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in
TIMx_CCER register, as long as the related channel is configured in output
through the CCxS bits) as well as OSSR and OSSI bits can no longer be
written.
11: LOCK Level 3 = LOCK Level 2 + CC Control bits (OcxM and OcxPE bits
in TIMx_CCMRx registers, as long as the related channel is configured in
output through the CCxS bits) can no longer be written.
Note: The LOCK bits can be written only once after the reset. Once the
TIMx_BDTR register has been written, their content is frozen until the
next reset.
7:0 DTG[7:0] Dead-time generator setup
This bit-field defines the duration of the dead-time inserted between the
complementary outputs. DT correspond to this duration.
DTG[7:5]=0xx => DT=DTG[7:0]* tdtg,with tdtg=tDTS
DTG[7:5]=10x => DT=(64+DTG[5:0]) * tdtg,with tdtg= 2*tDTS
DTG[7:5]=110 => DT=(32+DTG[4:0]) * tdtg,with tdtg=8* tDTS
DTG[7:5]=111 => DT=(32+DTG[4:0]) * tdtg,with tdtg= 16*tDTS
Example if tDTS =125 ns (8 MHz),dead-time possible values are:
DTG[7:0] = 0~7Fh,0 to 15875 ns by 125 ns steps,
DTG[7:0] = 80h~BFh,16 us to 31750 ns by 250 ns steps,
DTG[7:0] = C0h~DFh,32 us to 63 us by 1 us steps,
DTG[7:0] = E0h~FFh,64 us to 126 us by 2 us steps
Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has
been programmed (LOCK bits in TIMx_BDTR register).

16.4.19. TIM1 DMA control register(TIM1_DCR)

Address offset: 0x48


Reset value: 0x0000

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bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0


31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 — DBL[4:0]
type RO-0 RO-0 RO-0 RW RW RW RW RW
7:0 — DBA[4:0]
type RO-0 RO-0 RO-0 RW RW RW RW RW

Bit Name Function


31:13 NA Reserved, undefined
12:8 DBL[4:0] DMA burst length
This 5-bit vector defines the number of DMA transfers (the timer recognizes
a burst transfer when a read or a write access is done to the TIMx_DMAR
address)
00000: 1 transfer
00001: 2 transfers
00010: 3 transfers
...
10001: 18 transfers
7:5 NA Reserved, undefined
4:0 DBA[4:0] DMA base address
This 5-bit vector defines the base-address for DMA transfers (when
read/write access are done through the TIMx_DMAR address). DBA is
defined as an offset starting from the address of the TIMx_CR1 register.
Example:
00000: TIMx_CR1,
00001: TIMx_CR2,
00010: TIMx_SMCR,
...
Example: Let us consider the following transfer: DBL = 7 transfers and DBA
= TIMx_CR1. In this case the transfer is done to/from 7 registers starting
from the TIMx_CR1 address.

16.4.20. TIM1 DMA address for full transfer(TIM1_DMAR)

Address offset: 0x4C


Reset value: 0x0000
bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0

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15:8 DMAB[15:8]
type RW RW RW RW RW RW RW RW
7:0 DMAB[7:0]
type RW RW RW RW RW RW RW RW

Bit Name Function


31:16 NA Reserved, undefined
15:0 DMAB[15:0] DMA register for burst accesses
A read or write operation to the DMAR register accesses the register located
at the address (TIMx_CR1 address) + (DBA + DMA index) x 4
where TIMx_CR1 address is the address of the control register 1, DBA is the
DMA base address configured in TIMx_DCR register; DMA index is
automatically controlled by the DMA transfer, and ranges from 0 to DBL (DBL
configured in TIMx_DCR).

Example of how to use the DMA burst feature


In this example the timer DMA burst feature is used to update the contents of the CCRx registers (x = 2, 3, 4)
with the DMA transferring half words into the CCRx registers.
This is done in the following steps:
1. Configure the corresponding DMA channel as follows:
− DMA channel peripheral address is the DMAR register address
− DMA channel memory address is the address of the buffer in the RAM containing the data to be
transferred by DMA into CCRx registers.
− Number of data to transfer = 3.
− Circular mode disabled.
2. Configure the DCR register by configuring the DBA and DBL bit fields: DBL=3, DMA burst length of the
transfer is 3 , DBA=0xE, the initial transfer address offset is 0x38(TIMx_CCR2).
3. Enable the TIMx update DMA request
4. Enable TIMx
5. Enable the DMA channel
Note:This example is for the case where every CCRx register to be updated once. If every CCRx register is
to be updated twice for example, the number of data to transfer should be 6. Let’s take the example of a
buffer in the RAM containing data1, data2, data3, data4, data5 and data6. The data is transferred to the
CCRx registers as follows: on the first update DMA request, data1 is transferred to CCR2, data2 is
transferred to CCR3, data3 is transferred to CCR4 and on the second update DMA request, data4 is
transferred to CCR2, data5 is transferred to CCR3 and data6 is transferred to CCR4.

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17. General-purpose timers(TIM3)

17.1. TIM3 introduction

The general-purpose timers consist of a 16-bit auto-reload counter driven by a programmable prescaler.
They may be used for a variety of purposes, including measuring the pulse lengths of input signals (input
capture) or generating output waveforms (output compare and PWM).
Pulse lengths and waveform periods can be modulated from a few microseconds to several milliseconds
using the timer prescaler and the RCC clock controller prescalers.
The timers are completely independent, and do not share any resources. They can be synchronized
together as described in Section 17.3.15.

17.2. TIM3 main features

TIM3 features include:


 116-bit up, down, up/down auto-reload counter.
 16-bit programmable prescaler used to divide (also “on the fly”) the counter clock frequency by any
factor between 1 and 65535.
 Up to 4 independent channels for:
− Input capture
− Output compare
− PWM generation (Edge- and Center-aligned modes)
− One-pulse mode output
 Synchronization circuit to control the timer with external signals and to interconnect several timers.
 Interrupt/DMA generation on the following events:
− Update: counter overflow/underflow, counter initialization (by software or internal/external trigger)
− Trigger event (counter start, stop, initialization or count by internal/external trigger)
− Input capture
− Output compare
− Break input
 Supports incremental (quadrature) encoder and hall-sensor circuitry for positioning purposes
 Trigger input for external clock or cycle-by-cycle current management

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Internal Clock(CK_INT)
CK_TIM from RCC
ETRP Trigger
ETR Polarity Selection & Edge ETRF Controller TRGO
TIM1_ETR Input Filter
Detector & Prescaler to other timers
to DAC/ADC
ITR0
ITR1 ITR TGI Reset, Enable, Up/Down, Count
ITR2 Slave
ITR3 TRC TRGI Mode
Controller
TI1F_ED

TI1FP1 Encoder
TI1FP2 Interface

Auto-reload register UI

Stop,clear or up/down
UEV
CK_PSC PSC CK_CNT
+/- CNT counter
prescaler
CC1I UEV
XOR CC1I
TI1FP1 OC1 TIM1_CH1
TIM1_CH1 TI1 Input Filter & TI1FP2 IC1 IC1PS OC1REF output
Edge Prescaler Capture/Compare 1 Register
control
detector TRC
CC2I UEV
CC2I
OC2 TIM1_CH2
TIM1_CH2 TI2 Input Filter & TI2FP1 IC2 IC2PS OC2REF output
Edge TI2FP2 Prescaler Capture/Compare 2 Register
control
detector TRC
CC3I UEV
CC3I
TI3FP3 OC3 TIM1_CH3
TIM1_CH3 Input Filter & IC3 IC3PS OC3REF output
TI3 TI3FP4
Edge Prescaler Capture/Compare 3 Register
control
detector
TRC
CC4I UEV
CC4I
OC4 TIM1_CH4
TIM1_CH4 TI4 Input Filter & TI4FP3 IC4 IC4PS OC4REF output
Edge TI4FP4 Prescaler Capture/Compare 4 Register control
detector
TRC
ETRF

Notes:
Preload registers transferred
Reg
to active registers on UEV event
according to control bit

event

interrupt & DMA output

Figure 17-1 General-purpose timer block diagram (TIM3)

17.3. TIM3 functional description

17.3.1. Time-base unit

The main block of the programmable timer is a 16-bit counter with its related auto-reload register. The
counter can count up but also down or both up and down. The counter clock can be divided by a prescaler.
The counter, the auto-reload register and the prescaler register can be written or read by software. This is
true even when the counter is running.
The time-base unit includes:
 Counter Register(TIMx_CNT)
 Prescaler Register(TIMx_PSC)
 Auto-Reload Register(TIMx_ARR)

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The auto-reload register is preloaded. Writing to or reading from the auto-reload register accesses the
preload register. The content of the preload register are transferred into the shadow register permanently or
at each update event (UEV), depending on the auto-reload preload enable bit (ARPE) in TIMx_CR1 register.
The update event is sent when the counter reaches the overflow (or underflow when downcounting) and if
the UDIS bit equals 0 in the TIMx_CR1 register. It can also be generated by software. The generation of the
update event is described in detail for each configuration.
The counter is clocked by the prescaler output CK_CNT, which is enabled only when the counter enable bit
(CEN) in TIMx_CR1 register is set (refer also to the slave mode controller description to get more details on
counter enabling).
Note that the actual counter enable signal CNT_EN is set 1 clock cycle after CEN.

Prescaler description
The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It is based on a
16-bit counter controlled through a 16-bit register (in the TIMx_PSC register). It can be changed on the fly as
this control register is buffered. The new prescaler ratio is taken into account at the next update event.

Figure 17-2 and Figure 17-3 give some examples of the counter behavior when the prescaler ratio is
changed on the fly:
CK_PSC

CEN

CK_CNT

Counter register F7 F8 F9 FA FB FC 00 01 02 03

UEV

Prescaler control register 0 1

Write a new value in TIMx_PSC

Prescaler buffer 0 1

Prescaler counter 0 0 1 0 1 0 1 0 1

Figure 17-2 Counter timing diagram with prescaler division change from 1 to 2

CK_PSC

CEN

CK_CNT

Counter register F7 F8 F9 FA FB FC 00 01

UEV

Prescaler control register 0 3

Write a new value in TIMx_PSC

Prescaler buffer 0 3

Prescaler counter 0 0 1 2 3 0 1 2 3

Figure 17-3 Counter timing diagram with prescaler division change from 1 to 4

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17.3.2. Counter modes

Upcounting mode
In upcounting mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register),
then restarts from 0 and generates a counter overflow event.
An Update event can be generated at each counter overflow or by setting the UG bit in the TIMx_EGR
register (by software or by using the slave mode controller).
The UEV event can be disabled by software by setting the UDIS bit in TIMx_CR1 register. This is to avoid
updating the shadow registers while writing new values in the preload registers. Then no update event
occurs until the UDIS bit has been written to 0. However, the counter restarts from 0, as well as the counter
of the prescaler (but the prescale rate does not change). In addition, if the URS bit (update request selection)
in TIMx_CR1 register is set, setting the UG bit generates an update event UEV but without setting the UIF
flag (thus no interrupt or DMA request is sent). This is to avoid generating both update and capture interrupts
when clearing the counter on the capture event.
When an update event occurs, all the registers are updated and the update flag (UIF bit in TIMx_SR register)
is set (depending on the URS bit):
 The auto-reload shadow register is updated with the preload value (TIMx_ARR)
 The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC register)
The following figures show some examples of the counter behavior for different clock frequencies when
TIMx_ARR=0x36.

CK_PSC

CNT_EN

CK_CNT

Counter register 31 32 33 34 35 36 00 01 02 03 04 05 06 07

Counter overflow

UEV

UIF

Figure 17-4 Counter timing diagram, internal clock divided by 1

CK_PSC

CNT_EN

CK_CNT

Counter register 34 35 36 00 01 02 03

Counter overflow

UEV

UIF

Figure 17-5 Counter timing diagram, internal clock divided by 2

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CK_PSC

CNT_EN

CK_CNT

Counter register 35 36 00 01

Counter overflow

UEV

UIF

Figure 17-6 Counter timing diagram, internal clock divided by 4

CK_PSC

CK_CNT

Counter register 35 36 00 01

Counter overflow

UEV

UIF

Figure 17-7 Counter timing diagram, internal clock divided by N


CK_PSC

CEN

CK_CNT

Counter register 31 32 33 34 35 36 00 01 02 03 04 05 06 07

Counter overflow

UEV

UIF

Auto-reload preload register FF 36

Write a new value in TIMx_ARR

Figure 17-8 Counter timing diagram, Update event when ARPE=0

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CK_PSC

CEN

CK_CNT

Counter register F0 F1 F2 F3 F4 F5 00 01 02 03 04 05 06 07

Counter overflow

UEV

UIF

Auto-reload preload register F5 36

Auto-reload shadow register F5 36

Write a new value in TIMx_ARR

Figure 17-9 Counter timing diagram, Update event when ARPE=1

Downcounting mode
In downcounting mode, the counter counts from the auto-reload value (content of the TIMx_ARR register)
down to 0, then restarts from the auto-reload value and generates a counter underflow event.
An Update event can be generate at each counter underflow or by setting the UG bit in the TIMx_EGR
register (by software or by using the slave mode controller)
In downcounting mode, the counter counts from the auto-reload value (content of the TIMx_ARR register)
down to 0, then restarts from the auto-reload value and generates a counter underflow event.
An Update event can be generate at each counter underflow or by setting the UG bit in the TIMx_EGR
register (by software or by using the slave mode controller)
The UEV update event can be disabled by software by setting the UDIS bit in TIMx_CR1 register. This is to
avoid updating the shadow registers while writing new values in the preload registers. Then no update event
occurs until UDIS bit has been written to 0. However, the counter restarts from the current auto-reload value,
whereas the counter of the prescaler restarts from 0 (but the prescale rate doesn’t change).
In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the UG bit
generates an update event UEV but without setting the UIF flag (thus no interrupt or DMA request is sent).
This is to avoid generating both update and capture interrupts when clearing the counter on the capture
event.
When an update event occurs, all the registers are updated and the update flag (UIF bit in TIMx_SR register)
is set (depending on the URS bit):
 The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC register).
 The auto-reload active register is updated with the preload value (content of the TIMx_ARR register).
Note that the auto-reload is updated before the counter is reloaded, so that the next period is the
expected one.
The following figures show some examples of the counter behavior for different clock frequencies when
TIMx_ARR=0x36.

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CK_PSC

CNT_EN

CK_CNT

Counter register 05 04 03 02 01 00 36 35 34 33 32 31 30 2F

Counter underflow

UEV

UIF

Figure 17-10 Counter timing diagram, internal clock divided by 1

CK_PSC

CNT_EN

CK_CNT

Counter register 02 01 00 36 35 34 33

Counter underflow

UEV

UIF

Figure 17-11 Counter timing diagram, internal clock divided by 2

CK_PSC

CNT_EN

CK_CNT

Counter register 01 00 36 35

Counter underflow

UEV

UIF

Figure 17-12 Counter timing diagram, internal clock divided by 4

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CK_PSC

CK_CNT

Counter register 20 1F 00 36 01

Counter underflow

UEV

UIF

Figure 17-13 Counter timing diagram, internal clock divided by N

CK_PSC

CEN

CK_CNT

Counter register 05 04 03 02 01 00 36 35 34 33 32 31 30 2F

Counter underflow

UEV

UIF

Auto-reload preload register FF 36

Write a new value in TIMx_ARR

Figure 17-14 Counter timing diagram, Update event when repetition counter is not used

Center-aligned mode (up/down counting)


In center-aligned mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR
register) – 1, generates a counter overflow event, then counts from the auto-reload value down to 1 and
generates a counter underflow event. Then it restarts counting from 0.
Center-aligned mode is active when the CMS bits in TIMx_CR1 register are not equal to ‘00’. The Output
compare interrupt flag of channels configured in output is set when: the counter counts down (Center
aligned mode 1, CMS = “01”), the counter counts up (Center aligned mode 2, CMS = “10”) the counter
counts up and down (Center aligned mode 3, CMS = “11”).
In this mode, the direction bit (DIR from TIMx_CR1 register) cannot be written. It is updated by hardware
and gives the current direction of the counter.
The update event can be generated at each counter overflow and at each counter underflow or by setting
the UG bit in the TIMx_EGR register (by software or by using the slave mode controller) also generates an
update event. In this case, the counter restarts counting from 0, as well as the counter of the prescaler.
The UEV update event can be disabled by software by setting the UDIS bit in TIMx_CR1 register. This is to
avoid updating the shadow registers while writing new values in the preload registers. Then no update event
occurs until the UDIS bit has been written to 0. However, the counter continues counting up and down,
based on the current auto-reload value.
In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the UG bit
generates an update event UEV but without setting the UIF flag (thus no interrupt or DMA request is sent).

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This is to avoid generating both update and capture interrupt when clearing the counter on the capture
event.
When an update event occurs, all the registers are updated and the update flag (UIF bit in TIMx_SR register)
is set (depending on the URS bit):
 The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC register).
 The auto-reload active register is updated with the preload value (content of the TIMx_ARR register).
Note that if the update source is a counter overflow, the autoreload is updated before the counter is
reloaded, so that the next period is the expected one (the counter is loaded with the new value).
The following figures show some examples of the counter behavior for different clock frequencies.

CK_PSC

CNT_EN

CK_CNT

Counter register 04 03 02 01 00 01 02 03 04 05 06 05 04 03

Counter underflow

Counter overflow

UEV

UIF

Figure 17-15 Counter timing diagram, internal clock divided by 1,TIMx_ARR=0x6


1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

CK_PSC

CNT_EN

CK_CNT

Counter register 02 01 00 36 35 34 33

Counter underflow

UEV

UIF

Figure 17-16 Counter timing diagram, internal clock divided by 2

CK_PSC

CNT_EN

CK_CNT

Counter register 35 36 36 35

Counter overflow

UEV

UIF

Figure 17-17 Counter timing diagram, internal clock divided by 4,TIMx_ARR=0x36

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CK_PSC

CK_CNT

Counter register 20 1F 01 00 01

Counter underflow

UEV

UIF

Figure 17-18 Counter timing diagram, internal clock divided by N


CK_PSC

CEN

CK_CNT

Counter register 06 05 04 03 02 01 00 01 02 03 04 05 06 07

Counter underflow

UEV

UIF

Auto-reload preload register FD 36

Auto-reload shadow register FD 36

Write a new value in TIMx_ARR

Figure 17-19 Counter timing diagram, Update event with ARPE=1 (counter underflow)
CK_PSC

CEN

CK_CNT

Counter register F7 F8 F9 FA FB FC 36 35 34 33 32 31 30 2F

Counter overflow

UEV

UIF

Auto-reload preload register FD 36

Auto-reload shadow register FD 36

Write a new value in TIMx_ARR

Figure 17-20 Counter timing diagram, Update event with ARPE=1 (counter overflow)

17.3.3. Clock sources

The counter clock can be provided by the following clock sources:


 Internal clock(CK_INT)

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 External clock mode1: external input pin


 External clock mode2: external trigger input (ETR)
 Internal trigger inputs (ITRx): using one timer as prescaler for another timer, for example, you can
configure Timer 1 to act as a prescaler for Timer 2.

Internal clock source (CK_INT)


If the slave mode controller is disabled (SMS=000 in the TIMx_SMCR register), then the CEN, DIR (in the
TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual control bits and can be changed only
by software (except UG which remains cleared automatically). As soon as the CEN bit is written to 1, the
prescaler is clocked by the internal clock CK_INT.
Figure 17-21 shows the behavior of the control circuit and the upcounter in normal mode, without prescaler.

Interal clock

CNT_EN

UG

CNT_INIT

CK_CNT=CK_PSC

Counter register 31 32 33 34 35 36 00 01 02 03 04 05 06 07

Figure 17-21 Control circuit in normal mode, internal clock divided by 1

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External clock source mode 1


This mode is selected when SMS=111 in the TIMx_SMCR register. The counter can count at each rising or
falling edge on a selected input.

TIMx_SMCR
TS[2:0]
T12F or
TI1F or Encoder
ITRx mode
0xx
TI1_ED
100
TRGI External
TI1FP1 clock mode 1
101 CK_PSC
TI2F_rising
TI2 Edge 0 TI2FP2
Filter TI2F_falling 1 110
Detector
ETRF External
111 ETRF
clock mode 2
ICF[3:0] CC2P
TIMx_CCMR1 TIMx_CCER
CK_INT Internal clock
(internal clock) mode

ECE SMS[2:0]
TIMx_SMCR

Figure 17-22 TI2 external clock connection example

For example, to configure the upcounter to count in response to a rising edge on the TI2 input, use the
following procedure:
1. Configure channel 2 to detect rising edges on the TI2 input by writing CC2S= ‘01’ in the TIMx_CCMR1
register.
2. Configure the input filter duration by writing the IC2F[3:0] bits in the TIMx_CCMR1 register (if no filter is
needed, keep IC2F=0000).
3. Select rising edge polarity by writing CC2P=0 in the TIMx_CCER register
4. Configure the timer in external clock mode 1 by writing SMS=111 in the TIMx_SMCR register.
5. Select TI2 as the input source by writing TS=110 in the TIMx_SMCR register.
6. Enable the counter by writing CEN=1 in the TIMx_CR1 register.
Note: The capture prescaler is not used for triggering, so you don’t need to configure it.
When a rising edge occurs on TI2, the counter counts once and the TIF flag is set.
The delay between the rising edge on TI2 and the actual clock of the counter is due to the resynchronization
circuit on TI2 input.

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TI2

CEN

CK_CNT=CK_PSC

Counter register 34 35 36 0

TIF

Write TIF=0

Figure 17-23 Control circuit in external clock mode 1


External clock source mode 2
This mode is selected by writing ECE=1 in the TIMx_SMCR register.
The counter can count at each rising or falling edge on the external trigger input ETR.

T12F or
TI1F or Encoder
mode

TRGI External
clock mode 1 CK_PSC
fDTS
ETR Filter ETRF External
0 Divider
ETRP down-counter clock mode 2
1 /1,/2,/4,/8

CK_INT Internal clock


ETP ETPS[1:0] ETF[3:0] mode
internal clock
TIMx_SMCR TIMx_SMCR TIMx_SMCR
ECE SMS[2:0]
TIMx_SMCR

Figure 17-24 External trigger input block

For example, to configure the upcounter to count each 2 rising edges on ETR, use the following procedure:
1. As no filter is needed in this example, write ETF[3:0]=0000 in the TIMx_SMCR register.
2. Set the prescaler by writing ETPS[1:0]=01 in the TIMx_SMCR register
3. Select rising edge detection on the ETR pin by writing ETP=0 in the TIMx_SMCR register
4. Enable external clock mode 2 by writing ECE=1 in the TIMx_SMCR register.
5. Enable the counter by writing CEN=1 in the TIMx_CR1 register.
The counter counts once each 2 ETR rising edges
The delay between the rising edge on ETR and the actual clock of the counter is due to the
resynchronization circuit on the ETRP signal.

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fCK_INT

CNT_EN
del ay
del ay

ETR

ETRP

ETRF

CK_INT=CK_PSC

COUNTER 34 35 36

Figure 17-25 Control circuit in external clock mode 2

17.3.4. Capture/compare channels

Each Capture/Compare channel is built around a capture/compare register (including a shadow register), a
input stage for capture (with digital filter, multiplexing and prescaler) and an output stage (with comparator
and output control).
The input stage samples the corresponding Tix input to generate a filtered signal TixF. Then, an edge
detector with polarity selection generates a signal (TixFPx) which can be used as trigger input by the slave
mode controller or as the capture command. It is prescaled before the capture register(IC1PS).

TI1F_ED
To the slave mode controller

TI1 TI1F_Rising
Filter Edge 0 TI1FP1
fDTS
downcounter detector TI1F_Falling 1
01
TI2FP1 IC1 Divider IC1PS
10
ICF[3:0] /1,/2,/4,/8
CC1P/CC1NP TRC
TIMx_CCMR1 11
TIMx_CCER (from slave
mode controller)

TI2F_Rising
(from channel 2) 0
CC1S[1:0] ICPS[1:0] CCIE
TI2F_Falling 1
TIMx_CCMR1 TIMx_CCER
(from channel 2)

Figure 17-26 Capture/compare channel (example: channel 1 input stage)

The output stage generates an intermediate waveform which is then used for reference: OcxRef (active
high). The polarity acts at the end of the chain.

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APB Bus

MCU-peripheral interface

high 8
if 16-bit

low 8
write_in_progress S write CCR1H
Read CCR1H S read_in_progress
Capture/Compare Preload Register R write CCR1L
Read CCR1L R CC1S[1]
capture_transfer compare_transfer output
CC1S[0]
CC1S[1] mode
OC1PE OC1PE
CC1S[0] Capture/Compare Shadow Register UEV
from time TIMx_CCMR1
IC1PS capture base unit
CC1E CNT>CCR1
Counter CNT=CCR1
CC1G
TIMx_EGR

Figure 17-27 Capture/compare channel 1 main circuit

TIMx_SMCR
OCCS

OCREF_CLR
0
ETRF To the master
1
mode controller
ocref_clr_int
‘0’
0
CNT>CCR1 Output 0 Output OC1
mode OC1REF enable
CNT=CCR1 1 1 circuit
controller

CC1P
TIMx_CCER CC1E TIMx_CCER

OC1M[2:0] CC1E
TIMx_CCMR1 TIMx_CCER

Figure 17-28 Output stage of capture/compare channel (channel 1)


The capture/compare block is made of one preload register and one shadow register. Write and read always
access the preload register.
In capture mode, captures are actually done in the shadow register, which is copied into the preload register.
In compare mode, the content of the preload register is copied into the shadow register which is compared
to the counter.

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17.3.5. Input capture mode

In Input capture mode, the Capture/Compare Registers (TIMx_CCRx) are used to latch the value of the
counter after a transition detected by the corresponding Icx signal. When a capture occurs, the
corresponding CCXIF flag (TIMx_SR register) is set and an interrupt or a DMA request can be sent if they
are enabled. If a capture occurs while the CcxIF flag was already high, then the over-capture flag CcxOF
(TIMx_SR register) is set. CcxIF can be cleared by software by writing it to 0 or by reading the captured data
stored in the TIMx_CCRx register. CcxOF is cleared when you write it to 0.
The following example shows how to capture the counter value in TIMx_CCR1 when TI1 input rises. To do
this, use the following procedure:
 Select the active input: TIMx_CCR1 must be linked to the TI1 input, so write the CC1S bits to 01 in the
TIMx_CCMR1 register. As soon as CC1S becomes different from 00, the channel is configured in input
and the TIMx_CCR1 register becomes read-only.
 Program the input filter duration you need with respect to the signal you connect to the timer when the
input is one of the Tix (IcxF bits in the TIMx_CCMRx register). Let’s imagine that, when toggling, the
input signal is not stable during at must 5 internal clock cycles. We must program a filter duration longer
than these 5 clock cycles. We can validate a transition on TI1 when 8 consecutive samples with the
new level have been detected (sampled at fDTS frequency). Then write IC1F bits to 0011 in the
TIMx_CCMR1 register.
 Program the input prescaler. In our example, we wish the capture to be performed at each valid
transition, so the prescaler is disabled (write IC1PS bits to 00 in the TIMx_CCMR1 register).
 Enable capture from the counter into the capture register by setting the CC1E bit in the TIMx_CCER
register.
 If needed, enable the related interrupt request by setting the CC1IE bit in the TIMx_DIER register,
and/or the DMA request by setting the CC1DE bit in the TIMx_DIER register.
When an input capture occurs:
 The TIMx_CCR1 register gets the value of the counter on the active transition.
 CC1IF flag is set (interrupt flag). CC1OF is also set if at least two consecutive captures occurred
whereas the flag was not cleared.
 An interrupt is generated depending on the CC1IE bit.
 A DMA request is generated depending on the CC1DE bit.
In order to handle the overcapture, it is recommended to read the data before the overcapture flag. This is to
avoid missing an overcapture which could happen after reading the flag and before reading the data.
IC interrupt and/or DMA requests can be generated by software by setting the corresponding CCxG bit in the
TIMx_EGR register.

17.3.6. PWM input mode

This mode is a particular case of input capture mode. The procedure is the same except:
 Two Icx signals are mapped on the same Tix input.
 These 2 Icx signals are active on edges with opposite polarity.

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 One of the two TixFP signals is selected as trigger input and the slave mode controller is configured in
reset mode.
For example, you can measure the period (in TIMx_CCR1 register) and the duty cycle (in TIMx_CCR2
register) of the PWM applied on TI1 using the following procedure (depending on CK_INT frequency and
prescaler value):
 Select the active input for TIMx_CCR1: write the CC1S bits to 01 in the TIMx_CCMR1 register (TI1
selected).
 Select the active polarity for TI1FP1 (used both for capture in TIMx_CCR1 and counter clear): write the
CC1P to ‘0’ (active on rising edge).
 Select the active input for TIMx_CCR2: write the CC2S bits to 10 in the TIMx_CCMR1 register (TI1
selected).
 Select the active polarity for TI1FP2 (used for capture in TIMx_CCR2): write the CC2P bit to ‘1’ (active
on falling edge).
 Select the valid trigger input: write the TS bits to 101 in the TIMx_SMCR register (TI1FP1 selected).
 Configure the slave mode controller in reset mode: write the SMS bits to 100 in the TIMx_SMCR
register.
 Enable the captures: write the CC1E and CC2E bits to ‘1’ in the TIMx_CCER register.

TI1

IC1/IC2

COUNTER
5 0 1 2 3 4 5 0

T1CCR1 5

T1CCR2 3

IC1: IC2: IC1:


reset counter m easure m easure
pulse width pulse period

Figure 17-29 PWM input mode timing

17.3.7. Forced output mode

In output mode (CCxS bits = 00 in the TIMx_CCMRx register), each output compare signal (OCxREF and
then Ocx/OcxN) can be forced to active or inactive level directly by software, independently of any
comparison between the output compare register and the counter.
To force an output compare signal (ocxref/Ocx) to its active level, you just need to write 101 in the OcxM bits
in the corresponding TIMx_CCMRx register. Thus OCxREF is forced high (OCxREF is always active high)
and Ocx get opposite value to CCxP polarity bit.
e.g.: CCxP=0 (Ocx active high) => Ocx is forced to high level.
OCxREF signal can be forced low by writing the OcxM bits to 100 in the TIMx_CCMRx register.
Anyway, the comparison between the TIMx_CCRx shadow register and the counter is still performed and
allows the flag to be set. Interrupt and DMA requests can be sent accordingly. This is described in the Output

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Compare Mode section.

17.3.8. Output compare mode

This function is used to control an output waveform or indicating when a period of time has elapsed.
When a match is found between the capture/compare register and the counter, the output compare function:
 Assigns the corresponding output pin to a programmable value defined by the output compare mode
(OcxM bits in the TIMx_CCMRx register) and the output polarity (CCxP bit in the TIMx_CCER register).
The output pin can keep its level (OCXM=000), be set active (OcxM=001), be set inactive (OcxM=010)
or can toggle (OcxM=011) on match.
 Sets a flag in the interrupt status register (CcxIF bit in the TIMx_SR register).
 Generates an interrupt if the corresponding interrupt mask is set (CCXIE bit in the TIMx_DIER register).
 Sends a DMA request if the corresponding enable bit is set (CcxDE bit in the TIMx_DIER register,
CCDS bit in the TIMx_CR2 register for the DMA request selection).
The TIMx_CCRx registers can be programmed with or without preload registers using the OcxPE bit in the
TIMx_CCMRx register.
In output compare mode, the update event UEV has no effect on OCxREF and Ocx output. The timing
resolution is one count of the counter. Output compare mode can also be used to output a single pulse (in
One-pulse mode).
Procedure:
1. Select the counter clock (internal, external, prescaler).
2. Write the desired data in the TIMx_ARR and TIMx_CCRx registers.
3. Set the CcxIE bits if an interrupt is to be generated.
4. Select the output mode,For example:
− Write OcxM = 011 to toggle Ocx output pin when CNT matches CCRx
− Write OcxPE = 0 to disable preload register
− Write CCxP = 0 to select active high polarity
− Write CcxE = 1 to enable the output
5. Enable the counter by setting the CEN bit in the TIMx_CR1 register.
The TIMx_CCRx register can be updated at any time by software to control the output waveform, provided
that the preload register is not enabled (OcxPE=0, else TIMx_CCRx shadow register is updated only at the
next update event UEV). An example is given in Figure 17-30.

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Write B201h in the CC1R register

TIM1_CNT 0039 003A 003B B200 B201 B202 03

TIM1_CCR1 003A B201

oc1ref=OC1

Match detected on CCR1


Interrupt generated if enabled

Figure 17-30 Output compare mode, toggle on OC1

17.3.9. PWM mode

Pulse width modulation mode allows you to generate a signal with a frequency determined by the value of
the TIMx_ARR register and a duty cycle determined by the value of the TIMx_CCRx register.
The PWM mode can be selected independently on each channel (one PWM per Ocx output) by writing 110
(PWM mode 1) or ‘111 (PWM mode 2) in the OcxM bits in the TIMx_CCMRx register. You must enable the
corresponding preload register by setting the OcxPE bit in the TIMx_CCMRx register, and eventually the
auto-reload preload register (in upcounting or center-aligned modes) by setting the ARPE bit in the
TIMx_CR1 register.
As the preload registers are transferred to the shadow registers only when an update event occurs, before
starting the counter, you have to initialize all the registers by setting the UG bit in the TIMx_EGR register.
Ocx polarity is software programmable using the CCxP bit in the TIMx_CCER register. It can be
programmed as active high or active low. Ocx output is enabled by a combination of the CcxE, CcxNE, MOE,
OSSI and OSSR bits
In PWM mode (1 or 2), TIMx_CNT and TIMx_CCRx are always compared to determine whether
TIMx_CCRx≤ TIMx_CNT or TIMx_CNT≤ TIMx_CCRx (depending on the direction of the counter). The timer
is able to generate PWM in edge-aligned mode or center-aligned mode depending on the CMS bits in the
TIMx_CR1 register.

PWM edge-aligned mode


 Upcounting configuration
Upcounting is active when the DIR bit in the TIMx_CR1 register is low. In the following example, we consider
PWM mode 1. The reference PWM signal OCxREF is high as long as TIMx_CNT <TIMx_CCRx else it
becomes low. If the compare value in TIMx_CCRx is greater than the auto-reload value (in TIMx_ARR) then
OCxREF is held at ‘1. If the compare value is 0 then OCxREF is held at ‘0’.
Figure 17-31 shows some edge-aligned PWM waveforms in an example where TIMx_ARR=8.

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Counter register 0 1 2 3 4 5 6 7 8 0 1

OCxREF
CCRx=4
CCxIF

OCxREF
CCRx=8
CCxIF

OCxREF ‘1’
CCRx>8
CCxIF

OCxREF
‘0’
CCRx=0
CCxIF

Figure 17-31 Edge-aligned PWM waveforms (ARR=8)


 Downcounting configuration
In PWM mode 1, the reference signal ocxref is low as long as TIMx_CNT>TIMx_CCRx else it becomes high.
If the compare value in TIMx_CCRx is greater than the auto-reload value in TIMx_ARR, then ocxref is held
at ‘1’. 0% PWM is not possible in this mode.

PWM center-aligned mode


Center-aligned mode is active when the CMS bits in TIMx_CR1 register are different from ’00 (all the
remaining configurations having the same effect on the OCxREF/Ocx signals). The compare flag is set
when the counter counts up, when it counts down or both when it counts up and down depending on the
CMS bits configuration. The direction bit (DIR) in the TIMx_CR1 register is updated by hardware and must
not be changed by software.
Figure 17-32 shows some center-aligned PWM waveforms in an example where:
 TIMx_ARR=8
 PWM mode 1
 The flag is set when the counter counts down corresponding to the center-aligned mode 1 selected for
CMS=01 in TIMx_CR1 register

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Counter register 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1 0 1 2

OCxREF
CCRx=4 CMS=01
CCxIF CMS=10
CMS=11

OCxREF
CCRx=7
CCxIF CMS=10 or 11

OCxREF
CCRx=8 CMS=01
CCxIF CMS=10
CMS=11

OCxREF
CCRx>8
CMS=01
CCxIF CMS=10
CMS=11

OCxREF
CCRx=0
CMS=01
CCxIF CMS=10
CMS=11

Figure 17-32 Center-aligned PWM waveforms (ARR=8)


Hints on using center-aligned mode:
 When starting in center-aligned mode, the current up-down configuration is used. It means that the
counter counts up or down depending on the value written in the DIR bit in the TIMx_CR1 register.
Moreover, the DIR and CMS bits must not be changed at the same time by the software.
 Writing to the counter while running in center-aligned mode is not recommended as it can lead to
unexpected results. In particular:
− The direction is not updated if you write a value in the counter that is greater than the auto-reload
value (TIMx_CNT>TIMx_ARR). For example, if the counter was counting up, it continues to count
up.
− The direction is updated if you write 0 or write the TIMx_ARR value in the counter but no Update
Event UEV is generated.
 The safest way to use center-aligned mode is to generate an update by software (setting the UG bit in
the TIMx_EGR register) just before starting the counter and not to write the counter while it is running.

17.3.10. One-pulse mode

Be started in response to a stimulus and to generate a pulse with a programmable length after a
programmable delay.
Starting the counter can be controlled through the slave mode controller. Generating the waveform can be
done in output compare mode or PWM mode. You select One-pulse mode by setting the OPM bit in the
TIMx_CR1 register. This makes the counter stop automatically at the next update event UEV.

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A pulse can be correctly generated only if the compare value is different from the counter initial value. Before
starting (when the timer is waiting for the trigger), the configuration must be:
 In upcounting: CNT<CCRx≤ ARR (in particular, 0<CCRx),
 In downcounting: CNT>CCRx.

TI2

OC1REF

OC1

TIM1_ARR

TIM1_CCR1

0 Tdelay TIME
Tpulse

Figure 17-33 Example of one-pulse mode


For example you may want to generate a positive pulse on OC1 with a length of 𝑇𝑝𝑢𝑙𝑠𝑒 and after a delay of
𝑇𝑑𝑒𝑙𝑎𝑦 as soon as a positive edge is detected on the TI2 input pin.
Use TI2FP2 as trigger 1:
 Map TI2FP2 on TI2 by writing CC2S=01 in the TIMx_CCMR1 register.
 TI2FP2 must detect a rising edge, write CC2P=0 and CC2NP=’0’ in the TIMx_CCER register.
 Configure TI2FP2 as trigger for the slave mode controller (TRGI) by writing TS=110 in the TIMx_SMCR
register.
 TI2FP2 is used to start the counter by writing SMS to ‘110’ in the TIMx_SMCR register (trigger mode).
The OPM waveform is defined by writing the compare registers (taking into account the clock frequency and
the counter prescaler).
 The 𝑇𝑑𝑒𝑙𝑎𝑦 is defined by the value written in the TIMx_CCR1 register.
 The 𝑇𝑝𝑢𝑙𝑠𝑒 is defined by the difference between the auto-reload value and the compare
value(TIMx_ARR-TIMx_CCR1 + 1)
 Let’s say you want to build a waveform with a transition from ‘0’to ‘1’ when a compare match occurs and
a transition from ‘1’ to ‘0’ when the counter reaches the auto-reload value. To do this you enable PWM
mode 2 by writing OC1M=111 in the TIMx_CCMR1 register. You can optionally enable the preload
registers by writing OC1PE=1 in the TIMx_CCMR1 register and ARPE in the TIMx_CR1 register. In this
case you have to write the compare value in the TIMx_CCR1 register, the auto-reload value in the
TIMx_ARR register, generate an update by setting the UG bit and wait for external trigger event on TI2.
CC1P is written to ‘0 in this example.
In our example, the DIR and CMS bits in the TIMx_CR1 register should be low.
You only want 1 pulse, so you write ‘1’ in the OPM bit in the TIMx_CR1 register to stop the counter at the

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next update event (when the counter rolls over from the auto-reload value back to 0). When OPM bit in the
TIMx_CR1 register is set to ‘0’, so the Repetitive Mode is selected.

Particular case: Ocx fast enable


In One-pulse mode, the edge detection on Tix input set the CEN bit which enables the counter. Then the
comparison between the counter and the compare value makes the output toggle. But several clock cycles
are needed for these operations and it limits the minimum delay 𝑇𝑑𝑒𝑙𝑎𝑦 min we can get.
If you want to output a waveform with the minimum delay, you can set the OcxFE bit in the TIMx_CCMRx
register. Then OCxREF (and Ocx) are forced in response to the stimulus, without taking in account the
comparison. Its new level is the same as if a compare match had occurred. OcxFE acts only if the channel is
configured in PWM1 or PWM2 mode.

17.3.11. Clearing the OCxREF signal on an external event

the OCxREF signal can be connected to the output of a comparator to be used for current handling. In this
case, the ETR must be configured as follow:
1. The external trigger prescaler should be kept off: bits ETPS[1:0] in the TIMx_SMCR register are cleared
to 00.
2. The external clock mode 2 must be disabled: bit ECE in the TIM1_SMCR register is cleared to 0.
3. The external trigger polarity (ETP) and the external trigger filter (ETF) can be configured according to
the application’s needs.
Figure 17-34 shows the behavior of the OCxREF signal when the ETRF input becomes high, for both
values of the OcxCE enable bit. In this example, the timer TIMx is programmed in PWM mode.

CCRx

Counter

ETRF

OCxREF
(OCxCE=0)

OCxREF
(OCxCE=0)

OCxREF_CLR OCxREF_CLR
become high still high

Figure 17-34 Clearing TIMx OCxREF


Note: In case of a PWM with a 100% duty cycle (if CCRx>ARR), OCxREF is enabled again at the next
counter overflow.

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17.3.12. Encoder interface mode

To select Encoder Interface mode write SMS=‘001 in the TIMx_SMCR register if the counter is counting on
TI2 edges only, SMS=010 if it is counting on TI1 edges only and SMS=011 if it is counting on both TI1 and
TI2 edges.
Select the TI1 and TI2 polarity by programming the CC1P and CC2P bits in the TIMx_CCER register.
CC1NP and CC2NP must be kept cleared. When needed, you can program the input filter as well.
The two inputs TI1 and TI2 are used to interface to an incremental encoder. Refer to Table 17-1. The
counter is clocked by each valid transition on TI1FP1 or TI2FP2 (TI1 and TI2after input filter and polarity
selection, TI1FP1=TI1 if not filtered and not inverted, TI2FP2=TI2 if not filtered and not inverted) assuming
that it is enabled (CEN bit in TIMx_CR1 register written to ‘1). The sequence of transitions of the two inputs
is evaluated and generates count pulses as well as the direction signal. Depending on the sequence the
counter counts up or down, the DIR bit in the TIMx_CR1 register is modified by hardware accordingly. The
DIR bit is calculated at each transition on any input (TI1 or TI2), whatever the counter is counting on TI1 only,
TI2 only or both TI1 and TI2.
Encoder interface mode acts simply as an external clock with direction selection. This means that the
counter just counts continuously between 0 and the auto-reload value in the TIMx_ARR register (0 to ARR
or ARR down to 0 depending on the direction). So you must configure TIMx_ARR before starting. In the
same way, the capture, compare, prescaler, trigger output features continue to work as normal.
Encoder mode and External clock mode 2 are not compatible and must not be selected together.
In this mode, the counter is modified automatically following the speed and the direction of the incremental
encoder and its content, therefore, always represents the encoder’s position. The count direction
correspond to the rotation direction of the connected sensor. The table summarizes the possible
combinations, assuming TI1 and TI2 don’t switch at the same time.
Table 17-1 Counting direction versus encoder signals

Level on opposite TI1FP1signal TI2FP2signal

Active edge signal (TI1FP1 for TI2)


Rising Falling Rising Falling
(TI2FP2 for TI1)

High Down Up —— ——
TI1
Low Up Down —— ——
High —— —— Up Down
TI2
Low —— —— Down Up
High Down Up Up Down
TI1 or TI2
Low Up Down Down Up

An external incremental encoder can be connected directly to the MCU without external interface logic.
However, comparators are normally be used to convert the encoder’s differential outputs to digital signals.
This greatly increases noise immunity. The third encoder output which indicate the mechanical zero position,
may be connected to an external interrupt input and trigger a counter reset.
Figure 17-35 gives an example of counter operation, showing count signal generation and direction control.
It also shows how input jitter is compensated where both edges are selected. This might occur if the sensor
is positioned near to one of the switching points. For this example we assume that the configuration is the

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following:
 CC1S= 01 (TIMx_CCMR1 register, TI1FP1 mapped on TI1)
 CC2S= 01 (TIMx_CCMR2 register, TI2FP2 mapped on TI2)
 CC1P=0 (TIMx_CCER register, TI1FP1 noninverted, TI1FP1=TI1)
 CC2P=0 (TIMx_CCER register, TI2FP2 noninverted, TI2FP2=TI2)
 SMS=011 (TIMx_SMCR register, both inputs are active on both rising and falling edges)
 CEN=1 (TIMx_CR1 register, Counter is enabled)

forward jitter backward jitter forward

TI1

TI2

Counter

UP DOWN UP

Figure 17-35 Example of counter operation in encoder interface mode


Figure 17-36 gives an example of counter behavior when TI1FP1 polarity is inverted (same configuration as
above except CC1P=1).

forward jitter backward jitter forward

TI1

TI2

Counter

DOWN UP DOWN

Figure 17-36 Example of encoder interface mode with TI1FP1 polarity inverted
The timer, when configured in Encoder Interface mode provides information on the sensor’s current position.
You can obtain dynamic information (speed, acceleration, deceleration) by measuring the period between
two encoder events using a second timer configured in capture mode. The output of the encoder which
indicates the mechanical zero can be used for this purpose. Depending on the time between two events, the
counter can also be read at regular times. You can do this by latching the counter value into a third input
capture register if available (then the capture signal must be periodic and can be generated by another
timer). When available, it is also possible to read its value through a DMA request generated by a Real-Time
clock.

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17.3.13. Timer input XOR function

The TI1S bit in the TIMx_CR2 register, allows the input filter of channel 1 to be connected to the output of a
XOR gate, combining the four input pins TIMx_CH1, TIMx_CH2 , TIMx_CH3 and TIMx_CH4.
The XOR output can be used with all the timer input functions such as trigger or input capture.

17.3.14. Timers and external trigger synchronization

The TIMx Timers can be synchronized with an external trigger in several modes: Reset mode, Gated mode
and Trigger mode.

Slave mode: Reset mode


The counter and its prescaler can be reinitialized in response to an event on a trigger input. Moreover, if the
URS bit from the TIMx_CR1 register is low, an update event UEV is generated. Then all the preloaded
registers (TIMx_ARR, TIMx_CCRx) are updated.
In the following example, the upcounter is cleared in response to a rising edge on TI1 input:
 Configure the channel 1 to detect rising edges on TI1. Configure the input filter duration (in this example,
we don’t need any filter, so we keep IC1F=0000). The capture prescaler is not used for triggering, so
you don’t need to configure it. The CC1S bits select the input capture source only, CC1S = 01 in the
TIMx_CCMR1 register. Write CC1P=0 and CC1NP=0 in TIMx_CCER register to validate the polarity
(and detect rising edges only).
 Configure the timer in reset mode by writing SMS=100 in TIMx_SMCR register. Select TI1 as the input
source by writing TS=101 in TIMx_SMCR register.
 Start the counter by writing CEN=1 in the TIMx_CR1 register.
The counter starts counting on the internal clock, then behaves normally until TI1 rising edge. When TI1
rises, the counter is cleared and restarts from 0. In the meantime, the trigger flag is set (TIF bit in the
TIMx_SR register) and an interrupt request, or a DMA request can be sent if enabled (depending on the TIE
and TDE bits in TIMx_DIER register).
Figure 17-37 shows this behavior when the auto-reload register TIMx_ARR=0x36. The delay between the
rising edge on TI1 and the actual reset of the counter is due to the resynchronization circuit on TI1 input.

TI1

UG

ck_cnt=ck_psc

Counter register 30 31 32 33 34 35 36 0 1 2 3 0 1 2 3

TIF

Figure 17-37 Control circuit in reset mode

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Slave mode: Gated mode


The counter can be enabled depending on the level of a selected input.
In the following example, the upcounter counts only when TI1 input is low:
 Configure the channel 1 to detect low levels on TI1. Configure the input filter duration (in this example,
we don’t need any filter, so we keep IC1F=0000). The capture prescaler is not used for triggering, so
you don’t need to configure it. The CC1S bits select the input capture source only, CC1S=01 in
TIMx_CCMR1 register. Write CC1P=1 and CC1NP=0 in TIMx_CCER register to validate the polarity
(and detect low level only).
 Configure the timer in gated mode by writing SMS=101 in TIMx_SMCR register. Select TI1 as the input
source by writing TS=101 in TIMx_SMCR register.
 Enable the counter by writing CEN=1 in the TIMx_CR1 register (in gated mode, the counter doesn’t
start if CEN=0, whatever is the trigger input level).
The counter starts counting on the internal clock as long as TI1 is low and stops as soon as TI1 becomes
high. The TIF flag in the TIMx_SR register is set both when the counter starts or stops.
The delay between the rising edge on TI1 and the actual stop of the counter is due to the resynchronization
circuit on TI1 input.

TI1

synchronization time
CEN

synchronization time
cnt_en

ck_cnt=ck_psc

Counter register 30 31 32 33 34 35 36 37 38

TIF

write TIF=0

Figure 17-38 Control circuit in gated mode


Slave mode: Trigger mode
The counter can start in response to an event on a selected input.
In the following example, the upcounter starts in response to a rising edge on TI2 input:
 Configure the channel 2 to detect rising edges on TI2. Configure the input filter duration (in this example,
we don’t need any filter, so we keep IC2F=0000). The capture prescaler is not used for triggering, so
you don’t need to configure it. CC2S bits are selecting the input capture source only, CC2S=01 in
TIMx_CCMR1 register. Write CC2P=1 and CC2NP=0 in TIMx_CCER register to validate the polarity
(and detect low level only)..
 Configure the timer in trigger mode by writing SMS=110 in TIMx_SMCR register. Select TI2 as the input
source by writing TS=110 in TIMx_SMCR register.
When a rising edge occurs on TI2, the counter starts counting on the internal clock and the TIF flag is set.
The delay between the rising edge on TI2 and the actual start of the counter is due to the resynchronization

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circuit on TI2 input.

TI2

synchorization tim e
CNT_EN

ck_cnt=ck_psc

Counter register 34 35 36 37

TIF

Figure 17-39 Control circuit in trigger mode

Slave mode: External Clock mode 2 + trigger mode


The external clock mode 2 can be used in addition to another slave mode (except external clock mode 1 and
encoder mode). In this case, the ETR signal is used as external clock input, and another input can be
selected as trigger input when operating in reset mode, gated mode or trigger mode. It is recommended not
to select ETR as TRGI through the TS bits of TIMx_SMCR register.
In the following example, the upcounter is incremented at each rising edge of the ETR signal as soon as a
rising edge of TI1 occurs:
1. Configure the external trigger input circuit by programming the TIMx_SMCR register as follows:
− ETF = 0000: no filter
− ETPS=00: prescaler disabled
− ETP=0: detection of rising edges on ETR and ECE=1 to enable the external clock mode 2.
2. Configure the channel 1 as follows, to detect rising edges on TI:
− IC1F=0000: no filter.
− The capture prescaler is not used for triggering and does not need to be configured.
− CC1S=01in TIMx_CCMR1 register to select only the input capture source
− CC1P=0 and CC1NP=0 in TIMx_CCER register to validate the polarity (and detect rising edge
only).
3. Configure the timer in trigger mode by writing SMS=110 in TIMx_SMCR register. Select TI1 as the input
source by writing TS=101 in TIMx_SMCR register.
A rising edge on TI1 enables the counter and sets the TIF flag. The counter then counts on ETR rising
edges.
The delay between the rising edge of the ETR signal and the actual reset of the counter is due to the
resynchronization circuit on ETRP input.

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TI1

CNT_EN

ETR

CK_CNT=CK_PSC

Counter register 34 35 36

TIF

Figure 17-40 Control circuit in external clock mode 2 + trigger mode

17.3.15. Timer synchronization

The TIMx timers are linked together internally for timer synchronization or chaining. When one Timer is
configured in Master Mode, it can reset, start, stop or clock the counter of another Timer configured in Slave
Mode.
Figure 17-41 Master/Slave timer exampleresents an overview of the trigger selection and the master mode
selection blocks.

Using one timer as prescaler for another

TIM1 TIM3

TS
MMS SMS
Clock
UEV

Master Slave CK_PSC


TRGO1 ITR0
mode mode
Prescaler Counter control control Prescaler Counter

Input
trigger
selection

Figure 17-41 Master/Slave timer example


For example, you can configure Timer 1 to act as a prescaler for Timer 3. Refer toFigure 17-41
Master/Slave timer example. To do this:
 Configure Timer 1 in master mode so that it outputs a periodic trigger signal on each update event UEV.
If you write MMS=010 in the TIM1_CR2 register, a rising edge is output on TRGO1 each time an update
event is generated.

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 To connect the TRGO1 output of Timer 1 to Timer 3, Timer 3 must be configured in slave mode using
ITR0 as internal trigger. You select this through the TS bits in the TIM3_SMCR register (writing
TS=000).
 Then the Timer2’s slave mode controller should be configured in external clock mode 1 (write SMS=111
in the TIM3_SMCR register). This causes Timer 3 to be clocked by the rising edge of the periodic Timer
1 trigger signal (which correspond to the timer 1 counter overflow).
 Finally both timers must be enabled by setting their respective CEN bits within their respective
TIMx_CR1 registers.
Note: If Ocx is selected on Timer 1 as trigger output (MMS=1xx), its rising edge is used to clock the counter
of timer 2.

Using one timer to enable another timer


In this example, we control the enable of Timer 3 with the output compare 1 of Timer 1. Refer to Figure
17-41 Master/Slave timer examplefor connections. Timer 3 counts on the divided internal clock only when
OC1REF of Timer 1 is high. Both counter clock frequencies are divided by 3 by the prescaler compared to
CK_INT (𝑓𝐶𝐾_𝐶𝑁𝑇 =𝑓𝐶𝐾_𝐶𝑁𝑇 /3).
 Configure Timer 1 master mode to send its Output Compare 1 Reference (OC1REF)
 Configure the Timer 1 OC1REF waveform (TIM1_CCMR1 register).
 Configure Timer 3 to get the input trigger from Timer 1 (TS=000 in the TIM3_SMCR register).
 Configure Timer 3 in gated mode (SMS=101 in TIM3_SMCR register).
 Enable Timer 3 by writing ‘1’ in the CEN bit (TIM3_CR1 register).
 Start Timer 1 by writing ‘1 in the CEN bit (TIM1_CR1 register).
Note:The counter 3 clock is not synchronized with counter 1, this mode only affects the Timer 3 counter
enable signal.

CK_CNT

TIM1-OC1REF

TIM1-CNT FC FD FE FF 00 01

TIM3-CNT 3045 3046 3047 3048

TIF

Write TIF=0

Figure 17-42 Gating timer 3 with OC1REF of timer 1


In the example in Figure 17-42, the Timer 3 counter and prescaler are not initialized before being started.
So they start counting from their current value. It is possible to start from a given value by resetting both
timers before starting Timer 1. You can then write any value you want in the timer counters. The timers can
easily be reset by software using the UG bit in the TIMx_EGR registers.
In the next example, we synchronize Timer 1 and Timer 3. Timer 1 is the master and starts from 0. Timer 3 is
the slave and starts from 0xE7. The prescaler ratio is the same for both timers. Timer 3 stops when Timer 1
is disabled by writing ‘0’ to the CEN bit in the TIM1_CR1 register:

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 Configure Timer 1 master mode to send its OC1REF as a trigger output (MMS=100, in the TIM1_CR2
register).
 Configure the Timer 1 OC1REF waveform (TIM1_CCMR1 register).
 Configure Timer 3 to get the input trigger from Timer 1 (TS=000 in the TIM3_SMCR register).
 Configure Timer 3 in gated mode (SMS=101 in TIM3_SMCR register).
 Reset Timer 1 by writing ‘1’ in UG bit (TIM1_EGR register).
 Reset Timer 3 by writing ‘1’ in UG bit (TIM3_EGR register).
 Initialize Timer 3 to 0xE7 by writing ‘0xE7’ in the timer 3 counter (TIM3_CNT).
 Enable Timer 3 by writing ‘1’ in the CEN bit (TIM3_CR1 register).
 Start Timer 1 by writing ‘1’ in the CEN bit (TIM1_CR1 register).
 Stop Timer 1 by writing ‘0’ in the CEN bit (TIM1_CR1 register).

CK_CNT

TIM1-CEN=CNT_EN

TIM1-CNT_INIT

TIM1-CNT 75 00 01 02

TIM3-CNT AB 00 E7 E8 E9

TIM3-CNT_INT

TIM3-write CNT

TIM3-TIF

Write TIF=0

Figure 17-43 Gating timer 3 with Enable of timer 1

Using one timer to start another timer


In this example, we set the enable of Timer 3 with the update event of Timer 1. Refer toFigure 17-41
Master/Slave timer example.Timer 3 starts counting from its current value (which can be nonzero) on the
divided internal clock as soon as the update event is generated by Timer 1. When Timer 3 receives the
trigger signal its CEN bit is automatically set and the counter counts until we write ‘0 to the CEN bit in the
TIM3_CR1 register. Both counter clock frequencies are divided by 3 by the prescaler compared to
CK_INT(𝑓𝐶𝐾_𝐶𝑁𝑇 =𝑓𝐶𝐾_𝐶𝑁𝑇 /3).
 Configure Timer 1 master mode to send its Update Event (UEV) as trigger output (MMS=010 in the
TIM1_CR2 register).
 Configure the Timer 1 period (TIM1_ARR registers).
 Configure Timer 3 to get the input trigger from Timer 1 (TS=000 in the TIM3_SMCR register).
 Configure Timer 3 in trigger mode (SMS=110 in TIM3_SMCR register).
 Start Timer 1 by writing ‘1’ in the CEN bit (TIM1_CR1 register).

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CK_CNT

TIM1-UEV

TIM1-CNT FD FE FF 00 01 02

TIM3-CNT 45 46 47 48

TIM3-CEN=CNT_EN

TIM3-TIF

Write TIF=0

Figure 17-44 Triggering timer 3 with update of timer 1


As in the previous example, you can initialize both counters before starting counting. Figure 17-45 shows
the behavior with the same configuration as in Figure 17-44 but in trigger mode instead of gated mode
(SMS=110 in the TIM3_SMCR register).

CK_CNT

TIM1-CEN=CNT_EN

TIM1-CNT_INIT

TIM1-CNT 75 00 01 02

TIM3-CNT CD 00 E7 E8 E9 EA

TIM3-CNT_INT

TIM3-write CNT

TIM3-TIF

Write TIF=0

Figure 17-45 Triggering timer 3 with Enable of timer 1


Using one timer as prescaler for another
For example, you can configure Timer 1 to act as a prescaler for Timer 3. Refer to Figure 17-41
Master/Slave timer example
 Configure Timer 1 in master mode so that it outputs a periodic trigger signal on each update event UEV.
(MMS=000 in the TIM1_CR2 register);
 Configure Timer1 period;
 Timer3 must be configured in slave mode using timer1 output as internal trigger. (TS=000 in the
TIM3_SMCR register);
 Then the Timer3’s slave mode controller should be configured in external clock mode 1(SMS=111 in the
TIM3_SMCR register);
 Set CEN=1 in the TIM3_CR1 register to enable timer3;
 Set CEN=1 in the TIM1_CR1 register to enable timer1.

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Starting 2 timers synchronously in response to an external


trigger
In this example, we set the enable of timer 1 when its TI1 input rises, and the enable of Timer 3 with the
enable of Timer 1. To ensure the counters are aligned, Timer 1 must be configured in Master/Slave mode
(slave with respect to TI1, master with respect to Timer 3):
 Configure Timer 1 master mode to send its Enable as trigger output (MMS=001 in the TIM1_CR2
register).
 Configure Timer 1 slave mode to get the input trigger from TI1 (TS=100 in the TIM1_SMCR register).
 Configure Timer 1 in trigger mode (SMS=110 in the TIM1_SMCR register).
 Configure the Timer 1 in Master/Slave mode by writing MSM=1 (TIM1_SMCR register).
 Configure Timer 3 to get the input trigger from Timer 1 (TS=000 in the TIM3_SMCR register).
 Configure Timer 3 in trigger mode (SMS=110 in the TIM3_SMCR register).
When a rising edge occurs on TI1 (Timer 1), both counters starts counting synchronously on the internal
clock and both TIF flags are set.
Note:In this example both timers are initialized before starting (by setting their respective UG bits). Both
counters starts from 0, but you can easily insert an offset between them by writing any of the counter
registers (TIMx_CNT). You can see that the master/slave mode insert a delay between CNT_EN and
CK_PSC on timer 1.

CK_CNT

TIM1-TI1

TIM1-CEN=CNT_EN

TIM1-CK_PSC

TIM1-CNT 00 01 02 03 04 05 06 07

TIM1-TIF

TIM3-CEN=CNT_EN

TIM3-CK_PSC

TIM3-CNT 00 01 02 03 04 05 06 07

TIM3-TIF

Figure 17-46 Triggering timer 1 and 3 with timer 1 TI1 input

17.3.16. Debug mode

When the microcontroller enters debug mode (ARM® Cortex®-M0 core – halted), the TIMx counter either
continues to work normally or stops, depending on DBG_TIMx_STOP configuration bit in DBGMCU module.

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17.4. TIM3 register map

The following table shows the TIM3 register map and reset values.
31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10
Address offset Name

0
CMS[1:0]
CKD[1:0]

ARPE

UDIS
OPM

URS

CEN
DIR
TIM3_CR1
–

–
0x00

Reset x x x x x x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0

CCDS
TI1S
TIM3_CR2 MMS[2:0]
–

–
0x04

Reset x x x x x x x x x x x x x x x x x x x x x x x x 0 0 0 0 0 x x x

ETPS[1:0]

MSM
ECE
ETP
TIM3_SMCR ETF[3:0] TS[2:0] SMS[2:0]
–

–
0x08

Reset x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 x 0 0 0

CC4DE

CC3DE

CC2DE

CC1DE

CC4IE

CC3IE

CC2IE

CC1IE
UDE
TDE

UIE
TIE
TIM3_DIER
–

–
0x0C

Reset x x x x x x x x x x x x x x x x x 0 x 0 0 0 0 0 x 0 x 0 0 0 0 0

CC4OF

CC3OF

CC2OF

CC1OF

CC4IF

CC3IF

CC2IF

CC1IF

UIF
TIF
TIM3_SR
–

–
0x10

Reset x x x x x x x x x x x x x x x x x x x 0 0 0 0 x x 0 x 0 0 0 0 0

CC4G

CC3G

CC2G

CC1G
TG

UG
TIM3_EGR
–

–
0x14

Reset x x x x x x x x x x x x x x x x x x x x x x x x x 0 x 0 0 0 0 0
CC2S[1:0]

CC1S[1:0]
OC2CE

TIM3_CCMR
CC2PE

CC2FE

CC1CE

CC1PE

CC1FE
1 OC2M[2:0] OC1M[2:0]
–

(output mode)

Reset x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x18
CC2S[1:0]

CC1S[1:0]
IC2F[3:0]

IC1F[3:0]

TIM3_CCMR
IC2PSC IC1PSC
1
–

[1:0] [1:0]
(input mode)

Reset x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

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CC4S[1:0]

CC3S[1:0]
OC4CE
TIM3_CCMR

CC4PE

CC4FE

CC3CE

CC3PE

CC3FE
2 OC4M[2:0] OC3M[2:0]

–
(output mode)

Reset x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x1C

CC4S[1:0]

CC3S[1:0]
IC4F[3:0]

IC3F[3:0]
TIM3_CCMR
IC4PSC IC3PSC
2

–
[1:0] [1:0]
(input mode)

Reset x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CC3NP

CC2NP

CC1NP
CC4P

CC4E

CC3P

CC3E

CC2P

CC2E

CC1P

CC1E
TIM3_CCER
–

–
0x20

Reset x x x x x x x x x x x x x x x x x x 0 0 0 x 0 0 0 x 0 0 0 x 0 0

TIM3_CNT CNT[15:0]
–

–
0x24

Reset x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TIM3_PSC PSC[15:0]
–

–
0x28

Reset x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TIM3_ARR ARR[15:0]
–

–
0x2C

Reset x x x x x x x x x x x x x x x x 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

TIM3_CCR1 CCR1[15:0]
–

0x34

Reset x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TIM3_CCR2 CCR2[15:0]
–

0x38

Reset x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TIM3_CCR3 CCR3[15:0]
–

0x3C

Reset x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TIM3_CCR4 CCR4[15:0]
–

0x40

Reset x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TIM3_DCR DBL[4:0] DBA[4:0]


–

0x48

Reset x x x x x x x x x x x x x x x x x x x 0 0 0 0 0 x x x 0 0 0 0 0

TIM3_DMAR DMAB[15:0]
–

0x4C

Reset x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

17.4.1. TIM3 control register 1(TIM3_CR1)

Address offset: 0x00


Reset value: 0x0000
bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0

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15:8 — CKD[1:0]
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RW RW
7:0 ARPE CMS[1:0] DIR OPM URS UDIS CEN
type RW RW RW RW RW RW RW RW

Bit Name Function


31:10 NA Reserved, undefined
9:8 CKD[1:0] Clock division
This bit-field indicates the division ratio between the timer clock (CK_INT)
frequency and sampling clock used by the digital filters (ETR, Tix),
00: 𝑡𝐷𝑇𝑆 = 𝑡𝐶𝐾_𝐼𝑁𝑇
01: 𝑡𝐷𝑇𝑆 = 2 ∗ 𝑡𝐶𝐾_𝐼𝑁𝑇
10: 𝑡𝐷𝑇𝑆 = 4 ∗ 𝑡𝐶𝐾_𝐼𝑁𝑇
11: Reserved, not allowed
7 ARPE Auto-reload preload enable
0: TIMx_ARR register is not buffered. It can be written directly
1: TIMx_ARR register is buffered
6:5 CMS[1:0] Center-aligned mode selection
00: Edge-aligned mode. The counter counts up or down depending on the
direction bit (DIR).
01: Center-aligned mode 1. The counter counts up and down alternatively.
Output compare interrupt flags of channels configured in output (CCxS=00 in
TIMx_CCMRx register) are set only when the counter is counting down.
10: Center-aligned mode 2. The counter counts up and down alternatively.
Output compare interrupt flags of channels configured in output (CCxS=00 in
TIMx_CCMRx register) are set only when the counter is counting up.
11: Center-aligned mode 3. The counter counts up and down alternatively.
Output compare interrupt flags of channels configured in output (CCxS=00 in
TIMx_CCMRx register) are set both when the counter is counting up or
down.
Note: It is not allowed to switch from edge-aligned mode to center-aligned
mode as long as the counter is enabled (CEN=1)
4 DIR Direction
0: Counter used as upcounter
1: Counter used as downcounter
Note: This bit is read only when the timer is configured in Center-aligned
mode or Encoder mode.
3 OPM One-pulse mode
0: Counter is not stopped at update event
1: Counter stops counting at the next update event (clearing the bit CEN)
2 URS Update request source
This bit is set and cleared by software to select the UEV event sources.
0: if UDIS allows to generate an update event, Any of the following events
generate an update interrupt or DMA request if enabled.
− Counter overflow/underflow
− Setting the UG bit
− Update generation by reset trigger

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1: Only counter overflow/underflow generates an update interrupt or DMA


request if enabled.
1 UDIS Update disable
This bit is set and cleared by software to enable/disable UEV event
generation.
0: UEV enabled. The Update (UEV) event is generated by one of the
following events:
− Counter overflow/underflow
− Setting the UG bit
− Update generation by reset trigger
1: UEV disabled. The Update event is not generated, shadow registers keep
their value (ARR, PSC, CCRx). However the counter and the prescaler are
reinitialized if the UG bit is set or trigger evnent occurred in reset mode
0 CEN Counter enable
0: Counter disabled
1: Counter enabled
Note: External clock, gated mode and encoder mode can work only if the
CEN bit has been previously set by software. However trigger mode can set
the CEN bit automatically by hardware.

17.4.2. TIM3 control register 2(TIM3_CR2)

Address offset: 0x04


Reset value: 0x0000
bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
7:0 TI1S MMS[2:0] CCDS —
type RW RW RW RW RW RO-0 RO-0 RO-0

Bit Name Function


31:8 NA Reserved, undefined
7 TI1S TI1 selection
0:CC1 pin is connected to TI1 input (digital filter input)
1: The CC1、CC2、CC3 and CC4 pins are connected to the TI1 input (XOR
combination)
6:4 MMS[2:0] Master mode selection
These bits allow to select the information to be sent in master mode to slave
timers for synchronization (TRGO). The combination is as follows:
000: Reset – the UG bit from the TIMx_EGR register is used as trigger
output (TRGO). If the reset is generated by the trigger input (slave mode

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controller configured in reset mode) then the signal on TRGO is delayed


compared to the actual reset.
001: Enable – the Counter enable signal, CNT_EN, is used as trigger output
(TRGO). It is useful to start several timers at the same time or to control a
window in which a slave timer is enabled. The Counter Enable signal is
generated by a logic OR between CEN control bit and the trigger input when
configured in gated mode. When the Counter Enable signal is controlled by
the trigger input, there is a delay on TRGO, except if the master/slave mode
is selected (see the MSM bit description in TIMx_SMCR register).
010: Update – The update event is selected as trigger output (TRGO). For
instance a master timer can then be used as a prescaler for a slave timer..
011: Compare Pulse – The trigger output send a positive pulse when the
CC1IF flag is to be set (even if it was already high), as soon as a capture or
a compare match occurred.
(TRGO)
100: Compare – OC1REF signal is used as trigger output (TRGO)
101: Compare – OC2REF signal is used as trigger output (TRGO)
110: Compare – OC3REF signal is used as trigger output (TRGO)
111: Compare – OC4REF signal is used as trigger output (TRGO)
3 CCDS Capture/compare DMA selection
0: CCx DMA request sent when CCx event occurs
1: CCx DMA requests sent when update event occurs
2:0 NA Reserved, undefined

17.4.3. TIM3 slave mode control register(TIM3_SMCR)

Address offset: 0x08


Reset value: 0x0000
bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 ETP ECE ETPS[1:0] ETF[3:0]
type RW RW RW RW RW RW RW RW
7:0 MSM TS[2:0] OCCS SMS[2:0]
type RW RW RW RW RW RW RW RW

Bit Name Function


31:16 NA Reserved, undefined
15 ETP External trigger polarity
External trigger polarity This bit selects whether ETR or reverse of ETR is
used for trigger operations
0: ETR is noninverted, active at high level or rising edge
1: ETR is inverted, active at low level or falling edge

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14 ECE External clock enable


This bit enables External clock mode 2.
0: External clock mode 2 disabled
1: External clock mode 2 enabled. The counter is clocked by any active edge
on the ETRF signal.
1: Setting the ECE bit has the same effect as selecting external clock mode
1 with TRGI connected to ETRF (SMS=111 and TS=111).
2: It is possible to simultaneously use external clock mode 2 with the
following slave modes: reset mode, gated mode and trigger mode.
Nevertheless, TRGI must not be connected to ETRF in this case (TS bits
must not be 111).
3: If external clock mode 1 and external clock mode 2 are enabled at the
same time, the external clock input is ETRF.
13:12 ETPS[1:0] External trigger prescaler
External trigger signal ETRP frequency must be at most 1/4 of CK_INT
frequency. A prescaler can be enabled to reduce ETRP frequency. It is
useful when inputting fast external clocks.
00: Prescaler OFF
01: ETRP frequency divided by 2
10: ETRP frequency divided by 4
11: ETRP frequency divided by 8
11:8 ETF[3:0] External trigger filter
This bit-field defines the frequency used to sample ETRP signal and the
length of the digital filter applied to ETRP. The digital filter is made of an
event counter in which N consecutive events are needed to validate a
transition on the output:
0000: No filter, sampling is done at fSAMPLING = fDTS
0001: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐶𝐾_𝐼𝑁𝑇 , N=2
0010: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐶𝐾_𝐼𝑁𝑇 , N=4
0011: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐶𝐾_𝐼𝑁𝑇 , N=8
0100: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐷𝑇𝑆 /2, N=6
0101: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐷𝑇𝑆 /2, N=8
0110: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐷𝑇𝑆 /4, N=6
0111: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐷𝑇𝑆 /4, N=8
1000: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐷𝑇𝑆 /8, N=6
1001: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐷𝑇𝑆 /8, N=8
1010: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐷𝑇𝑆 /16, N=5
1011: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐷𝑇𝑆 /16, N=6
1100: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐷𝑇𝑆 /16, N=8
1101: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐷𝑇𝑆 /32, N=5
1110: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐷𝑇𝑆 /32, N=6
1111: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐷𝑇𝑆 /32, N=8
7 MSM Master/Slave mode
0: No action
1: The effect of an event on the trigger input (TRGI) is delayed to allow a
perfect synchronization between the current timer and its slaves (through
TRGO). It is useful if we want to synchronize several timers on a single
external event.
6:4 TS[2:0] Trigger selection

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This bit-field selects the trigger input to be used to synchronize the counter.
000: Internal Trigger 0 (ITR0)
001: Reserved
010: Internal Trigger 2 (ITR2)
011: Internal Trigger 3 (ITR3)
100: TI1 Edge Detector (TI1F_ED)
101: Filtered Timer Input 1 (TI1FP1)
110: Filtered Timer Input 2 (TI2FP2)
111: External Trigger input (ETRF)
Note: These bits must be changed only when they are not used (e.g. when
SMS=000) to avoid wrong edge detections at the transition.
3 OCCS OCREF clear selection.
This bit is used to select the OCREF clear source.
0:OCREF_CLR_INT is connected to the OCREF_CLR input
1: OCREF_CLR_INT is connected to ETRF
2:0 SMS[2:0] Slave mode selection
When external signals are selected the active edge of the trigger signal
(TRGI) is linked to the polarity selected on the external input (see Input
Control register and Control Register description.
000: clock/trigger controller disabled
–if CEN = ‘1’ then the prescaler is clocked directly by the internal clock.
001: Encoder mode 1
–Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
010: Encoder mode 2
–Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
011: Encoder mode 3
–Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on
the level of the other input.
100: Reset Mode
–Rising edge of the selected trigger input (TRGI) reinitializes the counter
and generates an update of the registers
101: Gated Mode
–The counter clock is enabled when the trigger input (TRGI) is high. The
counter stops (but is not reset) as soon as the trigger becomes low. Both
start and stop of the counter are controlled.
110: Trigger Mode
–The counter starts at a rising edge of the trigger TRGI (but it is not reset).
Only the start of the counter is controlled
111: External Clock Mode 1
–Rising edges of the selected trigger (TRGI) clock the counter.
Note: The gated mode must not be used if TI1F_ED is selected as the
trigger input (TS=100). Indeed, TI1F_ED outputs 1 pulse for each transition
on TI1F, whereas the gated mode checks the level of the trigger signal.

Table 17-2 TIM3 internal trigger connection


Slave TIM ITR0(TS=000) ITR2(TS=010) ITR3(TS=011)
TIM3 TIM1 TIM15 TIM14

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17.4.4. TIM3 DMA/Interrupt enable register(TIM3_DIER)

Address offset: 0x0C


Reset value: 0x0000
bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 — TDE — CC4DE CC3DE CC2DE CC1DE UDE
type RO-0 RW RO-0 RW RW RW RW RW
7:0 — TIE — CC4IE CC3IE CC2IE CC1IE UIE
type RO-0 RW RO-0 RW RW RW RW RW

Bit Name Function


31:15 NA Reserved, undefined
14 TDE Trigger DMA request enable
0: Trigger DMA request disabled.
1: Trigger DMA request enabled
13 NA Reserved, undefined
12 CC4DE Capture/Compare 4 DMA request enable
0: CC4 DMA request disabled.
1: CC4 DMA request enabled.
11 CC3DE Capture/Compare 3 DMA request enable
0: CC3 DMA request disabled.
1: CC3 DMA request enabled.
10 CC2DE Capture/Compare 2 DMA request enable
0: CC2 DMA request disabled.
1: CC2 DMA request enabled.
9 CC1DE Capture/Compare 1 DMA request enable
0: CC1 DMA request disabled.
1: CC1 DMA request enabled.
8 UDE Update DMA request enable
0: Update DMA request disabled.
1: Update DMA request enabled.
7 NA Reserved, undefined
6 TIE Trigger interrupt enable
0: Trigger interrupt disabled.
1: Trigger interrupt enabled.
5 NA Reserved, undefined
4 CC4IE Capture/Compare 4 interrupt enable
0: CC4 interrupt disabled.

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1: CC4 interrupt enabled.


3 CC3IE Capture/Compare 3 interrupt enable
0: CC3 interrupt disabled
1: CC3 interrupt enabled
2 CC2IE Capture/Compare 2 interrupt enable
0: CC2 interrupt disabled
1: CC2 interrupt enabled
1 CC1IE Capture/Compare 1 interrupt enable
0: CC1 interrupt disabled
1: CC1 interrupt enabled
0 UIE Update interrupt enable
0: Update interrupt disabled
1: Update interrupt enabled

17.4.5. TIM3 status register(TIM3_SR)

Address offset: 0x10


Reset value: 0x0000
bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 — CC4OF CC3OF CC2OF CC1OF —
type RO-0 RO-0 RO-0 RC_W0 RC_W0 RC_W0 RC_W0 RO-0
7:0 Reserved TIF Reserved CC4IF CC3IF CC2IF CC1IF UIF
type RO-0 RC_W0 RO-0 RC_W0 RC_W0 RC_W0 RC_W0 RC_W0

Bit Name Function


31:13 NA Reserved, undefined
12 CC4OF Capture/Compare 4 overcapture flag Refer to CC1OF description
11 CC3OF Capture/Compare 3 overcapture flag Refer to CC1OF description
10 CC2OF Capture/compare 2 overcapture flag Refer to CC1OF description
9 CC1OF Capture/Compare 1 overcapture flag
This flag is set by hardware only when the corresponding channel is
configured in input capture mode. It is cleared by software by writing it to ‘0.
0: No overcapture has been detected
1: The counter value has been captured in TIMx_CCR1 register while CC1IF
flag was already set
8 NA Reserved, undefined
7 NA Reserved, undefined
6 TIF Trigger interrupt flag
This flag is set by hardware on trigger event (active edge detected on TRGI

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input when the slave mode controller is enabled in all modes but gated
mode. It is set when the counter starts or stops when gated mode is
selected. It is cleared by software.
0: No trigger event occurred
1: Trigger interrupt pending
5 NA Reserved, undefined
4 CC4IF Capture/Compare 4 interrupt flag Refer to CC1IF description
3 CC3IF Capture/Compare 3 interrupt flag Refer to CC1IF description
2 CC2IF Capture/Compare 2 interrupt flag Refer to CC1IF description
1 CC1IF Capture/compare 1 interrupt flag
If channel CC1 is configured as output:
This flag is set by hardware when the counter matches the compare value,
with some exception in center-aligned mode (refer to the CMS bits in the
TIMx_CR1 register description). It is cleared by software.
0: No match
1: The content of the counter TIMx_CNT matches the content of the
TIMx_CCR1 register. When the contents of TIMx_CCR1 are greater than
the contents of TIMx_ARR, the CC1IF bit goes high on the counter overflow
(in upcounting and up/down-counting modes) or underflow (in downcounting
mode)
If channel CC1 is configured as input:
This bit is set by hardware on a capture. It is cleared by software or by
reading the TIMx_CCR1 register.
0: No input capture occurred
1: The counter value has been captured in TIMx_CCR1 register (An edge
has been detected on IC1 which matches the selected polarity)
0 UIF Update interrupt flag
This bit is set by hardware on an update event. It is cleared by software.
0: No update occurred.
1: Update interrupt pending.
− At overflow or underflow and if UDIS=0 in the TIMx_CR1 register;
− When CNT is reinitialized by software using the UG bit in TIMx_EGR
register, if URS=0 and UDIS=0 in the TIMx_CR1 register.
− When CNT is reinitialized by a trigger event (refer to the synchro control
register description), if URS=0 and UDIS=0 in the TIMx_CR1 register.

17.4.6. TIM3 event generation register(TIM3_EGR)

Address offset: 0x14


Reset value: 0x0000
bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 —

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type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0


7:0 — TG — CC4G CC3G CC2G CC1G UG
type RO-0 W RO-0 W W W W W

Bit Name Function


31:7 NA Reserved, undefined
6 TG Trigger generation
This bit is set by software in order to generate an event, it is automatically
cleared by hardware.
0: No action
1: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer
can occur if enabled.
5 NA Reserved, undefined
4 CC4G Capture/compare 4 generation Refer to CC1G description
3 CC3G Capture/compare 3 generation Refer to CC1G description
2 CC2G Capture/compare 2 generation Refer to CC1G description
1 CC1G Capture/compare 1 generation
This bit is set by software in order to generate an event, it is automatically
cleared by hardware.
0: No action
1: A capture/compare event is generated on channel 1:
If channel CC1 is configured as output:
CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled.
If channel CC1 is configured as input:
The current value of the counter is captured in TIMx_CCR1 register. The
CC1IF flag is set, the corresponding interrupt or DMA request is sent if
enabled. The CC1OF flag is set if the CC1IF flag was already high.
0 UG Update generation
This bit can be set by software, it is automatically cleared by hardware.
0: No action
1: Re-initialize the counter and generates an update of the registers. Note
that the prescaler counter is cleared too (anyway the prescaler ratio is not
affected). The counter is cleared if the center-aligned mode is selected or if
DIR=0 (upcounting), else it takes the auto-reload value (TIMx_ARR) if
DIR=1 (downcounting).

17.4.7. TIM3 capture/compare mode register 1(TIM3_CCMR1)

Address offset: 0x18


Reset value: 0x0000
The channels can be used in input (capture mode) or in output (compare mode). The direction of a channel
is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different
function in input and in output mode. For a given bit, Ocxx describes its function when the channel is
configured in output, Icxx describes its function when the channel is configured in input. So you must take
care that the same bit can have a different meaning for the input stage and for the output stage.

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Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0


31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
OC2CE OC2M[2:0] OC2PE OC2FE
15:8 CC2S[1:0]
IC2F[3:0] IC2PSC[1:0]
type RW RW RW RW RW RW RW RW
OC1CE OC1M[2:0] OC1PE OC1FE
7:0 CC1S[1:0]
IC1F[3:0] IC1PSC[1:0]
type RW RW RW RW RW RW RW RW

Output compare mode:


Bit Name Function
31:16 NA Reserved, undefined
15 OC2CE Output compare 2 clear enable
14:12 OC2M[2:0] Output compare 2 mode
11 OC2PE Output compare 2 preload enable
10 OC2FE Output compare 2 fast enable
9:8 CC2S Capture/Compare 2 selection
This bit-field defines the direction of the channel (input/output) as well as the
used input.
00: CC2 channel is configured as output
01: CC2 channel is configured as input, IC2 is mapped on TI2
10: CC2 channel is configured as input, IC2 is mapped on TI1
11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode
is working only if an internal trigger input is selected through the TS bit
(TIMx_SMCR register)
Note: CC2S bits are writable only when the channel is OFF
(CC2E=0,CC2NE=0 in the TIMx_CCER and and have been updated)
7 OC1CE Output compare 1 clear enable
OC1CE: Output Compare 1 Clear Enable
0: OC1Ref is not affected by the ETRF input
1: OC1Ref is cleared as soon as a High level is detected on ETRF input
6:4 OC1M[2:0] Output compare 1 mode
These bits define the behavior of the output reference signal OC1REF from
which OC1 and OC1N are derived. OC1REF is active high whereas OC1
and OC1N active level depends on CC1P and CC1NP bits.
000: Frozen .The comparison between the output compare register
TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs.
001: Set channel 1 to active level on match. OC1REF signal is forced high
when the counter TIMx_CNT matches the capture/compare register 1
(TIMx_CCR1).
010: Set channel 1 to inactive level on match. OC1REF signal is forced low
when the counter TIMx_CNT matches the capture/compare register 1
(TIMx_CCR1).

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011: Toggle – OC1REF toggles when TIMx_CNT=TIMx_CCR1.


100: Force inactive level – OC1REF is forced low.
101: Force active level – OC1REF is forced high.
110: PWM mode 1
－ In upcounting, channel 1 is active as long as TIMx_CNT<TIMx_CCR1
else inactive.
－ In downcounting, channel 1 is inactive (OC1REF=‘0) as long as
TIMx_CNT>TIMx_CCR1 else active (OC1REF=1).
111: PWM mode 2
－ In upcounting, channel 1 is inactive as long as TIMx_CNT<TIMx_CCR1
else active.
－ In downcounting, channel 1 is active as long as TIMx_CNT>TIMx_CCR1
else inactive.
Note1: These bits can not be modified as long as LOCK level 3 has been
programmed (LOCK bits in TIMx_BDTR register) and CC1S=00 (the
channel is configured in output).
Note2:In PWM mode 1 or 2, the OCREF level changes only when the result
of the comparison changes or when the output compare mode switches from
“frozen” mode to “PWM” mode.
Note3: On channels having a complementary output, this bit field is
preloaded. If the CCPC bit is set in the TIMx_CR2 register then the OC1M
active bits take the new value from the preloaded bits only when a COM
event is generated.
3 OC1PE Output compare 1 preload enable
0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at
anytime, the new value is taken in account immediately.
1: Preload register on TIMx_CCR1 enabled. Read/Write operations access
the preload register. TIMx_CCR1 preload value is loaded in the active
register at each update event.
Note1: These bits can not be modified as long as LOCK level 3 has been
programmed (LOCK bits in TIMx_BDTR register) and CC1S=00 (the
channel is configured in output).
Note 2: The PWM mode can be used without validating the preload register
only in onepulse mode (OPM bit set in TIMx_CR1 register). Else the
behavior is not guaranteed.
2 OC1FE Output compare 1 fast enable
This bit is used to accelerate the effect of an event on the trigger in input on
the CC output.
0: CC1 behaves normally depending on counter and CCR1 values even
when the trigger is ON. The minimum delay to activate CC1 output when an
edge occurs on the trigger input is 5 clock cycles.
1: An active edge on the trigger input acts like a compare match on CC1
output. Then, OC is set to the compare level independently from the result of
the comparison. Delay to sample the trigger input and to activate CC1 output
is reduced to 3 clock cycles.
Note:OCFE acts only if the channel is configured in PWM1 or PWM2 mode.
1:0 CC1S[1:0] Capture/Compare 1 selection
This bit-field defines the direction of the channel (input/output) as well as the
used input.

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00: CC1 channel is configured as output.


01: CC1 channel is configured as input, IC1 is mapped on TI1.
10: CC1 channel is configured as input, IC1 is mapped on TI2.
11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode
is working only if an internal trigger input is selected through TS bit
(TIMx_SMCR register)
Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in
TIMx_CCER).

Input capture mode:


Bit Name Function
31:16 NA Reserved, undefined
15:12 IC2F[3:0] Input capture 2 filter
11:10 IC2PSC[1:0] Input capture 2 prescaler
9:8 CC2S[1:0] Capture/compare 2 selection
This bit-field defines the direction of the channel (input/output) as well as the
used input.
00: CC2 channel is configured as output.
01: CC2 channel is configured as input, IC2 is mapped on TI2.
10: CC2 channel is configured as input, IC2 is mapped on TI1.
11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode
is working only if an internal trigger input is selected through TS bit
(TIMx_SMCR register)
Note: CC2S bits are writable only when the channel is OFF
(CC2E=0,CC2NE=0 in the TIMx_CCER and and have been updated)
7:4 IC1F[3:0] Input capture 1 filter
This bit-field defines the frequency used to sample TI1 input and the length
of the digital filter applied to TI1. The digital filter is made of an event counter
in which N consecutive events are needed to validate a transition on the
output:
0000: No filter, sampling is done at 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐶𝐾_𝐼𝑁𝑇
0001: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐶𝐾_𝐼𝑁𝑇 , N=2
0010: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐶𝐾_𝐼𝑁𝑇 , N=4
0011: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐶𝐾_𝐼𝑁𝑇 , N=8
0100: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐷𝑇𝑆 /2, N=6
0101: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐷𝑇𝑆 /2, N=8
0110: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐷𝑇𝑆 /4, N=6
0111: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐷𝑇𝑆 /4, N=8
1000: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐷𝑇𝑆 /8, N=6
1001: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐷𝑇𝑆 /8, N=8
1010: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐷𝑇𝑆 /16, N=5
1011: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐷𝑇𝑆 /16, N=6
1100: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐷𝑇𝑆 /16, N=8
1101: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐷𝑇𝑆 /32, N=5
1110: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐷𝑇𝑆 /32, N=6
1111: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐷𝑇𝑆 /32, N=8
3:2 IC1PSC[1:0] Input capture 1 prescaler
This bit-field defines the ratio of the prescaler acting on CC1 input (IC1).

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The prescaler is reset as soon as CC1E=0 (TIMx_CCER register).


00: no prescaler, capture is done each time an edge is detected on the
capture input
01: capture is done once every 2 events
10: capture is done once every 4 events
11: capture is done once every 8 events
1:0 CC1S[1:0] Capture/Compare 1 selection
This bit-field defines the direction of the channel (input/output) as well as the
used input.
00: CC1 channel is configured as output
01: CC1 channel is configured as input, IC1 is mapped on TI1
10: CC1 channel is configured as input, IC1 is mapped on TI2
11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode
is working only if an internal trigger input is selected through TS bit
(TIMx_SMCR register)
Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in
TIMx_CCER).

17.4.8. TIM3 capture/compare mode register 2(TIM3_CCMR2)

Address offset: 0x1C


Reset value: 0x0000
Refer to the above CCMR1 register description.
Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
OC4CE OC4M[2:0] OC4PE OC4FE
15:8 CC4S[1:0]
IC4F[3:0] IC4PSC[1:0]
type RW RW RW RW RW RW RW RW
OC3CE OC3M[2:0] OC3PE OC3FE
7:0 CC3S[1:0]
IC3F[3:0] IC3PSC[1:0]
type RW RW RW RW RW RW RW RW

Output compare mode:


Bit Name Function
31:16 NA Reserved, undefined
15 OC4CE Output compare 4 clear enable
14:12 OC4M[2:0] Output compare 4 mode
11 OC4PE Output compare 4 preload enable
10 OC4FE Output compare 4 fast enable
9:8 CC4S Capture/Compare 4 selection
This bit-field defines the direction of the channel (input/output) as well as the

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used input.
00: CC4 channel is configured as output
01: CC4 channel is configured as input, IC4 is mapped on TI4
10: CC4 channel is configured as input, IC4 is mapped on TI3
11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode
is working only if an internal trigger input is selected through TS bit
(TIMx_SMCR register)
Note: CC4S bits are writable only when the channel is OFF (CC4E=0 in the
TIMx_CCER and and have been updated)
7 OC3CE Output compare 3 clear enable
6:4 OC3M[2:0] Output compare 3 mode
3 OC3PE Output compare 3 preload enable
2 OC3FE Output compare 3 fast enable
1:0 CC3S Capture/Compare 3 selection
This bit-field defines the direction of the channel (input/output) as well as the
used input.
00: CC3 channel is configured as output
01: CC3 channel is configured as input, IC3 is mapped on TI3
10: CC3 channel is configured as input, IC3 is mapped on TI4
11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode
is working only if an internal trigger input is selected through TS bit
(TIMx_SMCR register)
Note: CC3S bits are writable only when the channel is OFF
(CC3E=0,CC3NE=0 in the TIMx_CCER and and have been updated)

Input capture mode:


Bit Name Function
31:16 NA Reserved, undefined
15:12 IC4F[3:0] Input capture 4 filter
11:10 IC4PSC[1:0] Input capture 4 prescaler
9:8 CC4S[1:0] Capture/Compare 4 selection
This bit-field defines the direction of the channel (input/output) as well as the
used input.
00: CC4 channel is configured as output
01: CC4 channel is configured as input, IC4 is mapped on TI4
10: CC4 channel is configured as input, IC4 is mapped on TI3
11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode
is working only if an internal trigger input is selected through TS bit
(TIMx_SMCR register)
Note: CC4S bits are writable only when the channel is OFF (CC4E=0 in the
TIMx_CCER and and have been updated)
7:4 IC3F[3:0] Input capture 3 filter
3:2 IC3PSC[1:0] Input capture 3 prescaler
1:0 CC3S[1:0] Capture/Compare 3 selection
This bit-field defines the direction of the channel (input/output) as well as the
used input.
00: CC3 channel is configured as output

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01: CC3 channel is configured as input, IC3 is mapped on TI3


10: CC3 channel is configured as input, IC3 is mapped on TI4
11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode
is working only if an internal trigger input is selected through TS bit
(TIMx_SMCR register)
Note: CC3S bits are writable only when the channel is OFF
(CC3E=0,CC3NE=0 in the TIMx_CCER and and have been updated)

17.4.9. TIM3 capture/compare enable register(TIM3_CCER)

Address offset: 0x20


Reset value: 0x0000
bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 — CC4P CC4E CC3NP — CC3P CC3E
type RO-0 RO-0 RW RW RW RO-0 RW RW
7:0 CC2NP — CC2P CC2E CC1NP — CC1P CC1E
type RW RO-0 RW RW RW RO-0 RW RW

Bit Name Function


31:14 NA Reserved, undefined
13 CC4P Capture/Compare 4 output Polarity. Refer to CC1P description
12 CC4E Capture/Compare 4 output enable. Refer to CC1E description
11 CC3NP Capture/Compare 3 output Polarity. Refer to CC1NP description
10 NA Reserved, undefined
9 CC3P Capture/Compare 3 output Polarity. Refer to CC1P description
8 CC3E Capture/Compare 3 output enable. Refer to CC1E description
7 CC2NP Capture/Compare 2 output Polarity. Refer to CC1NP description
6 NA Reserved, undefined
5 CC2P Capture/Compare 2 output Polarity. Refer to CC1P description
4 CC2E Capture/Compare 2 output enable. Refer to CC1E description
3 CC1NP Capture/Compare 1 output Polarity.
CC1 channel configured as output:
0: OC1 active high
1: OC1 active low
CC1 channel configured as input:
This bit is used in conjunction with CC1P to define TI1FP1/TI2FP1 polarity.
Refer to CC1P description.
Note1: This bit is not writable as soon as LOCK level 2 or 3 has been
programmed (LOCK bits in TIMx_BDTR register) and CC1S=”00” (the
channel is configured in output).

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Note2: On channels having a complementary output, this bit is preloaded. If


the CCPC bit is set in the TIMx_CR2 register then the CC1NP active bit
takes the new value from the preloaded bits only when a Commutation event
is generated.
2 NA Reserved, undefined
1 CC1P Capture/Compare 1 output Polarity.
CC1 channel configured as output:
0: OC1 active high
1: OC1 active low
CC1 channel configured as input:
CC1NP/CC1P bits select TI1FP1 and TI2FP1 polarity for trigger or capture
operations.
00: noninverted/rising edge
Circuit is sensitive to TixFP1 rising edge (capture, trigger in reset, external clock
or trigger mode), TixFP1 is not inverted (in gated mode, encoder mode)..
01: inverted/falling edge
Circuit is sensitive to TixFP1 falling edge (capture, trigger in reset, external
clock or trigger mode), TixFP1 is inverted (gated mode, encoder mode).
10: reserved
11: noninverted/both edges
Circuit is sensitive to both TixFP1 rising and falling edges (capture, trigger in
reset, external clock or trigger mode), TixFP1 is not inverted(gated mode,
encoder mode)
Note1: This bit is not writable as soon as LOCK level 2 or 3 has been
programmed (LOCK bits in TIMx_BDTR register).
Note2: This bit is not writable as soon as LOCK level 2 or 3 has been
programmed (LOCK bits in TIMx_BDTR register).
0 CC1E Capture/Compare 1 output enable
CC1 channel configured as output:
0: Off
－ OC1 is not active, OC1 level is then function of MOE, OSSI, OSSR,
OIS1, OIS1N and CC1NE bits.
1: On
－ OC1 signal is output on the corresponding output pin depending on
MOE, OSSI, OSSR, OIS1, OIS1N and CC1NE bits.
CC1 channel configured as input:
This bit determines if a capture of the counter value can actually be done
into the input capture/compare register 1 (TIMx_CCR1) or not.
0: Capture disabled
1: Capture enabled
Note: On channels having a complementary output, this bit is preloaded. If
the CCPC bit is set in the TIMx_CR2 register then the CC1E active bit takes
the new value from the preloaded bits only when a Commutation event is
generated.

Table 17-3 Output control bit for standard Ocx channels


CcxE bit Ocx output state
0 Output Disabled(Ocx=0, Ocx_EN=0)

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1 Ocx=OCxREF + Polarity, Ocx_EN=1


Note:The state of the external IO pins connected to the standard Ocx channels depends on the Ocx channel
state and the GPIO registers.

17.4.10. TIM3 counter(TIM3_CNT)

Address offset: 0x24


Reset value: 0x0000
bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 CNT[15:8]
type RW RW RW RW RW RW RW RW
7:0 CNT[7:0]
type RW RW RW RW RW RW RW RW

Bit Name Function


31:16 NA Reserved, undefined
15:0 CNT[15:0] Low counter value

17.4.11. TIM3 prescaler(TIM3_PSC)

Address offset: 0x28


Reset value: 0x0000
bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 PSC[15:8]
type RW RW RW RW RW RW RW RW
7:0 PSC[7:0]
type RW RW RW RW RW RW RW RW

Bit Name Function


31:16 NA Reserved, undefined
15:0 PSC[15:0] Prescaler value
The counter clock frequency CK_CNT is equal to 𝑓𝐶𝐾_𝑃𝑆𝐶 /(PSC[15:0]+1).
PSC contains the value to be loaded in the active prescaler register at each
update event.

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17.4.12. TIM3 auto-reload register(TIM3_ARR)

Address offset: 0x2C


Reset value: 0x0000
bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 ARR[15:8]
type RW RW RW RW RW RW RW RW
7:0 ARR[7:0]
type RW RW RW RW RW RW RW RW

Bit Name Function


31:16 NA Reserved, undefined
15:0 ARR[15:0] Low Auto-reload value
ARR is the value to be loaded in the actual auto-reload register.
Refer to Section 17.3.1: Time-base unit for more details about ARR update
and behavior.
The counter is blocked while the auto-reload value is null.

17.4.13. TIM3 capture /compare register 1(TIM3_CCR1)

Address offset: 0x34


Reset value: 0x0000
bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 CCR1[15:8]
type RW RW RW RW RW RW RW RW
7:0 CCR1[7:0]
type RW RW RW RW RW RW RW RW

Bit Name Function


31:16 NA Reserved, undefined
15:0 CCR1[15:0] Capture/Compare 1 value
If channel CC1 is configured as output:
CCR1 is the value to be loaded in the actual capture/compare 1 register
(preload value). It is loaded permanently if the preload feature is not selected

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in the TIMx_CCMR1 register (bit OC1PE). Otherwise the preload value is


copied in the active capture/compare 1 register when an update event
occurs. The active capture/compare register contains the value to be
compared to the counter TIMx_CNT and signaled on OC1 output.
If channel CC1is configured as input:
CCR1 is the counter value transferred by the last input capture 1 event (IC1).

17.4.14. TIM3 capture/compare register 2(TIM3_CCR2)

Address offset: 0x38


Reset value: 0x0000
bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 CCR2[15:8]
type RW RW RW RW RW RW RW RW
7:0 CCR2[7:0]
type RW RW RW RW RW RW RW RW

Bit Name Function


31:16 NA Reserved, undefined
15:0 CCR2[15:0] Capture/Compare 2 value
If channel CC2 is configured as output:
CCR2 is the value to be loaded in the actual capture/compare 2 register
(preload value). It is loaded permanently if the preload feature is not selected
in the TIMx_CCMR2 register (bit OC2PE). Else the preload value is copied
in the active capture/compare 2 register when an update event occurs.
The active capture/compare register contains the value to be compared to
the counter TIMx_CNT and signaled on OC2 output.
If channel CC2 is configured as input:
CCR2 is the counter value transferred by the last input capture 2 event (IC2).

17.4.15. TIM3 capture/compare register 3(TIM3_CCR3)

Address offset: 0x3C


Reset value: 0x0000
bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0

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15:8 CCR3[15:8]
type RW RW RW RW RW RW RW RW
7:0 CCR3[7:0]
type RW RW RW RW RW RW RW RW

Bit Name Function


31:16 NA Reserved, undefined
15:0 CCR3[15:0] Capture/Compare 3 value
If channel CC3 is configured as output:
CCR3 is the value to be loaded in the actual capture/compare 3 register
(preload value). It is loaded permanently if the preload feature is not selected
in the TIMx_CCMR3 register (bit OC3PE). Else the preload value is copied
in the active capture/compare 3 register when an update event occurs.
The active capture/compare register contains the value to be compared to
the counter TIMx_CNT and signaled on OC3 output.
If channel CC3is configured as input:
CCR3 is the counter value transferred by the last input capture 3 event (IC3).

17.4.16. TIM3 capture/compare register 4(TIM3_CCR4)

Address offset: 0x40


Reset value: 0x0000
bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 CCR4[15:8]
type RW RW RW RW RW RW RW RW
7:0 CCR4[7:0]
type RW RW RW RW RW RW RW RW

Bit Name Function


31:16 NA Reserved, undefined
15:0 CCR4[15:0] Capture/Compare 4 value
If CC4 channel is configured as output:
CCR4 is the value to be loaded in the actual capture/compare 4 register
(preload value).
It is loaded permanently if the preload feature is not selected in the
TIMx_CCMR4 register (bit OC4PE). Otherwise, the preload value is copied
in the active capture/compare 4 register when an update event occurs.
The active capture/compare register contains the value to be compared to
the counter TIMx_CNT and signaled on OC4 output.
If CC4 channel is configured as input:
CCR4 is the counter value transferred by the last input capture 4 event (IC4).

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17.4.17. TIM3 DMA control register(TIM3_DCR)

Address offset: 0x48


Reset value: 0x0000
bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 — DBL[4:0]
type RO-0 RO-0 RO-0 RW RW RW RW RW
7:0 — DBA[4:0]
type RO-0 RO-0 RO-0 RW RW RW RW RW

Bit Name Function


31:13 NA Reserved, undefined
12:8 DBL[4:0] DMA burst length
This 5-bit vector defines the number of DMA transfers (the timer recognizes
a burst transfer when a read or a write access is done to the TIMx_DMAR
address).
00000: 1 transfer,
00001: 2 transfers,
00010: 3 transfers,
...
10001: 18 transfers.
7:5 NA Reserved, undefined
4:0 DBA[4:0] DMA base address
This 5-bit vector defines the base-address for DMA transfers (when
read/write access are done through the TIMx_DMAR address). DBA is
defined as an offset starting from the address of the TIMx_CR1 register.
Example:
00000: TIMx_CR1,
00001: TIMx_CR2,
00010: TIMx_SMCR,
...
Example:Let us consider the following transfer: DBL=7, DBA=TIMx_CR1
In this case the transfer is done to/from 7 registers starting from the
TIMx_CR1 address.

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17.4.18. TIM3 address for full transfer(TIM3_DMAR)

Address offset: 0x4C


Reset value: 0x0000
bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 DMAB[15:8]
type RW RW RW RW RW RW RW RW
7:0 DMAB[7:0]
type RW RW RW RW RW RW RW RW

Bit Name Function


31:16 NA Reserved, undefined
15:0 DMAB[15:0] DMA register for burst accesses
A read or write operation to the DMAR register accesses the register located
at the addressTIMx_CR1 address)+(DBA + DMA index)*4
where TIMx_CR1 address is the address of the control register 1, DBA is the
DMA base address configured in TIMx_DCR register, DMA index is
automatically controlled by the DMA transfer, and ranges from 0 to DBL
(DBL configured in TIMx_DCR).

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Example of how to use the DMA burst feature


In this example the timer DMA burst feature is used to update the contents of the CCRx registers (x = 2, 3, 4)
with the DMA transferring half words into the CCRx registers.
This is done in the following steps:
1. Configure the corresponding DMA channel as follows:
− DMA channel peripheral address is the DMAR register address
− DMA channel memory address is the address of the buffer in the RAM containing the data to be
transferred by DMA into CCRx registers.
− Number of data to transfer = 3
− Circular mode disabled
2. Configure the DCR register by configuring the DBA and DBL bit fields: DBL=3, DMA burst length of the
transfer is 3 , DBA=0xE, the initial transfer address offset is 0x38(TIMx_CCR2).
3. Enable the TIMx update DMA request
4. Enable TIMx
5. Enable the DMA channel
Note:This example is for the case where every CCRx register to be updated once. If every CCRx register is
to be updated twice for example, the number of data to transfer should be 6. Let us take the example of a
buffer in the RAM containing data1, data2, data3, data4, data5 and data6. The data is transferred to the
CCRx registers as follows: on the first update DMA request, data1 is transferred to CCR2, data2 is
transferred to CCR3, data3 is transferred to CCR4 and on the second update DMA request, data4 is
transferred to CCR2, data5 is transferred to CCR3 and data6 is transferred to CCR4.

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18. Basic timer(TIM6)

18.1. TIM6 introduction

The basic timer TIM6 consists of a 16-bit auto-reload counter driven by a programmable prescaler.

18.2. TIM6 main features

TIM6 features include:


 16-bit auto-reload upcounter
 16-bit programmable prescaler used to divide (also “on the fly”) the counter clock frequency by any
factor between 1 and 65535
 Interrupt/DMA generation on the update event: counter overflow

Internal Clock(CK_INT) Trigger Reset, Enable, Count


CK_TIM from RCC
Controller

Auto-reload register UI

Stop,clear or up
U
CK_PSC PSC CK_CNT
+/- CNT counter
prescaler

Notes:
Preload registers transferred
Reg
to active registers on UEV event
according to control bit

event

interrupt & DMA output

Figure 18-1 Basic timer block diagram

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18.3. TIM6 functional description

18.3.1. Time-base unit

The main block of the programmable timer is a 16-bit upcounter with its related auto-reload register. The
counter clock can be divided by a prescaler.
The counter, the auto-reload register and the prescaler register can be written or read by software. This is
true even when the counter is running.
The time-base unit includes:
 Counter Register(TIMx_CNT)
 Prescaler Register(TIMx_PSC)
 Auto-Reload Register(TIMx_ARR)
The auto-reload register is preloaded. The preload register is accessed each time an attempt is made to
write or read the auto-reload register. The contents of the preload register are transferred into the shadow
register permanently or at each update event UEV, depending on the auto-reload preload enable bit (ARPE)
in the TIMx_CR1 register. The update event is sent when the counter reaches the overflow value and if the
UDIS bit equals 0 in the TIMx_CR1 register. It can also be generated by software.
The counter is clocked by the prescaler output CK_CNT, which is enabled only when the counter enable bit
(CEN) in the TIMx_CR1 register is set.
Note that the actual counter enable signal CNT_EN is set 1 clock cycle after CEN.

Prescaler description
The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It is based on a
16-bit counter controlled through a 16-bit register (in the TIMx_PSC register). It can be changed on the fly as
the TIMx_PSC control register is buffered. The new prescaler ratio is taken into account at the next update
event.

Figure 18-2 and Figure 18-3 give some examples of the counter behavior when the prescaler ratio is
changed on the fly.

CK_PSC

CEN

CK_CNT

Counter register F7 F8 F9 FA FB FC 00 01 02 03

UEV

Prescaler control register 0 1

Write a new value in TIMx_PSC

Prescaler buffer 0 1

Prescaler counter 0 0 1 0 1 0 1 0 1

Figure 18-2 Counter timing diagram with prescaler division change from 1 to 4

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CK_PSC

CEN

CK_CNT

Counter register F7 F8 F9 FA FB FC 00 01

UEV

Prescaler control register 0 3

Write a new value in TIMx_PSC

Prescaler buffer 0 3

Prescaler counter 0 0 1 2 3 0 1 2 3

Figure 18-3 Counter timing diagram with prescaler division change from 1 to 4

18.3.2. Counter modes

The counter counts from 0 to the auto-reload value (contents of the TIMx_ARR register), then restarts from 0
and generates a counter overflow event. An update event can be generate at each counter overflow or by
setting the UG bit in the TIMx_EGR register.
The UEV event can be disabled by software by setting the UDIS bit in the TIMx_CR1 register. This avoids
updating the shadow registers while writing new values into the preload registers. In this way, no update
event occurs until the UDIS bit has been written to 0, however, the counter and the prescaler counter both
restart from 0 (but the prescale rate does not change). In addition, if the URS (update request selection) bit
in the TIMx_CR1 register is set, setting the UG bit generates an update event UEV, but the UIF flag is not
set (so no interrupt or DMA request is sent).
When an update event occurs, all the registers are updated and the update flag (UIF bit in the TIMx_SR
register) is set (depending on the URS bit):
 The auto-reload shadow register is updated with the preload value (TIMx_ARR).
 The buffer of the prescaler is reloaded with the preload value (contents of the TIMx_PSC register).
The following figures show some examples of the counter behavior for different clock frequencies when
TIMx_ARR = 0x36.

CK_PSC

CNT_EN

CK_CNT

Counter register 31 32 33 34 35 36 00 01 02 03 04 05 06 07

Counter overflow

UEV

UIF

Figure 18-4 Counter timing diagram, internal clock divided by 1

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CK_PSC

CNT_EN

CK_CNT

Counter register 34 35 36 00 01 02 03

Counter overflow

UEV

UIF

Figure 18-5 Counter timing diagram, internal clock divided by 2


CK_PSC

CNT_EN

CK_CNT

Counter register 35 36 00 01

Counter overflow

UEV

UIF

Figure 18-6 Counter timing diagram, internal clock divided by 4

CK_PSC

CK_CNT

Counter register 35 36 00 01

Counter overflow

UEV

UIF

Figure 18-7 Counter timing diagram, internal clock divided by N

CK_PSC

CEN

CK_CNT

Counter register 31 32 33 34 35 36 00 01 02 03 04 05 06 07

Counter overflow

UEV

UIF

Auto-reload preload register FF 36

Write a new value in TIMx_ARR

Figure 18-8 Counter timing diagram, update event when ARPE = 0

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CK_PSC

CEN

CK_CNT

Counter register F0 F1 F2 F3 F4 F5 00 01 02 03 04 05 06 07

Counter overflow

UEV

UIF

Auto-reload preload register F5 36

Auto-reload shadow register F5 36

Write a new value in TIMx_ARR

Figure 18-9 Counter timing diagram, update event when ARPE=1

18.3.3. Clock source

The counter clock is provided by the Internal clock (CK_INT) source.

The CEN (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual control bits and can
be changed only by software (except for UG that remains cleared automatically). As soon as the CEN bit is
written to 1, the prescaler is clocked by the internal clock CK_INT.

Figure 18-10 shows the behavior of the control circuit and the upcounter in normal mode, without prescaler.

Interal clock

CNT_EN

UG

CNT_INIT

CK_CNT=CK_PSC

Counter register 31 32 33 34 35 36 00 01 02 03 04 05 06 07

Figure 18-10 Control circuit in normal mode, internal clock divided by 1

18.3.4. Debug mode

When the microcontroller enters the debug mode (Cortex™-M0 core – halted), the TIMx counter either
continues to work normally or stops, depending on the DBG_TIMx_STOP configuration bit in the DBG
module.

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18.4. TIM6 register map

The following table shows the TIM6 register map and reset values.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
Address offset Name

9
8
7
6
5
4
3
2
1
0
ARPE

UDIS
OPM

CEN
URS
TIM6_CR1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–

–
–
–
0x00

Reset x x x x x x x x x x x x x x x x x x x x x x x x 0 x x x 0 0 0 0

UDE

UIE
TIM6_DIER
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–

–
–
–
–
–
–
–
0x0C

Reset x x x x x x x x x x x x x x x x x x x x x x x 0 x x x x x x x 0

UIF
TIM6_SR
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0x10

Reset x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 0

UG
TIM6_EGR
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0x14

Reset x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 0

TIM6_CNT CNT[15:0]
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0x24

Reset x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TIM6_PSC PSC[15:0]
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–

0x28

Reset x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TIM6_ARR ARR[15:0]
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–

0x2C

Reset x x x x x x x x x x x x x x x x 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

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18.4.1. TIM6 control register 1(TIM6_CR1)

Address offset: 0x00


Reset value: 0x0000
bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
7:0 ARPE — OPM URS UDIS CEN
type RW RO-0 RO-0 RO-0 RW RW RW RW

Bit Name Function


31:8 NA Reserved, undefined
7 ARPE Auto-reload preload enable
0: TIMx_ARR register is not buffered. It can be written directly
1: TIMx_ARR register is buffered.
6:4 NA Reserved, undefined
3 OPM One-pulse mode
0: Counter is not stopped at update event
1: Counter stops counting at the next update event (clearing the CEN bit).
2 URS Update request source
This bit is set and cleared by software to select the UEV event sources.
0: if UDIS allows to generate an update event, Any of the following events
generate an update interrupt or DMA request if enabled.
− Counter overflow/underflow
− Setting the UG bit
1: Only counter overflow/underflow generates an update interrupt or DMA
request if enabled.
1 UDIS Update disable
This bit is set and cleared by software to enable/disable UEV event
generation.
0: UEV enabled. The Update (UEV) event is generated by one of the
following events:
− Counter overflow/underflow
− Setting the UG bit
1: UEV disabled. The Update event is not generated, shadow registers keep
their value (ARR、PSC、CCRx). However the counter and the prescaler are
reinitialized if the UG bit is set.
0 CEN Counter enable
0: Counter disabled
1: Counter enabled

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18.4.2. TIM6 DMA/Interrupt enable register(TIM6_DIER)

Address offset: 0x0C


Reset value: 0x0000
bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 — UDE
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RW
7:0 — UIE
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RW

Bit Name Function


31:9 NA Reserved, undefined
8 UDE Update DMA request enable
0: Update DMA request disabled.
1: Update DMA request enabled.
7:1 NA Reserved, undefined
0 UIE Update interrupt enable
0: Update interrupt disabled.
1: Update interrupt enabled.

18.4.3. TIM6 status register(TIM6_SR)

Address offset: 0x10


Reset value: 0x0000
bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
7:0 — UIF
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RC_W0

Bit Name Function


31:1 NA Reserved, undefined
0 UIF Update interrupt flag
This bit is set by hardware on an update event. It is cleared by software.
0: No update occurred.

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1: Update interrupt pending. This bit is set by hardware when the registers
are updated:
− When the counter overflows, if UDIS = 0 in the TIMx_CR1 register
− When CNT is reinitialized by software using the UG bit in the
TIMx_EGR register, if URS = 0 and UDIS = 0 in the TIMx_CR1 register.

18.4.4. TIM6 event generation register(TIM6_EGR)

Address offset: 0x14


Reset value: 0x0000
bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
7:0 — UG
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 W

Bit Name Function


31:1 NA Reserved, undefined
0 UG Update generation
This bit can be set by software, it is automatically cleared by hardware.
0: No action.
1: Re-initializes the timer counter and generates an update of the registers.
Note that the prescaler counter is cleared too (but the prescaler ratio is not
affected).

18.4.5. TIM6 counter(TIM6_CNT)

Address offset: 0x24


Reset value: 0x0000
bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 CNT[15:8]
type RW RW RW RW RW RW RW RW
7:0 CNT[7:0]
type RW RW RW RW RW RW RW RW

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Bit Name Function


31:16 NA Reserved, undefined
15:0 CNT[15:0] Counter value

18.4.6. TIM6 prescaler(TIM6_PSC)

Address offset: 0x28


Reset value: 0x0000
bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 PSC[15:8]
type RW RW RW RW RW RW RW RW
7:0 PSC[7:0]
type RW RW RW RW RW RW RW RW

Bit Name Function


31:16 NA Reserved, undefined
15:0 PSC[15:0] Prescaler value
The counter clock frequency CK_CNT is equal to 𝑓𝐶𝐾_𝑃𝑆𝐶 /(PSC[15:0]+1).
PSC contains the value to be loaded into the active prescaler register at
each update event

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18.4.7. TIM6 auto-reload register(TIM6_ARR)

Address offset: 0x2C


Reset value: 0xFFFF
bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 ARR[15:8]
type RW RW RW RW RW RW RW RW
7:0 ARR[7:0]
type RW RW RW RW RW RW RW RW

Bit Name Function


31:16 NA Reserved, undefined
15:0 ARR[15:0] Auto-reload value
ARR is the value to be loaded into the actual auto-reload register.
Refer to Section 18.3.1: Time-base unit for more details about ARR update
and behavior. The counter is blocked while the auto-reload value is null.

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19. General-purpose timer(TIM14)

19.1. TIM14 introduction

The TIM14 general-purpose timer consists of a 16-bit auto-reload counter driven by a programmable
prescaler.
It may be used for a variety of purposes, including measuring the pulse lengths of input signals (input
capture) or generating output waveforms (output compare, PWM).
Pulse lengths and waveform periods can be modulated from a few microseconds to several milliseconds
using the timer prescaler and the RCC clock controller prescalers.
The TIM14 timer is completely independent, and does not share any resources.

19.2. TIM14 main features

TIM14 features include:


 16-bit auto-reload upcounter
 16-bit programmable prescaler used to divide the counter clock frequency by any factor between 1 and
65535 (can be changed “on the fly”)
 independent channel for:
− Input capture
− Output compare
− PWM generation (edge-aligned mode)
 Interrupt generation on the following events:
− Update: counter overflow, counter initialization (by software)
− Input capture
− Output compare

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Internal Clock(CK_INT) Trigger Enable, Count


CK_TIM from RCC
Controller

Auto-reload register UI

Stop,clear or up
U
CK_PSC PSC CK_CNT
+/- CNT counter
prescaler
CC1I UEV
CC1I
OC1 TIMx_CH1
TIMx_CH1 Input Filter & TI1FP1 IC1 OC1REF
TI1 IC1PS output
Edge Prescaler Capture/Compare 1 Register
control
detector

Notes:
Preload registers transferred
Reg
to active registers on UEV event
according to control bit

event

interrupt & DMA output

Figure 19-1 General-purpose timer block diagram

19.3. TIM14 functional description

19.3.1. Time-base unit

The main block of the programmable advanced-control timer is a 16-bit counter with its related auto-reload
register. The counter can count up. The counter clock can be divided by a prescaler.
The counter, the auto-reload register and the prescaler register can be written or read by software. This is
true even when the counter is running.
The time-base unit includes:
 Counter register(TIMx_CNT)
 Prescaler register(TIMx_PSC)
 Auto-reload register(TIMx_ARR)
The auto-reload register is preloaded. Writing to or reading from the auto-reload register accesses the
preload register. The content of the preload register are transferred into the shadow register permanently or
at each update event (UEV), depending on the auto-reload preload enable bit (ARPE) in TIMx_CR1 register.
The update event is sent when the counter reaches the overflow (or underflow when downcounting) and if
the UDIS bit equals 0 in the TIMx_CR1 register. It can also be generated by software. The generation of the
update event is described in detail for each configuration.
The counter is clocked by the prescaler output CK_CNT, which is enabled only when the counter enable bit
(CEN) in TIMx_CR1 register is set.
Note that the counter starts counting 1 clock cycle after setting the CEN bit in the TIMx_CR1 register.

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Prescaler description
The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It is based on a
16-bit counter controlled through a 16-bit register (in the TIMx_PSC register). It can be changed on the fly as
this control register is buffered. The new prescaler ratio is taken into account at the next update event.
Figure 19-2 and Figure 19-3 give some examples of the counter behavior when the prescaler ratio is
changed on the fly.

CK_PSC

CEN

CK_CNT

Counter register F7 F8 F9 FA FB FC 00 01 02 03

UEV

Prescaler control register 0 1

Write a new value in TIMx_PSC

Prescaler buffer 0 1

Prescaler counter 0 0 1 0 1 0 1 0 1

Figure 19-2 Counter timing diagram with prescaler division change from 1 to 2
CK_PSC

CEN

CK_CNT

Counter register F7 F8 F9 FA FB FC 00 01

UEV

Prescaler control register 0 3

Write a new value in TIMx_PSC

Prescaler buffer 0 3

Prescaler counter 0 0 1 2 3 0 1 2 3

Figure 19-3 Counter timing diagram with prescaler division change from 1 to 4

19.3.2. Counter modes

Upcounting mode
In upcounting mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register),
then restarts from 0 and generates a counter overflow event. Setting the UG bit in the TIMx_EGR register
also generates an update event.
The UEV event can be disabled by software by setting the UDIS bit in the TIMx_CR1 register. This is to
avoid updating the shadow registers while writing new values in the preload registers. Then no update event
occurs until the UDIS bit has been written to 0. However, the counter restarts from 0, as well as the counter
of the prescaler (but the prescale rate does not change). In addition, if the URS bit (update request selection)
in TIMx_CR1 register is set, setting the UG bit generates an update event UEV but without setting the UIF

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flag (thus no interrupt is sent). This is to avoid generating both update and capture interrupts when clearing
the counter on the capture event.
When an update event occurs, all the registers are updated and the update flag (UIF bit in TIMx_SR register)
is set (depending on the URS bit):
 The auto-reload shadow register is updated with the preload value (TIMx_ARR),
 The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC register).
The following figures show some examples of the counter behavior for different clock frequencies when
TIMx_ARR=0x36.

CK_PSC

CNT_EN

CK_CNT

Counter register 31 32 33 34 35 36 00 01 02 03 04 05 06 07

Counter overflow

UEV

UIF

Figure 19-4 Counter timing diagram, internal clock divided by 1

CK_PSC

CNT_EN

CK_CNT

Counter register 34 35 36 00 01 02 03

Counter overflow

UEV

UIF

Figure 19-5 Counter timing diagram, internal clock divided by 2

CK_PSC

CNT_EN

CK_CNT

Counter register 35 36 00 01

Counter overflow

UEV

UIF

Figure 19-6 Counter timing diagram, internal clock divided by 4

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Fremont Micro Devices FT32F0xxx8 RM

CK_PSC

CK_CNT

Counter register 35 36 00 01

Counter overflow

UEV

UIF

Figure 19-7 Counter timing diagram, internal clock divided by N


CK_PSC

CEN

CK_CNT

Counter register 31 32 33 34 35 36 00 01 02 03 04 05 06 07

Counter overflow

UEV

UIF

Auto-reload preload register FF 36

Write a new value in TIMx_ARR

Figure 19-8 Counter timing diagram, update event when ARPE=0


CK_PSC

CEN

CK_CNT

Counter register F0 F1 F2 F3 F4 F5 00 01 02 03 04 05 06 07

Counter overflow

UEV

UIF

Auto-reload preload register F5 36

Auto-reload shadow register F5 36

Write a new value in TIMx_ARR

Figure 19-9 Counter timing diagram, update event when ARPE=1

19.3.3. Clock source

The counter clock is provided by the Internal clock (CK_INT) source.


The CEN (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual control bits and can
be changed only by software (except for UG that remains cleared automatically). As soon as the CEN bit is
written to 1, the prescaler is clocked by the internal clock CK_INT.

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Figure 19-10 shows the behavior of the control circuit and the upcounter in normal mode, without prescaler.

Interal clock

CNT_EN

UG

CNT_INIT

CK_CNT=CK_PSC

Counter register 31 32 33 34 35 36 00 01 02 03 04 05 06 07

Figure 19-10 Control circuit in normal mode, internal clock divided by 1

19.3.4. Capture/compare channels

Each Capture/Compare channel is built around a capture/compare register (including a shadow register), a
input stage for capture (with digital filter, multiplexing and prescaler) and an output stage (with comparator
and output control).
The input stage samples the corresponding Tix input to generate a filtered signal TixF. Then, an edge
detector with polarity selection generates a signal (TixFPx) which can be used as trigger input by the slave
mode controller or as the capture command. It is prescaled before the capture register (IC1PS).

TI1F_ED

11
TI1 TI1F_Falling TI1FP1 IC1 Divider IC1PS
Filter Edge 01 /1,/2,/4,/8
fDTS TI1F_Rising
downcounter detector 00

ICF[3:0] CC1P/CC1NP
TIMx_CCMR1 TIMx_CCER CC1S[1:0] CCIE
TIMx_CCMR1 TIMx_CCER

Figure 19-11 Capture/compare channel (example: channel 1 input stage)


The output stage generates an intermediate waveform which is then used for reference: OcxRef (active
high). The polarity acts at the end of the chain.

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APB Bus

MCU-peripheral interface

high 8
if 16-bit

low 8
S write CCR1H
write_in_progress
Read CCR1H S read_in_progress
Capture/Compare Preload Register R write CCR1L
Read CCR1L R CC1S[1]
capture_transfer compare_transfer output
CC1S[0]
CC1S[1] mode
OC1PE OC1PE
CC1S[0] Capture/Compare Shadow Register UEV
capture from time TIMx_CCMR1
IC1PS base unit
CC1E CNT>CCR1
Counter CNT=CCR1
CC1G
TIMx_EGR

Figure 19-12 Capture/compare channel 1 main circuit

To the master
mode controller

CNT>CCR1 Output 0 Output OC1


mode OC1REF enable
CNT=CCR1 1 circuit
controller

CC1P
TIMx_CCER CC1E TIMx_CCER
OC1M[2:0]
TIMx_CCMR1

Figure 19-13 Output stage of capture/compare channel (channel 1)


The capture/compare block is made of one preload register and one shadow register. Write and read always
access the preload register.
In capture mode, captures are actually done in the shadow register, which is copied into the preload register.
In compare mode, the content of the preload register is copied into the shadow register which is compared
to the counter.

19.3.5. Input capture mode

In Input capture mode, the Capture/Compare Registers (TIMx_CCRx) are used to latch the value of the
counter after a transition detected by the corresponding Icx signal. When a capture occurs, the
corresponding CCXIF flag (TIMx_SR register) is set and an interrupt can be sent if it is enabled. If a capture
occurs while the CcxIF flag was already high, then the over-capture flag CcxOF (TIMx_SR register) is set.
CcxIF can be cleared by software by writing it to ‘0’ or by reading the captured data stored in the
TIMx_CCRx register. CcxOF is cleared when you write it to ‘0’.
The following example shows how to capture the counter value in TIMx_CCR1 when TI1 input rises. To do
this, use the following procedure:
 Select the active input: TIMx_CCR1 must be linked to the TI1 input, so write the CC1S bits to ‘01’ in the

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TIMx_CCMR1 register. As soon as CC1S becomes different from ‘00’, the channel is configured in input
mode and the TIMx_CCR1 register becomes read-only.
 Program the input filter duration you need with respect to the signal you connect to the timer (when the
input is one of the Tix (IcxF bits in the TIMx_CCMRx register). Let us imagine that, when toggling, the
input signal is not stable during at must 5 internal clock cycles. We must program a filter duration longer
than these 5 clock cycles. We can validate a transition on TI1 when 8 consecutive samples with the
new level have been detected (sampled at fDTS frequency). Then write IC1F bits to ‘0011’ in the
TIMx_CCMR1 register.
 Program the input prescaler. In our example, we wish the capture to be performed at each valid
transition, so the prescaler is disabled (write IC1PS bits to ‘00’ in the TIMx_CCMR1 register).
 Enable capture from the counter into the capture register by setting the CC1E bit in the TIMx_CCER
register.
 If needed, enable the related interrupt request by setting the CC1IE bit in the TIMx_DIER register.
When an input capture occurs:
 The TIMx_CCR1 register gets the value of the counter on the active transition.
 CC1IF flag is set (interrupt flag). CC1OF is also set if at least two consecutive captures occurred
whereas the flag was not cleared.
 An interrupt is generated depending on the CC1IE bit.
In order to handle the overcapture, it is recommended to read the data before the overcapture flag. This is to
avoid missing an overcapture which could happen after reading the flag and before reading the data.
Note:IC interrupt requests can be generated by software by setting the corresponding CCxG bit in the
TIMx_EGR register.

19.3.6. Forced output mode

In output mode (CCxS bits = ‘00’ in the TIMx_CCMRx register), each output compare signal (OCxREF and
then Ocx/OcxN) can be forced to active or inactive level directly by software, independently of any
comparison between the output compare register and the counter.
To force an output compare signal (OCXREF/Ocx) to its active level, you just need to write ‘101’ in the OcxM
bits in the corresponding TIMx_CCMRx register. Thus OCXREF is forced high (OCxREF is always active
high) and Ocx get opposite value to CCxP polarity bit.
For example: CCxP=’0’ (Ocx active high) => Ocx is forced to high level.
The OCxREF signal can be forced low by writing the OcxM bits to ‘100’ in the TIMx_CCMRx register.
The comparison between the TIMx_CCRx shadow register and the counter is still performed and allows the
flag to be set. Interrupt requests can be sent accordingly.

19.3.7. Output compare mode

This function is used to control an output waveform or to indicate when a period of time has elapsed.
When a match is found between the capture/compare register and the counter, the output compare function:
 Assigns the corresponding output pin to a programmable value defined by the output compare mode
(OcxM bits in the TIMx_CCMRx register) and the output polarity (CCxP bit in the TIMx_CCER register).

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The output pin can keep its level (OCXM=’000’), be set active (OcxM=’001’), be set inactive
(OcxM=’010’) or can toggle (OcxM=’011’) on match.
 Sets a flag in the interrupt status register (CcxIF bit in the TIMx_SR register).
 Generates an interrupt if the corresponding interrupt mask is set (CCXIE bit in the TIMx_DIER register).
The TIMx_CCRx registers can be programmed with or without preload registers using the OcxPE bit in the
TIMx_CCMRx register.
In output compare mode, the update event UEV has no effect on OCxREF and Ocx output. The timing
resolution is one count of the counter. Output compare mode can also be used to output a single pulse (in
One-pulse mode).
Procedure:
1. Select the counter clock (internal, external, prescaler).
2. Write the desired data in the TIMx_ARR and TIMx_CCRx registers.
3. Set the CcxIE bit if an interrupt request is to be generated.
4. Select the output mode. For example:
− Write OcxM = ‘011’ to toggle Ocx output pin when CNT matches CCRx
− Write OcxPE = ‘0’ to disable preload register
− Write CCxP = ‘0’ to select active high polarity
− Write CcxE = ‘1’ to enable the output
5. Enable the counter by setting the CEN bit in the TIMx_CR1 register.
The TIMx_CCRx register can be updated at any time by software to control the output waveform, provided
that the preload register is not enabled (OcxPE=’0’, else TIMx_CCRx shadow register is updated only at the
next update event UEV). An example is given in Figure 19-14.

Write B201h in the CC1R register

TIM1_CNT 0039 003A 003B B200 B201 B202 03

TIM1_CCR1 003A B201

oc1ref=OC1

Match detected on CCR1


Interrupt generated if enabled

Figure 19-14 Output compare mode, toggle on OC1

19.3.8. PWM mode

Pulse Width Modulation mode allows you to generate a signal with a frequency determined by the value of
the TIMx_ARR register and a duty cycle determined by the value of the TIMx_CCRx register.

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The PWM mode can be selected independently on each channel (one PWM per Ocx output) by writing ‘110’
(PWM mode 1) or ‘111’ (PWM mode 2) in the OcxM bits in the TIMx_CCMRx register. You must enable the
corresponding preload register by setting the OcxPE bit in the TIMx_CCMRx register, and eventually the
auto-reload preload register (in upcounting or center-aligned modes) by setting the ARPE bit in the
TIMx_CR1 register.
As the preload registers are transferred to the shadow registers only when an update event occurs, before
starting the counter, you have to initialize all the registers by setting the UG bit in the TIMx_EGR register.
The Ocx polarity is software programmable using the CCxP bit in the TIMx_CCER register. It can be
programmed as active high or active low. Ocx output is enabled by a combination of the CcxE, CcxNE, MOE,
OSSI and OSSR bits (TIMx_CCER and TIMx_BDTR registers).
In PWM mode (1 or 2), TIMx_CNT and TIMx_CCRx are always compared to determine whether
TIMx_CCRx ≤ TIMx_CNT or TIMx_CNT ≤ TIMx_CCRx (depending on the direction of the counter).

PWM edge-aligned mode


 Upcounting configuration
Upcounting is active when the DIR bit in the TIMx_CR1 register is low. In the following example, we consider
PWM mode 1. The reference PWM signal OCxREF is high as long as TIMx_CNT < TIMx_CCRx else it
becomes low. If the compare value in TIMx_CCRx is greater than the auto-reload value (in TIMx_ARR)
then OCxREF is held at ‘1’. If the compare value is 0 then OcxRef is held at ‘0’. Figure 19-15 shows some
edge-aligned PWM waveforms in an example where TIMx_ARR=8.

Counter register 0 1 2 3 4 5 6 7 8 0 1

OCxREF
CCRx=4
CCxIF

OCxREF
CCRx=8
CCxIF

OCxREF ‘1’
CCRx>8
CCxIF

OCxREF
‘0’
CCRx=0
CCxIF

Figure 19-15 Edge-aligned PWM waveforms (ARR=8)

19.3.9. Debug mode

When the microcontroller enters debug mode (Cortex™-M0 core halted), the TIMx counter either continues
to work normally or stops, depending on DBG_TIMx_STOP configuration bit in DBG module.

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19.4. TIM14 register map

The following table shows the TIM14 register map and reset values.
31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10
Address offset Name

0
CKD[1:0]

ARPE

UDIS
URS

CEN
TIM14_CR1
–

–
0x00

Reset x x x x x x x x x x x x x x x x x x x x x x 0 0 0 x x x x 0 0 0

CC1IE

UIE
TIM14_DIER
–

–
0x0C

Reset x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 0 0

CC1OF

CC1IF

UIF
TIM14_SR
–

–
0x10

Reset x x x x x x x x x x x x x x x x x x x x x x 0 x x x x x x x 0 0

CC1G

UG
TIM14_EGR
–

–
0x14

Reset x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 0 0

CC1S[1:0]
TIM14_

CC1PE

CC1FE
CCMR1 OC1M[2:0]
–

–
(output mode)

Reset x x x x x x x x x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0
0x18

CC1S[1:0]
IC1F[3:0]
TIM14_
IC1PSC
CCMR1
–

–
[1:0]
(input mode)

Reset x x x x x x x x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0

CC1NP

CC1P

CC1E
TIM14_CCER
–

–
0x20

Reset x x x x x x x x x x x x x x x x x x x x x x x x x x x x 0 x 0 0

TIM14_CNT CNT[15:0]
–

0x24

Reset x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TIM14_PSC PSC[15:0]
–

0x28

Reset x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TIM14_ARR ARR[15:0]
–

0x2C

Reset x x x x x x x x x x x x x x x x 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

TIM14_CCR1 CCR1[15:0]
–

0x34

Reset x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TI1_RMP

TIM14_OR
–

0x50

Reset x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 0 0

19.4.1. TIM14 control register 1(TIM14_CR1)

Address offset: 0x00


Reset value: 0x0000
bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0

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31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 — CKD[1:0]
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RW RW
7:0 ARPE — URS UDIS CEN
type RW RO-0 RO-0 RO-0 RO-0 RW RW RW

Bit Name Function


31:10 NA Reserved, undefined
9:8 CKD[1:0] Clock division
This bit-field indicates the division ratio between the timer clock (CK_INT)
frequency and sampling clock used by the digital filters (ETR, Tix),
00: 𝑡𝐷𝑇𝑆 = 𝑡𝐶𝐾_𝐼𝑁𝑇
01: 𝑡𝐷𝑇𝑆 = 2 ∗ 𝑡𝐶𝐾_𝐼𝑁𝑇
10: 𝑡𝐷𝑇𝑆 = 4 ∗ 𝑡𝐶𝐾_𝐼𝑁𝑇
11: Reserved, not allowed
7 ARPE Auto-reload preload enable
0: TIMx_ARR register is not buffered, and it can be written directly
1: TIMx_ARR register is buffered
6:3 NA Reserved, undefined
2 URS Update request source
This bit is set and cleared by software to select the update interrupt (UEV)
sources
0: if UDIS allows to generate an update event, Any of the following events
generate an update interrupt or DMA request if enabled.
− Counter overflow/underflow
− Setting the UG bit
− Update generation by reset trigger
Only counter overflow/underflow generates an update interrupt or DMA
request if enabled.
1 UDIS Update disable
This bit is set and cleared by software to enable/disable update interrupt
(UEV) event generation
0: UEV enabled. The Update (UEV) event is generated by one of the
following events:
− Counter overflow/underflow
− Setting the UG bit
− Update generation by reset trigger
1: UEV disabled. No UEV is generated, shadow registers keep their value
(ARR, PSC,CCRx). However the counter and the prescaler are reinitialized if
the UG bit is set or trigger evnent occurred in reset mode
0 CEN Counter enable
0: Counter disabled
1: Counter enabled

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19.4.2. TIM14 DMA/ interrupt enable register(TIM14_DIER)

Address offset: 0x0C


Reset value: 0x0000
bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
7:0 — CC1IE UIE
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RW RW

Bit Name Function


31:2 NA Reserved, undefined
1 CC1IE Capture/Compare 1 interrupt enable
0: CC1 interrupt disabled
1: CC1 interrupt enabled
0 UIE Update interrupt enable
0: Update interrupt disabled
1: Update interrupt enabled

19.4.3. TIM14 status register(TIM14_SR)

Address offset: 0x10


Reset value: 0x0000
bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 — CC1OF —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RC_W0 RO-0
7:0 — CC1IF UIF
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RC_W0 RC_W0

Bit Name Function


31:10 NA Reserved, undefined
9 CC1OF Capture/Compare 1 overcapture flag
This flag is set by hardware only when the corresponding channel is

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configured in input capture mode. It is cleared by software by writing it to ‘0’.


0: No overcapture has been detected.
1: The counter value has been captured in TIMx_CCR1 register while CC1IF
flag was already set
8:2 NA Reserved, undefined
1 CC1IF Capture/Compare 1 interrupt flag
If channel CC1 is configured as output:
This flag is set by hardware when the counter matches the compare value, with some
exception in center-aligned mode (refer to the CMS bits in the TIMx_CR1 register
description). It is cleared by software.
0: No match.
1: The content of the counter TIMx_CNT matches the content of the
TIMx_CCR1 register.
When the contents of TIMx_CCR1 are greater than the contents of
TIMx_ARR, the CC1IF bit goes high on the counter overflow (in upcounting
and up/down-counting modes) or underflow (in downcounting mode)
If channel CC1 is configured as input:
This bit is set by hardware on a capture. It is cleared by software or by
reading the TIMx_CCR1 register.
0: No input capture occurred
1: The counter value has been captured in TIMx_CCR1 register (An edge
has been detected on IC1 which matches the selected polarity)
0 UIF Update interrupt flag
This bit is set by hardware on an update event. It is cleared by software.
0: No update occurred.
1: Update interrupt pending. This bit is set by hardware when the registers
are updated:
− When counter overflows or underflows, if the UDIS=0 in the TIMx_CR1
register.
− When CNT is reinitialized by software using the UG bit in TIMx_EGR
register, if URS=0 and UDIS=0 in the TIMx_CR1 register.

19.4.4. TIM14 event generation register(TIM14_EGR)

Address offset: 0x14


Reset value: 0x0000
bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
7:0 — CC1G UG
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 W W

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Bit Name Function


31:2 NA Reserved, undefined
1 CC1G Capture/compare 1 generation
This bit is set by software in order to generate an event, it is automatically
cleared by hardware.
0: No action
1: A capture/compare event is generated on channel 1:
If channel CC1 is configured as output:
CC1IF flag is set, Corresponding interrupt or is sent if enabled.
If channel CC1 is configured as input:
The current value of the counter is captured in TIMx_CCR1 register. The
CC1IF flag is set, the corresponding interrupt is sent if enabled. The CC1OF
flag is set if the CC1IF flag was already high.
0 UG Update generation
This bit can be set by software, it is automatically cleared by hardware.
0: No action
1: Re-initialize the counter and generates an update of the registers.
Note that the prescaler counter is cleared too (anyway the prescaler ratio is
not affected).

19.4.5. TIM14 capture/compare mode register (TIM14_CCMR1)

Address offset: 0x18


Reset value: 0x0000
The channels can be used in input (capture mode) or in output (compare mode). The direction of a channel
is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different
function in input and in output mode. For a given bit, Ocxx describes its function when the channel is
configured in output, Icxx describes its function when the channel is configured in input. So you must take
care that the same bit can have a different meaning for the input stage and for the output stage.
Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
— OC1M[2:0] OC1PE OC1FE
7:0 CC1S[1:0]
IC1F[3:0] IC1PSC[1:0]
type RW RW RW RW RW RW RW RW

Output compare mode:


Bit Name Function
31:7 NA Reserved, undefined
6:4 OC1M[2:0] These bits define the behavior of the output reference signal OC1REF from

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which OC1 is derived. OC1REF is active high whereas OC1 active level
depends on CC1P and CC1NP bits.
000: Frozen. The comparison between the output compare register
TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs.
001: Set channel 1 to active level on match. OC1REF signal is forced high
when the counter TIMx_CNT matches the capture/compare register 1
(TIMx_CCR1).
010: Set channel 1 to inactive level on match. OC1REF signal is forced low
when the counter TIMx_CNT matches the capture/compare register 1
(TIMx_CCR1).
011: Toggle – OC1REF toggles when TIMx_CNT = TIMx_CCR1.
100: Force inactive level – OC1REF is forced low.
101: Force active level – OC1REF is forced high.
110: PWM mode 1
－ In upcounting, channel 1 is active as long as TIMx_CNT<TIMx_CCR1
else inactive
In downcounting, channel 1 is inactive (OC1REF=‘0’) as long as
TIMx_CNT>TIMx_CCR1 else active (OC1REF=’1’)
111: PWM mode 2
－ In upcounting, In upcounting, channel 1 is inactive as long as
TIMx_CNT<TIMx_CCR1 else active.
In downcounting, channel 1 is active as long as TIMx_CNT>TIMx_CCR1
else inactive.
Note: In PWM mode 1 or 2, the OCREF level changes only when the result
of the comparison changes or when the output compare mode switches from
“frozen” mode to “PWM” mode.
3 OC1PE Output compare 1 preload enable
0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at
anytime, the new value is taken in account immediately.
1: Preload register on TIMx_CCR1 enabled. Read/Write operations access
the preload register. TIMx_CCR1 preload value is loaded in the active
register at each update event.
2 OC1FE Output compare 1 fast enable
This bit is used to accelerate the effect of an event on the trigger in input on
the CC output.
0: CC1 behaves normally depending on counter and CCR1 values even
when the trigger is ON. The minimum delay to activate CC1 output when an
edge occurs on the trigger input is 5 clock cycles.
1: An active edge on the trigger input acts like a compare match on CC1
output. OC is then set to the compare level independently of the result of the
comparison. Delay to sample the trigger input and to activate CC1 output is
reduced to 3 clock cycles.
Note: OC1FE acts only if the channel is configured in PWM1 or PWM2
mode.
1:0 CC1S[1:0] Capture/Compare 1 selection
This bit-field defines the direction of the channel (input/output) as well as the
used input.
00: CC1 channel is configured as output.
01: CC1 channel is configured as input, IC1 is mapped on TI1.

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10: Reserved
11: Reserved
Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in
TIMx_CCER).

Input capture mode:


Bit Name Function
31:8 NA Reserved, undefined
7:4 IC1F[3:0] Input capture 1 filter
This bit-field defines the frequency used to sample TI1 input and the length
of the digital filter applied to TI1. The digital filter is made of an event counter
in which N events are needed to validate a transition on the output:
0000: No filter, sampling is done at 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐶𝐾_𝐼𝑁𝑇
0001: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐶𝐾_𝐼𝑁𝑇 , N=2
0010: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐶𝐾_𝐼𝑁𝑇 , N=4
0011: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐶𝐾_𝐼𝑁𝑇 , N=8
0100: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐷𝑇𝑆 /2, N=6
0101: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐷𝑇𝑆 /2, N=8
0110: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐷𝑇𝑆 /4, N=6
0111: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐷𝑇𝑆 /4, N=8
1000: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐷𝑇𝑆 /8, N=6
1001: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐷𝑇𝑆 /8, N=8
1010: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐷𝑇𝑆 /16, N=5
1011: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐷𝑇𝑆 /16, N=6
1100: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐷𝑇𝑆 /16, N=8
1101: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐷𝑇𝑆 /32, N=5
1110: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐷𝑇𝑆 /32, N=6
1111: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐷𝑇𝑆 /32, N=8
3:2 IC1PSC[1:0] Input capture 1 prescaler
This bit-field defines the ratio of the prescaler acting on CC1 input (IC1).
The prescaler is reset as soon as CC1E=’0’ (TIMx_CCER register).
00: no prescaler, capture is done each time an edge is detected on the
capture input
01: capture is done once every 2 events
10: capture is done once every 4 events
11: capture is done once every 8 events
1:0 CC1S[1:0] Capture/Compare 1 selection
This bit-field defines the direction of the channel (input/output) as well as the
used input.
0: CC1 channel is configured as output
01: CC1 channel is configured as input, IC1 is mapped on TI1
10:Reserved
11: Reserved
Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in
TIMx_CCER).

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19.4.6. TIM14 capture/compare enable register (TIM14_CCER)

Address offset: 0x20


Reset value: 0x0000
bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
7:0 — CC1NP — CC1P CC1E
type RO-0 RO-0 RO-0 RO-0 RW RO-0 RW RW

Bit Name Function


31:4 NA Reserved, undefined
3 CC1NP Capture/Compare 1 complementary output polarity
CC1 channel configuration as output:
0: OC1N active high.
1: OC1N active low.
CC1 channel configuration as input:
This bit is used in conjunction with CC1P to define the polarity of TI1FP1 and
TI2FP1. Refer to CC1P description.
Note1: This bit is not writable as soon as LOCK level 2 or 3 has been
programmed (LOCK bits in TIMx_BDTR register) and CC1S=”00” (the
channel is configured in output)..
Note2: On channels having a complementary output, this bit is preloaded. If
the CCPC bit is set in the TIMx_CR2 register then the CC1NP active bit
takes the new value from the preloaded bits only when a Commutation event
is generated.
2 NA Reserved, undefined
1 CC1P Capture/Compare 1 output Polarity.
CC1 channel configured as output:
0: OC1 active high
1: OC1 active low
CC1 channel configured as input:
CC1NP/CC1P bits select the active polarity of TI1FP1 and TI2FP1 for trigger
or capture operations.
00: non-inverted/rising edge
The circuit is sensitive to TixFP1 rising edge (capture or trigger operations in
reset, external clock or trigger mode), TixFP1 is not inverted ( in gated mode
or encoder mode).
01:inverted/falling edge
The circuit is sensitive to TixFP1 falling edge (capture or trigger operations in
reset, external clock or trigger mode), TixFP1 is inverted (in gated mode or

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encoder mode).
10:Reserved, do not use this configuration.
11:11: non-inverted/both edges
The circuit is sensitive to both TixFP1 rising and falling edges (capture or
trigger operations in reset, external clock or trigger mode), TixFP1 is not
inverted (in gated mode or encoder mode ).
0 CC1E Capture/Compare 1 output enable.
CC1 channel configured as output:
0: Off – OC1 is not active
1: On – OC1 signal is output on the corresponding output pin
CC1 channel configured as input:
This bit determines if a capture of the counter value can actually be done
into the input capture/compare register 1 (TIMx_CCR1) or not.
0: Capture disabled
1: Capture enabled

Table 19-1 Output control bits for complementary Ocx and OcxN channels with break feature
CcxE bit Ocx output state
0 Output Disabled(Ocx=0,Ocx_EN=0)
1 Ocx=OCxREF + Polarity, Ocx_EN=1
Note:The state of the external I/O pins connected to the standard Ocx channels depends on the Ocx
channel state and the GPIO registers.

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19.4.7. TIM14 counter(TIM14_CNT)

Address offset: 0x24


Reset value: 0x0000
bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 CNT[15:8]
type RW RW RW RW RW RW RW RW
7:0 CNT[7:0]
type RW RW RW RW RW RW RW RW

Bit Name Function


31:16 NA Reserved, undefined
15:0 CNT[15:0] Counter value

19.4.8. TIM14 prescaler(TIM14_PSC)

Address offset: 0x28


Reset value: 0x0000
bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 PSC[15:8]
type RW RW RW RW RW RW RW RW
7:0 PSC[7:0]
type RW RW RW RW RW RW RW RW

Bit Name Function


31:16 NA Reserved, undefined
15:0 PSC[15:0] Prescaler value
The counter clock frequency CK_CNT is equal to 𝑓𝐶𝐾_𝑃𝑆𝐶 /(PSC[15:0]+1).
PSC contains the value to be loaded in the active prescaler register at each
update event.

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19.4.9. TIM14 auto-reload register(TIM14_ARR)

Address offset: 0x2C


Reset value: 0xFFFF
bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 ARR[15:8]
type RW RW RW RW RW RW RW RW
7:0 ARR[7:0]
type RW RW RW RW RW RW RW RW

Bit Name Function


31:16 NA Reserved, undefined
15:0 ARR[15:0] Auto-reload value
ARR is the value to be loaded in the actual auto-reload register.
Refer to the Section 19.3.1: Time-base unit for more details about ARR
update and behavior. The counter is blocked while the auto-reload value is
null.

19.4.10. TIM14 capture/compare register 1(TIM14_CCR1)

Address offset: 0x34


Reset value: 0x0000
bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 CCR1[15:8]
type RW RW RW RW RW RW RW RW
7:0 CCR1[7:0]
type RW RW RW RW RW RW RW RW

Bit Name Function


31:16 NA Reserved, undefined
15:0 CCR1[15:0] Capture/Compare 1 value
If channel CC1 is configured as output:
CCR1 is the value to be loaded in the actual capture/compare 1 register
(preload value). It is loaded permanently if the preload feature is not selected

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in the TIMx_CCMR1 register (bit OC1PE). Else the preload value is copied
in the active capture/compare 1 register when an update event occurs.
The active capture/compare register contains the value to be compared to
the counter TIMx_CNT and signaled on OC1 output.
If channel CC1is configured as input:
CCR1 is the counter value transferred by the last input capture 1 event (IC1).

19.4.11. TIM14 option register(TIM14_OR)

Address offset: 0x50


Reset value: 0x0000
bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RW
7:0 — TI1_RMP
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RW RW

Bit Name Function


31:2 NA Reserved, undefined
1:0 TI1_RMP[1:0] Timer Input 1 remap
00: TIM14 Channel1 is connected to the GPIO.
01: TIM14 Channel1 is connected to the RTCCLK.
10: TIM14 Channel1 is connected to the HSE/32 Clock.
11: TIM14 Channel1 is connected to the microcontroller clock output (MCO),

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20. General-purpose timers(TIM15/16/17)

20.1. TIM15/16/17 introduction

The TIM15/16/17 timers consist of a 16-bit auto-reload counter driven by a programmable prescaler.
They may be used for a variety of purposes, including measuring the pulse lengths of input signals (input
capture) or generating output waveforms (output compare, PWM).
Pulse lengths and waveform periods can be modulated from a few microseconds to several milliseconds
using the timer prescaler and the RCC clock controller prescalers.
The TIM15/16/17 timers are completely independent, and do not share any resources. They can be
synchronized together.

20.2. TIM15 main features

TIM15 includes the following features:


 16-bit auto-reload upcounter
 16-bit programmable prescaler used to divide (also “on the fly”) the counter clock frequency by any
factor between 1 and 65535
 2 independent channels for:
− Input capture
− Output compare
− PWM generation (Edge-aligned mode)
− One-pulse mode output
 Complementary outputs with programmable dead-time (for channel 1 only)
 Synchronization circuit to control the timer with external signals and to interconnect several timers
together
 Repetition counter to update the timer registers only after a given number of cycles of the counter
 Break input to put the timer’s output signals in the reset state or a known state
 Interrupt/DMA generation on the following events:
− Update: counter overflow, counter initialization (by software or internal/external trigger)
− Trigger event (counter start, stop, initialization or count by internal/external trigger)
− Input capture
− Output compare
− Break input

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Internal Clock(CK_INT) Trigger


CK_TIM from RCC TRGO
Controller
to other timers
ITR0
ITR1 ITR TGI Reset, Enable, Up, Count
ITR2
ITR3 TRC TRGI Slave
Mode
TI1F_ED TI1FP1 Controller

TI1FP2

REP register

Auto-reload register UI
Repetition
Stop,clear or up/down counter U
CK_PSC PSC CK_CNT
+/- CNT counter
prescaler
DTG registers
CC1I UEV
CC1I
TI1FP1 OC1 TIMx_CH1
TIMx_CH1 TI1 Input Filter &
TI1FP2 IC1 IC1PS OC1REF output
Edge Prescaler Capture/Compare 1 Register DTG TIMx_CH1N
control OC1N
detector TRC
CC2I UEV
CC2I
TIMx_CH2 TI2 Input Filter & TI2FP1 IC2 IC2PS OC2REF output OC2 TIMx_CH2
Edge TI2FP2 Prescaler Capture/Compare 2 Register
control
detector TRC
ETRF
TIMx_BKIN BRK Polarity BI
Selection

Interal break event sources

Notes:
Preload registers transferred
Reg
to active registers on UEV event
according to control bit

event

interrupt & DMA output

Figure 20-1 TIM15 block diagram

20.3. TIM16 and TIM17 main features

The TIM16 and TIM17 timers include the following features:


 16-bit auto-reload upcounter
 16-bit programmable prescaler used to divide (also “on the fly”) the counter clock frequency by any
factor between 1 and 65535
 One channel for:
− Input capture
− Output compare
− PWM generation (Edge-aligned mode)
− One-pulse mode output
 Complementary outputs with programmable dead-time
 Synchronization circuit to control the timer with external signals and to interconnect several timers
together
 Repetition counter to update the timer registers only after a given number of cycles of the counter
 Break input to put the timer’s output signals in the reset state or a known state

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 Interrupt/DMA generation on the following events:


− Update: counter overflow, counter initialization (by software or internal/external trigger)
− Trigger event
− Input capture
− Output compare
− Break input

Internal Clock(CK_INT)

Counter Enable(CEN)
REP register

Auto-reload register UI
Repetition
Stop,clear or up counter U
CK_PSC PSC CK_CNT
+/- CNT counter
prescaler
DTG registers
CC1I UEV CC1I
OC1 TIMx_CH1
TIMx_CH1 TI1 Input Filter & TI1FP1 IC1 IC1PS OC1REF output
Edge Prescaler Capture/Compare 1 Register DTG TIMx_CH1N
control OC1N
detector

TIMx_BKIN BRK Polarity BI


Selection
Interal break event sources

Notes:
Preload registers transferred
Reg
to active registers on UEV event
according to control bit

event

interrupt & DMA output

Figure 20-2 TIM16、TIM17 block diagram

20.4. TIM15/16/17 functional description

20.4.1. Time-base unit

The main block of the programmable advanced-control timer is a 16-bit counter with its related auto-reload
register. The counter can count up. The counter clock can be divided by a prescaler.
The counter, the auto-reload register and the prescaler register can be written or read by software. This is
true even when the counter is running.
The time-base unit includes:
 Counter register (TIMx_CNT)
 Prescaler register (TIMx_PSC)
 Auto-reload register (TIMx_ARR)
 Repetition counter register (TIMx_RCR)
The content of the preload register are transferred into the shadow register permanently or at each update
event (UEV), depending on the auto-reload preload enable bit (ARPE) in TIMx_CR1 register. The update
event is sent when the counter reaches the overflow and if the UDIS bit equals 0 in the TIMx_CR1 register. It
can also be generated by software. The generation of the update event is described in detailed for each

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configuration.
The counter is clocked by the prescaler output CK_CNT, which is enabled only when the counter enable bit
(CEN) in TIMx_CR1 register is set (refer also to the slave mode controller description to get more details on
counter enabling).
Note that the counter starts counting 1 clock cycle after setting the CEN bit in the TIMx_CR1 register.

Prescaler description
The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It is based on a
16-bit counter controlled through a 16-bit register (in the TIMx_PSC register). It can be changed on the fly as
this control register is buffered. The new prescaler ratio is taken into account at the next update event.
Figure 20-3 and Figure 20-4 ive some examples of the counter behavior when the prescaler ratio is
changed on the fly:

CK_PSC

CEN

CK_CNT

Counter register F7 F8 F9 FA FB FC 00 01 02 03

UEV

Prescaler control register 0 1

Write a new value in TIMx_PSC

Prescaler buffer 0 1

Prescaler counter 0 0 1 0 1 0 1 0 1

Figure 20-3 Counter timing diagram with prescaler division change from 1 to 2
CK_PSC

CEN

CK_CNT

Counter register F7 F8 F9 FA FB FC 00 01

UEV

Prescaler control register 0 3

Write a new value in TIMx_PSC

Prescaler buffer 0 3

Prescaler counter 0 0 1 2 3 0 1 2 3

Figure 20-4 Counter timing diagram with prescaler division change from 1 to 4

20.4.2. Counter modes

Upcounting mode
In upcounting mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register),
then restarts from 0 and generates a counter overflow event.

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If the repetition counter is used, the update event (UEV) is generated after upcounting is repeated for the
number of times programmed in the repetition counter register (TIMx_RCR). Else the update event is
generated at each counter overflow.
Setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller) also
generates an update event.
The UEV event can be disabled by software by setting the UDIS bit in the TIMx_CR1 register. This is to
avoid updating the shadow registers while writing new values in the preload registers. Then no update event
occurs until the UDIS bit has been written to 0. However, the counter restarts from 0, as well as the counter
of the prescaler (but the prescale rate does not change). In addition, if the URS bit (update request selection)
in TIMx_CR1 register is set, setting the UG bit generates an update event UEV but without setting the UIF
flag (thus no interrupt or DMA request is sent). This is to avoid generating both update and capture interrupts
when clearing the counter on the capture event.
When an update event occurs, all the registers are updated and the update flag (UIF bit in TIMx_SR register)
is set (depending on the URS bit):
 The repetition counter is reloaded with the content of TIMx_RCR register,
 The auto-reload shadow register is updated with the preload value (TIMx_ARR),
 The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC register).
The following figures show some examples of the counter behavior for different clock frequencies when
TIMx_ARR=0x36.

CK_PSC

CNT_EN

CK_CNT

Counter register 31 32 33 34 35 36 00 01 02 03 04 05 06 07

Counter overflow

UEV

UIF

Figure 20-5 Counter timing diagram, internal clock divided by 1

CK_PSC

CNT_EN

CK_CNT

Counter register 34 35 36 00 01 02 03

Counter overflow

UEV

UIF

Figure 20-6 Counter timing diagram, internal clock divided by 2

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CK_PSC

CNT_EN

CK_CNT

Counter register 35 36 00 01

Counter overflow

UEV

UIF

Figure 20-7 Counter timing diagram, internal clock divided by 4

CK_PSC

CK_CNT

Counter register 35 36 00 01

Counter overflow

UEV

UIF

Figure 20-8 Counter timing diagram, internal clock divided by N


CK_PSC

CEN

CK_CNT

Counter register 31 32 33 34 35 36 00 01 02 03 04 05 06 07

Counter overflow

UEV

UIF

Auto-reload preload register FF 36

Write a new value in TIMx_ARR

Figure 20-9 Counter timing diagram, update event when ARPE=0

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CK_PSC

CEN

CK_CNT

Counter register F0 F1 F2 F3 F4 F5 00 01 02 03 04 05 06 07

Counter overflow

UEV

UIF

Auto-reload preload register F5 36

Auto-reload shadow register F5 36

Write a new value in TIMx_ARR

Figure 20-10 Counter timing diagram, update event when ARPE=1

20.4.3. Repetition counter

Section 20.4.1: Time-base unit describes how the update event (UEV) is generated with respect to the
counter overflows/underflows. It is actually generated only when the repetition counter has reached zero.
This can be useful when generating PWM signals.
This means that data are transferred from the preload registers to the shadow registers (TIMx_ARR
auto-reload register, TIMx_PSC prescaler register, but also TIMx_CCRx capture/compare registers in
compare mode) every N counter overflows or underflows, where N is the value in the TIMx_RCR repetition
counter register.
The repetition counter is decremented at each counter overflow in upcounting mode
The repetition counter is an auto-reload type; the repetition rate is maintained as defined by the TIMx_RCR
register value. When the update event is generated by software (by setting the UG bit in TIMx_EGR register)
or by hardware through the slave mode controller, it occurs immediately whatever the value of the repetition
counter is and the repetition counter is reloaded with the content of the TIMx_RCR register.

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Upcounting

TIMx_RCR=0 UEV

TIMx_RCR=1 UEV

TIMx_RCR=2 UEV

TIMx_RCR=3 UEV

TIMx_RCR=3
and UEV
re-synchronization (by SW)
Update event: Preload registers transferred to
UEV
active registers and update interrupt generated

Figure 20-11 Update rate examples depending on mode and TIMx_RCR register settings

20.4.4. Clock sources

The counter clock can be provided by the following clock sources:


 Internal clock (CK_INT)
 External clock mode1: external input pin
 Internal trigger inputs (ITRx) (only for TIM15): using one timer as the prescaler for another timer, for
example, you can configure TIM1 to act as a prescaler for TIM15.

Internal clock source (CK_INT)


if the slave mode controller is disabled (SMS=000), then the CEN, DIR (in the TIMx_CR1 register) and UG
bits (in the TIMx_EGR register) are actual control bits and can be changed only by software (except UG
which remains cleared automatically). As soon as the CEN bit is written to 1, the prescaler is clocked by the
internal clock CK_INT.
Figure 20-12 shows the behavior of the control circuit and the upcounter in normal mode, without prescaler.

Interal clock

CNT_EN

UG

CNT_INIT

CK_CNT=CK_PSC

Counter register 31 32 33 34 35 36 00 01 02 03 04 05 06 07

Figure 20-12 Control circuit in normal mode, internal clock divided by 1

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External clock source mode 1


This mode is selected when SMS=111 in the TIMx_SMCR register. The counter can count at each rising or
falling edge on a selected input.
TIMx_SMCR
TS[2:0]

ITRx
0xx
TI1_ED
100
TRGI External
TI1FP1 clock mode 1
101
TI2F_rising
TI2 Edge 0 TI2FP2 CK_PSC
Filter TI2F_falling 1 110
Detector
ETRF
111
CK_INT Internal clock
ICF[3:0] CC2P mode
(internal clock)
TIMx_CCMR1 TIMx_CCER

SMS[2:0]
TIMx_SMCR

Figure 20-13 TI2 external clock connection example

For example, to configure the upcounter to count in response to a rising edge on the TI2 input, use the
following procedure:
1. Configure channel 2 to detect rising edges on the TI2 input by writing CC2S = ‘01’ in the TIMx_CCMR1
register.
2. Configure the input filter duration by writing the IC2F[3:0] bits in the TIMx_CCMR1 register (if no filter is
needed, keep IC2F=0000).
3. Select rising edge polarity by writing CC2P=0 in the TIMx_CCER register.
4. Configure the timer in external clock mode 1 by writing SMS=111 in the TIMx_SMCR register.
5. Select TI2 as the trigger input source by writing TS=110 in the TIMx_SMCR register.
6. Enable the counter by writing CEN=1 in the TIMx_CR1 register.
Note:The capture prescaler is not used for triggering, so you don’t need to configure it.
When a rising edge occurs on TI2, the counter counts once and the TIF flag is set.
The delay between the rising edge on TI2 and the actual clock of the counter is due to the resynchronization
circuit on TI2 input.

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TI2

CEN

CK_CNT=CK_PSC

Counter register 34 35 36 0

TIF

Write TIF=0

Figure 20-14 Control circuit in external clock mode 1

20.4.5. Capture/compare channels

Each Capture/Compare channel is built around a capture/compare register (including a shadow register), a
input stage for capture (with digital filter, multiplexing and prescaler) and an output stage (with comparator
and output control).
The input stage samples the corresponding Tix input to generate a filtered signal TixF. Then, an edge
detector with polarity selection generates a signal (TixFPx) which can be used as trigger input by the slave
mode controller or as the capture command. It is prescaled before the capture register (IcxPS).

TI1F_ED
To the slave mode controller

TI1 TI1F_Rising
Filter Edge 0 TI1FP1
fDTS
downcounter detector TI1F_Falling 1
01
TI2FP1 IC1 Divider IC1PS
10
ICF[3:0] /1,/2,/4,/8
CC1P/CC1NP TRC
TIMx_CCMR1 11
(from slave
TIMx_CCER mode controller)

TI2F_Rising
(from channel 2) 0
CC1S[1:0] ICPS[1:0] CCIE
TI2F_Falling 1
(from channel 2)
TIMx_CCMR1 TIMx_CCER

Figure 20-15 Capture/compare channel (example: channel 1 input stage)


The output stage generates an intermediate waveform which is then used for reference: OcxRef (active
high). The polarity acts at the end of the chain.

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APB Bus

MCU-peripheral interface

high 8
if 16-bit

low 8
S write CCR1H
write_in_progress
Read CCR1H S read_in_progress
Capture/Compare Preload Register R write CCR1L
Read CCR1L R CC1S[1]
capture_transfer compare_transfer output
CC1S[0]
CC1S[1] mode
OC1PE OC1PE
CC1S[0] Capture/Compare Shadow Register UEV
IC1PS capture from time TIMx_CCMR1
CNT>CCR1 base unit
CC1E
Counter CNT=CCR1
CC1G
TIMx_EGR

Figure 20-16 Capture/compare channel 1 main circuit

TIMx_SMCR
OCCS

OCREF_CLR 0 Output OC1


0
enable
ETRF ‘0’ 1
1 x0 circuit
10
ocref_clr_int CC1P
OC1_DT 11
CNT>CCR TIMx_CCER
1 Output Dead-
OC1REF
mode time
CNT=CCR1
controller generator
11
OC1N_DT 0 Output OC1N
10 enable
‘0’ 1 circuit
0x

OC1CE OC1M[2:0] DTG[7:0] CC1NP


TIMx_CCMR1 TIMx_BDTR CC1NE CC1E TIMx_CCER
TIMx_CCER
MOE OSSI OSSR TIMx_BDTR
CC1NE CC1E
TIMx_CCER

Figure 20-17 Output stage of capture/compare channel (channel 1)

To the master
mode controller

CNT>CCR2 Output 0 Output OC2


mode OC2REF enable
CNT=CCR2 1 circuit
controller

CC2P
TIMx_CCER CC2E TIMx_CCER
OC2M[2:0]
TIMx_CCMR2 MOE OSSI TIMx_BDTR
OIS2 TIMx_CR2

Figure 20-18 Output stage of capture/compare channel (channel 2 for TIM15)


The capture/compare block is made of one preload register and one shadow register. Write and read always
access the preload register.
In capture mode, captures are actually done in the shadow register, which is copied into the preload register.

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In compare mode, the content of the preload register is copied into the shadow register which is compared
to the counter.

20.4.6. Input capture mode

In Input capture mode, the Capture/Compare Registers (TIMx_CCRx) are used to latch the value of the
counter after a transition detected by the corresponding Icx signal. When a capture occurs, the
corresponding CCXIF flag (TIMx_SR register) is set and an interrupt or a DMA request can be sent if they
are enabled. If a capture occurs while the CcxIF flag was already high, then the over-capture flag CcxOF
(TIMx_SR register) is set. CcxIF can be cleared by software by writing it to ‘0’ or by reading the captured
data stored in the TIMx_CCRx register. CcxOF is cleared when you write it to ‘0’.
The following example shows how to capture the counter value in TIMx_CCR1 when TI1 input rises. To do
this, use the following procedure:
 Select the active input: TIMx_CCR1 must be linked to the TI1 input, so write the CC1S bits to 01 in the
TIMx_CCMR1 register. As soon as CC1S becomes different from 00, the channel is configured in input
and the TIMx_CCR1 register becomes read-only.
 Program the input filter duration you need with respect to the signal you connect to the timer when the
input is one of the Tix (IcxF bits in the TIMx_CCMRx register). Let’s imagine that, when toggling, the
input signal is not stable during at must 5 internal clock cycles. We must program a filter duration longer
than these 5 clock cycles. We can validate a transition on TI1 when 8 consecutive samples with the
new level have been detected (sampled at f DTS frequency). Then write IC1F bits to 0011 in the
TIMx_CCMR1 register.
 Program the input prescaler. In our example, we wish the capture to be performed at each valid
transition, so the prescaler is disabled (write IC1PS bits to ‘00’ in the TIMx_CCMR1 register).
 Enable capture from the counter into the capture register by setting the CC1E bit in the TIMx_CCER
register.
 If needed, enable the related interrupt request by setting the CC1IE bit in the TIMx_DIER register,
and/or the DMA request by setting the CC1DE bit in the TIMx_DIER register.
When an input capture occurs:
 The TIMx_CCR1 register gets the value of the counter on the active transition.
 CC1IF flag is set (interrupt flag). CC1OF is also set if at least two consecutive captures occurred
whereas the flag was not cleared.
 An interrupt is generated depending on the CC1IE bit.
 A DMA request is generated depending on the CC1DE bit.
In order to handle the overcapture, it is recommended to read the data before the overcapture flag. This is to
avoid missing an overcapture which could happen after reading the flag and before reading the data.
Note:IC interrupt and/or DMA requests can be generated by software by setting the corresponding CCxG bit
in the TIMx_EGR register.

20.4.7. PWM input mode (only for TIM15)

This mode is a particular case of input capture mode. The procedure is the same except:

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 Two Icx signals are mapped on the same Tix input


 These 2 Icx signals are active on edges with opposite polarity
 One of the two TixFP signals is selected as trigger input and the slave mode controller is configured in
reset mode
For example, you can measure the period (in TIMx_CCR1 register) and the duty cycle (in TIMx_CCR2
register) of the PWM applied on TI1 using the following procedure (depending on CK_INT frequency and
prescaler value):
 Select the active input for TIMx_CCR1: write the CC1S bits to 01 in the TIMx_CCMR1 register (TI1
selected).
 Select the active polarity for TI1FP1 (used both for capture in TIMx_CCR1 and counter clear): write the
CC1P bit to ‘0’ (active on rising edge).
 Select the active input for TIMx_CCR2: write the CC2S bits to 10 in the TIMx_CCMR1 register (TI1
selected).
 Select the active polarity for TI1FP2 (used for capture in TIMx_CCR2): write the CC2P bit to ‘1’ (active
on falling edge).
 Select the valid trigger input: write the TS bits to 101 in the TIMx_SMCR register (TI1FP1 selected).
 Configure the slave mode controller in reset mode: write the SMS bits to 100 in the TIMx_SMCR
register.
 Enable the captures: write the CC1E and CC2E bits to ‘1’ in the TIMx_CCER register.

TI1

IC1/IC2

COUNTER
5 0 1 2 3 4 5 0

T1CCR1 5

T1CCR2 3

IC1: IC2: IC1:


reset counter m easure m easure
pulse width pulse period

Figure 20-19 PWM input mode timing

20.4.8. Forced output mode

In output mode (CCxS bits = 00 in the TIMx_CCMRx register), each output compare signal (OCxREF and
then Ocx/OcxN) can be forced to active or inactive level directly by software, independently of any
comparison between the output compare register and the counter.
To force an output compare signal (OCXREF/Ocx) to its active level, you just need to write 101 in the OcxM
bits in the corresponding TIMx_CCMRx register. Thus OCXREF is forced high (OCxREF is always active
high) and Ocx get opposite value to CCxP polarity bit.
The OCxREF signal can be forced low by writing the OcxM bits to 100 in the TIMx_CCMRx register.
Anyway, the comparison between the TIMx_CCRx shadow register and the counter is still performed and

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allows the flag to be set. Interrupt and DMA requests can be sent accordingly.

20.4.9. Output compare mode

This function is used to control an output waveform or indicating when a period of time has elapsed.
When a match is found between the capture/compare register and the counter, the output compare function:
 Assigns the corresponding output pin to a programmable value defined by the output compare mode
(OcxM bits in the TIMx_CCMRx register) and the output polarity (CCxP bit in the TIMx_CCER register).
The output pin can keep its level (OCXM=000), be set active (OcxM=001), be set inactive (OcxM=010)
or can toggle (OcxM=011) on match.
 Sets a flag in the interrupt status register (CcxIF bit in the TIMx_SR register).
 Generates an interrupt if the corresponding interrupt mask is set (CCXIE bit in the TIMx_DIER register).
 Sends a DMA request if the corresponding enable bit is set (CcxDE bit in the TIMx_DIER register,
CCDS bit in the TIMx_CR2 register for the DMA request selection).
The TIMx_CCRx registers can be programmed with or without preload registers using the OcxPE bit in the
TIMx_CCMRx register.
In output compare mode, the update event UEV has no effect on OCxREF and Ocx output. The timing
resolution is one count of the counter. Output compare mode can also be used to output a single pulse (in
One-pulse mode).
Procedure:
1. Select the counter clock (internal, external, prescaler).
2. Write the desired data in the TIMx_ARR and TIMx_CCRx registers.
3. Set the CcxIE bit if an interrupt request is to be generated.
4. Select the output mode. For example:
− Write OcxM = 011 to toggle Ocx output pin when CNT matches CCRx
− Write OcxPE = 0 to disable preload register
− Write CCxP = 0 to select active high polarity
− Write CcxE = 1 to enable the output
5. Enable the counter by setting the CEN bit in the TIMx_CR1 register.
The TIMx_CCRx register can be updated at any time by software to control the output waveform, provided
that the preload register is not enabled (OcxPE=’0’, else TIMx_CCRx shadow register is updated only at the
next update event UEV). An example is given in Figure 20-20.

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Write B201h in the CC1R register

TIM1_CNT 0039 003A 003B B200 B201 B202 03

TIM1_CCR1 003A B201

oc1ref=OC1

Match detected on CCR1


Interrupt generated if enabled

Figure 20-20 Output compare mode, toggle on OC1

20.4.10. PWM mode

Pulse Width Modulation mode allows you to generate a signal with a frequency determined by the value of
the TIMx_ARR register and a duty cycle determined by the value of the TIMx_CCRx register.
The PWM mode can be selected independently on each channel (one PWM per Ocx output) by writing ‘110’
(PWM mode 1) or ‘111’ (PWM mode 2) in the OcxM bits in the TIMx_CCMRx register. You must enable the
corresponding preload register by setting the OcxPE bit in the TIMx_CCMRx register, and eventually the
auto-reload preload register (in upcounting or center-aligned modes) by setting the ARPE bit in the
TIMx_CR1 register.
As the preload registers are transferred to the shadow registers only when an update event occurs, before
starting the counter, you have to initialize all the registers by setting the UG bit in the TIMx_EGR register.
Ocx polarity is software programmable using the CCxP bit in the TIMx_CCER register. It can be
programmed as active high or active low. Ocx output is enabled by a combination of the CcxE, CcxNE, MOE,
OSSI and OSSR bits (TIMx_CCER and TIMx_BDTR registers).
In PWM mode (1 or 2), TIMx_CNT and TIMx_CCRx are always compared to determine whether
TIMx_CCRx ≤ TIMx_CNT or TIMx_CNT ≤ TIMx_CCRx (depending on the direction of the counter).

PWM edge-aligned mode


 Upcounting configuration
Upcounting is active when the DIR bit in the TIMx_CR1 register is low. In the following example, we consider
PWM mode 1. The reference PWM signal OCxREF is high as long as TIMx_CNT < TIMx_CCRx else it
becomes low. If the compare value in TIMx_CCRx is greater than the auto-reload value (in TIMx_ARR) then
OCxREF is held at ‘1’. If the compare value is 0 then OcxRef is held at ‘0’. Figure 20-21 shows some
edge-aligned PWM waveforms in an example where TIMx_ARR=8.

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Counter register 0 1 2 3 4 5 6 7 8 0 1

OCxREF
CCRx=4
CCxIF

OCxREF
CCRx=8
CCxIF

OCxREF ‘1’
CCRx>8
CCxIF

OCxREF
‘0’
CCRx=0
CCxIF

Figure 20-21 Edge-aligned PWM waveforms (ARR=8)

20.4.11. Complementary outputs and dead-time insertion

The TIM15/16/17 general-purpose timers can output two complementary signals and manage the
switching-off and the switching-on instants of the outputs.
This time is generally known as dead-time and you have to adjust it depending on the devices you have
connected to the outputs and their characteristics (intrinsic delays of level-shifters, delays due to power
switches...)
You can select the polarity of the outputs (main output Ocx or complementary OcxN) independently for each
output. This is done by writing to the CCxP and CCxNP bits in the TIMx_CCER register.
The complementary signals Ocx and OcxN are activated by a combination of several control bits: the CcxE
and CcxNE bits in the TIMx_CCER register and the MOE, OISx, OISxN, OSSI and OSSR bits in the
TIMx_BDTR and TIMx_CR2 registers. Refer to Table : Output control bits for complementary Ocx and OcxN
channels with break feature for more details. In particular, the dead-time is activated when switching to the
IDLE state (MOE falling down to 0).
Dead-time insertion is enabled by setting both CcxE and CcxNE bits, and the MOE bit if the break circuit is
present. There is one 10-bit dead-time generator for each channel. From a reference waveform OCxREF, it
generates 2 outputs Ocx and OcxN. If Ocx and OcxN are active high:
 The Ocx output signal is the same as the reference signal except for the rising edge, which is delayed
relative to the reference rising edge.
 The OcxN output signal is the opposite of the reference signal except for the rising edge, which is
delayed relative to the reference falling edge.
If the delay is greater than the width of the active output (Ocx or OcxN) then the corresponding pulse is not
generated.
The following figures show the relationships between the output signals of the dead-time generator and the

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reference signal OCxREF. (we suppose CCxP=0, CCxNP=0, MOE=1, CcxE=1 and CcxNE=1 in these
examples)

OCxREF

delay
OCx

OCxN

delay

Figure 20-22 Complementary output with dead-time insertion

OCxREF

delay
OCx

OCxN

Figure 20-23 Dead-time waveforms with delay greater than the negative pulse

OCxREF

OCx

delay
OCxN

Figure 20-24 Dead-time waveforms with delay greater than the positive pulse

The dead-time delay is the same for each of the channels and is programmable with the DTG bits in the
TIMx_BDTR register. Refer to Section.Refer to Section 20.5.15: TIM15 break and dead-time register
(TIM15_BDTR) for delay calculation.

Re-directing OCxREF to Ocx or OcxN


In output mode (forced, output compare or PWM), OCxREF can be re-directed to the Ocx output or to OcxN
output by configuring the CcxE and CcxNE bits in the TIMx_CCER register.
This allows you to send a specific waveform (such as PWM or static active level) on one output while the
complementary remains at its inactive level. Other alternative possibilities are to have both outputs at
inactive level or both outputs active and complementary with dead-time.
Note: When only OcxN is enabled (CcxE=0, CcxNE=1), it is not complemented and becomes active as soon
as OCxREF is high. For example, if CCxNP=0 then OcxN=OcxRef. On the other hand, when both Ocx and

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OcxN are enabled (CcxE=CcxNE=1) Ocx becomes active when OCxREF is high whereas OcxN is
complemented and becomes active when OCxREF is low.

20.4.12. Using the break function

When using the break function, the output enable signals and inactive levels are modified according to
additional control bits (MOE, OSSI and OSSR bits in the TIMx_BDTR register, OISx and OISxN bits in the
TIMx_CR2 register). In any case, the Ocx and OcxN outputs cannot be set both to active level at a given
time. Refer to Table : Output control bits for complementary Ocx and OcxN channels with break feature for
more details.
The break source can be either the break input pin or one of the internal break sources as shown below:
 Core’s LOCKUP output
 PVD output
 A clock failure event is detected by Clock Security System (CSS)
When exiting from reset, the break circuit is disabled and the MOE bit is low. You can enable the break
function by setting the BKE bit in the TIMx_BDTR register. The break input polarity can be selected by
configuring the BKP bit in the same register. BKE and BKP can be modified at the same time. When the BKE
and BKP bits are written, a delay of 1 APB clock cycle is applied before the writing is effective. Consequently,
it is necessary to wait 1 APB clock period to correctly read back the bit after the write operation.
Because MOE falling edge can be asynchronous, a resynchronization circuit has been inserted between the
actual signal (acting on the outputs) and the synchronous control bit (accessed in the TIMx_BDTR register).
It results in some delays between the asynchronous and the synchronous signals. In particular, if you write
MOE to 1 whereas it was low, you must insert a delay (dummy instruction) before reading it correctly. This is
because you write the asynchronous signal and read the synchronous signal.
When a break occurs (selected level on the break input):
 The MOE bit is cleared asynchronously, putting the outputs in inactive state, idle state or in reset state
(selected by the OSSI bit). This feature functions even if the MCU oscillator is off.
 Each output channel is driven with the level programmed in the OISx bit in the TIMx_CR2 register as
soon as MOE=0. If OSSI=0 then the timer releases the enable output else the enable output remains
high.
 When complementary outputs are used:
− The outputs are first put in reset state inactive state (depending on the polarity). This is done
asynchronously so that it works even if no clock is provided to the timer.
− If the timer clock is still present, then the dead-time generator is reactivated in order to drive the
outputs with the level programmed in the OISx and OISxN bits after a dead-time. Even in this case,
Ocx and OcxN cannot be driven to their active level together. Note that because of the
resynchronization on MOE, the dead-time duration is a bit longer than usual (around 2 ck_tim
clock cycles).
− If OSSI=0 then the timer releases the enable outputs else the enable outputs remain or become
high as soon as one of the CcxE or CcxNE bits is high.
 The break status flag (BIF bit in the TIMx_SR register) is set. An interrupt can be generated if the BIE
bit in the TIMx_DIER register is set.
 If the AOE bit in the TIMx_BDTR register is set, the MOE bit is automatically set again at the next

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update event UEV. This can be used to perform a regulation, for instance. Else, MOE remains low until
you write it to ‘1’ again. In this case, it can be used for security and you can connect the break input to
an alarm from power drivers, thermal sensors or any security components.
Note:The break inputs is acting on level. Thus, the MOE cannot be set while the break input is active
(neither automatically nor by software). In the meantime, the status flag BIF cannot be cleared.
The break can be generated by the BRK input which has a programmable polarity and an enable bit BKE in
the TIMx_BDTR Register.
In addition to the break input and the output management, a write protection has been implemented inside
the break circuit to safeguard the application. It allows you to freeze the configuration of several parameters
(dead-time duration, Ocx/OcxN polarities and state when disabled, OcxM configurations, break enable and
polarity). You can choose from 3 levels of protection selected by the LOCK bits in the TIMx_BDTR register.
The LOCK bits can be written only once after an MCU reset.
The Figure 20-25 shows an example of behavior of the outputs in response to a break.

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OCxREF

OCx
(OCxN not implemented,CCxP=0,OISx=1)

OCx
(OCxN not implemented,CCxP=0,OISx=0)

OCx
(OCxN not implemented,CCxP=1,OISx=1)

OCx
(OCxN not implemented,CCxP=1,OISx=0)

OCx

OCxN delay delay delay


(CCxE=1,CCxP=0,OISx=0,CCxNE=1,CCxNP=0,OISxN=1)

OCx

OCxN delay delay delay


(CCxE=1,CCxP=0,OISx=0,CCxNE=1,CCxNP=0,OISxN=1)

OCx

OCxN delay
(CCxE=1,CCxP=0,OISx=1,CCxNE=1,CCxNP=1,OISxN=1)

OCx
OCxN delay
(CCxE=1,CCxP=0,OISx=0,CCxNE=0,CCxNP=0,OISxN=1)

OCx
OCxN
(CCxE=1,CCxP=0,CCxNE=0,CCxNP=0,OISx=OISxN=0 or OISx=OISxN=1)

Figure 20-25 Output behavior in response to a break

20.4.13. One-pulse mode

One-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to be started in
response to a stimulus and to generate a pulse with a programmable length after a programmable delay.
Starting the counter can be controlled through the slave mode controller. Generating the waveform can be
done in output compare mode or PWM mode. You select One-pulse mode by setting the OPM bit in the
TIMx_CR1 register. This makes the counter stop automatically at the next update event UEV.
A pulse can be correctly generated only if the compare value is different from the counter initial value. Before
starting (when the timer is waiting for the trigger), the configuration must be:

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 upcounting: CNT < CCRx ≤ ARR (in particular, 0 < CCRx)


 In downcounting: CNT > CCRx

TI2

OC1REF

OC1

TIM1_ARR

TIM1_CCR1

0 Tdelay TIME
Tpulse

Figure 20-26 Example of One-pulse mode


For example you may want to generate a positive pulse on OC1 with a length of 𝑇𝑝𝑢𝑙𝑠𝑒 and after a delay of
𝑇𝑑𝑒𝑙𝑎𝑦 as soon as a positive edge is detected on the TI2 input pin.
Let’s use TI2FP2 as trigger 1:
 Map TI2FP2 to TI2 by writing CC2S=’01’ in the TIMx_CCMR1 register.
 TI2FP2 must detect a rising edge, write CC2P=0 and CC2NP=0 in the TIMx_CCER register.
 Configure TI2FP2 as trigger for the slave mode controller (TRGI) by writing TS=’110’ in the
TIMx_SMCR register.
 TI2FP2 is used to start the counter by writing SMS to ‘110’ in the TIMx_SMCR register (trigger mode).
The OPM waveform is defined by writing the compare registers (taking into account the clock frequency and
the counter prescaler).
 The 𝑇𝑑𝑒𝑙𝑎𝑦 is defined by the value written in the TIMx_CCR1 register.
 The 𝑇𝑝𝑢𝑙𝑠𝑒 is defined by the difference between the auto-reload value and the compare value
(TIMx_ARR – TIMx_CCR1 + 1).
 Let’s say you want to build a waveform with a transition from ‘0’ to ‘1’ when a compare match occurs
and a transition from ‘1’ to ‘0’ when the counter reaches the auto-reload value. To do this you enable
PWM mode 2 by writing OC1M=111 in the TIMx_CCMR1 register. You can optionally enable the
preload registers by writing OC1PE=’1’ in the TIMx_CCMR1 register and ARPE in the TIMx_CR1
register. In this case you have to write the compare value in the TIMx_CCR1 register, the auto-reload
value in the TIMx_ARR register, generate an update by setting the UG bit and wait for external trigger
event on TI2. CC1P is written to ‘0’ in this example.
In our example, the DIR and CMS bits in the TIMx_CR1 register should be low.
You only want 1 pulse, so you write ‘1’ in the OPM bit in the TIMx_CR1 register to stop the counter at the
next update event (when the counter rolls over from the auto-reload value back to 0). When OPM bit in the
TIMx_CR1 register is set to ‘0’, so the Repetitive Mode is selected.

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Particular case: Ocx fast enable


In One-pulse mode, the edge detection on Tix input set the CEN bit which enables the counter. Then the
comparison between the counter and the compare value makes the output toggle. But several clock cycles
are needed for these operations and it limits the minimum delay 𝑇𝑑𝑒𝑙𝑎𝑦 min we can get.
If you want to output a waveform with the minimum delay, you can set the OcxFE bit in the TIMx_CCMRx
register. Then OcxRef are forced in response to the stimulus, without taking in account the comparison. Its
new level is the same as if a compare match had occurred. OcxFE acts only if the channel is configured in
PWM1 or PWM2 mode.

20.4.14. TIM15 external trigger synchronization

The TIM15 timer can be synchronized with an external trigger in several modes: Reset mode, Gated mode
and Trigger mode.

Slave mode: Reset mode


The counter and its prescaler can be reinitialized in response to an event on a trigger input. Moreover, if the
URS bit from the TIMx_CR1 register is low, an update event UEV is generated. Then all the preloaded
registers (TIMx_ARR, TIMx_CCRx) are updated.
In the following example, the upcounter is cleared in response to a rising edge on TI1 input:
 Configure the channel 1 to detect rising edges on TI1. Configure the input filter duration (in this example,
we don’t need any filter, so we keep IC1F=0000). The capture prescaler is not used for triggering, so
you don’t need to configure it. The CC1S bits select the input capture source only, CC1S = 01 in the
TIMx_CCMR1 register. Write CC1P=0 and CC1NP=0 in TIMx_CCER register to validate the polarity
(and detect rising edges only).
 Configure the timer in reset mode by writing SMS=100 in TIMx_SMCR register. Select TI1 as the input
source by writing TS=101 in TIMx_SMCR register.
 Start the counter by writing CEN=1 in the TIMx_CR1 register.
The counter starts counting on the internal clock, then behaves normally until TI1 rising edge. When TI1
rises, the counter is cleared and restarts from 0. In the meantime, the trigger flag is set (TIF bit in the
TIMx_SR register) and an interrupt request, or a DMA request can be sent if enabled (depending on the TIE
and TDE bits in TIMx_DIER register).
The following figure shows this behavior when the auto-reload register TIMx_ARR=0x36. The delay
between the rising edge on TI1 and the actual reset of the counter is due to the resynchronization circuit on
TI1 input.

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TI1

UG

ck_cnt=ck_psc

Counter register 30 31 32 33 34 35 36 0 1 2 3 0 1 2 3

TIF

Figure 20-27 Control circuit in reset mode

Slave mode: Gated mode


The counter can be enabled depending on the level of a selected input.
In the following example, the upcounter counts only when TI1 input is low:
 Configure the channel 1 to detect low levels on TI1. Configure the input filter duration (in this example,
we don’t need any filter, so we keep IC1F=0000). The capture prescaler is not used for triggering, so
you don’t need to configure it. The CC1S bits select the input capture source only, CC1S=01 in
TIMx_CCMR1 register. Write CC1P=1 and CC1NP=0 in TIMx_CCER register to validate the polarity
(and detect low level only).
 Configure the timer in gated mode by writing SMS=101 in TIMx_SMCR register. Select TI1 as the input
source by writing TS=101 in TIMx_SMCR register.
 Enable the counter by writing CEN=1 in the TIMx_CR1 register (in gated mode, the counter doesn’t
start if CEN=0, whatever is the trigger input level).
The counter starts counting on the internal clock as long as TI1 is low and stops as soon as TI1 becomes
high. The TIF flag in the TIMx_SR register is set both when the counter starts or stops.
The delay between the rising edge on TI1 and the actual stop of the counter is due to the resynchronization
circuit on TI1 input.

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TI1

synchronization time
CEN

synchronization time
cnt_en

ck_cnt=ck_psc

Counter register 30 31 32 33 34 35 36 37 38

TIF

write TIF=0

Figure 20-28 Control circuit in gated mode

Slave mode: Trigger mode


The counter can start in response to an event on a selected input.
In the following example, the upcounter starts in response to a rising edge on TI2 input:
 Configure the channel 2 to detect rising edges on TI2. Configure the input filter duration (in this example,
we don’t need any filter, so we keep IC2F=0000). The capture prescaler is not used for triggering, so
you don’t need to configure it. The CC2S bits are configured to select the input capture source only,
CC2S=01 in TIMx_CCMR1 register. Write CC2P=1 and CC2NP=0 in TIMx_CCER register to validate
the polarity (and detect low level only).
 Configure the timer in trigger mode by writing SMS=110 in TIMx_SMCR register. Select TI2 as the input
source by writing TS=110 in TIMx_SMCR register.
When a rising edge occurs on TI2, the counter starts counting on the internal clock and the TIF flag is set.
The delay between the rising edge on TI2 and the actual start of the counter is due to the resynchronization
circuit on TI2 input.

TI2

synchorization tim e
CNT_EN

ck_cnt=ck_psc

Counter register 34 35 36 37

TIF

Figure 20-29 Control circuit in trigger mode

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20.4.15. Timer synchronization

The TIM timers are linked together internally for timer synchronization or chaining. Refer to Section 17.3.15:
Timer synchronization for details.

20.4.16. Debug mode

When the microcontroller enters debug mode (Cortex™-M0 core halted), the TIMx counter either continues
to work normally or stops, depending on DBG_TIMx_STOP configuration bit in DBG module.

20.5. TIM15 register map

The following table shows the TIM15 register map and reset values.
31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10
Address offset Name

0
CKD[1:0]

ARPE

UDIS
OPM

URS

CEN
TIM15_CR1
–

–
0x00

Reset x x x x x x x x x x x x x x x x x x x x x x 0 0 0 x x x 0 0 0 0

OIS1N

CCDS

CCUS

CCPC
OIS2

OIS1
TIM15_CR2 MMS[2:0]
–

–
0x04

Reset x x x x x x x x x x x x x x x x x x x x x 1 1 1 x 0 0 0 0 0 x 0

MSM
TIM15_SMCR TS[2:0] SMS[2:0]
–

–
0x08

Reset x x x x x x x x x x x x x x x x x x x x x x x x 0 0 0 0 x 0 0 0
CC2DE

CC1DE

COMIE

CC2IE

CC1IE
UDE
TDE

UIE
BIE

TIE

TIM15_DIER
–

–
0x0C

Reset x x x x x x x x x x x x x x x x x 0 x x x 0 0 0 0 0 0 x x 0 0 0
CC2OF

CC1OF

COMIF

CC2IF

CC1IF

UIF
BIF

TIF

TIM15_SR
–

0x10

Reset x x x x x x x x x x x x x x x x x x x x x 0 0 x 0 0 0 x x 0 0 0
COMG

CC2G

CC1G
BG

TG

UG

TIM15_EGR
–

0x14

Reset x x x x x x x x x x x x x x x x x x x x x x x x 0 0 0 x x 0 0 0

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CC2S[1:0]

CC1S[1:0]
TIM15

CC2PE

CC2FE

CC1PE

CC1FE
_CCMR1 OC2M[2:0] OC1M[2:0]

–
(output mode)

Reset x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 x 0 0 0 0 0 0 0
0x18

CC2S[1:0]

CC1S[1:0]
IC2F[3:0]

IC1F[3:0]
TIM15
IC2PSC IC1PSC
_CCMR1

–
[1:0] [1:0]
(input mode)

Reset x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CC2NP

CC1NP

CC1NE
CC2P

CC2E

CC1P

CC1E
TIM15_CCER
–

–
0x20

Reset x x x x x x x x x x x x x x x x x x x x x x x x 0 x 0 0 0 0 0 0

TIM15_CNT CNT[15:0]
–

–
0x24

Reset x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TIM15_PSC PSC[15:0]
–

–
0x28

Reset x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TIM15_ARR ARR[15:0]
–

–
0x2C

Reset x x x x x x x x x x x x x x x x 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

TIM15_RCR REP[7:0]
–

–
0x30

Reset x x x x x x x x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0

TIM15_CCR1 CCR1[15:0]
–

0x34

Reset x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TIM15_CCR2 CCR2[15:0]
–

0x38

Reset x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
LOCK[1:0]
OSSR
MOE

OSSI
AOE

BKP

BKE

TIM15_BDTR DTG[7:0]
–

0x44

Reset x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TIM15_DCR DBL[4:0] DBA[4:0]


–

0x48

Reset x x x x x x x x x x x x x x x x x x x 0 0 0 0 0 x x x 0 0 0 0 0

TIM15_DMAR DMAB[15:0]
–

0x4C

Reset x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

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20.5.1. TIM15 control register 1(TIM15_CR1)

Address offset: 0x00


Reset value: 0x0000
bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 — CKD[1:0]
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RW RW
7:0 ARPE — OPM URS UDIS CEN
type RW RO-0 RO-0 RO-0 RW RW RW RW

Bit Name Function


31:10 NA Reserved, undefined
9:8 CKD[1:0] Clock division
This bit field indicates the division ratio between the timer clock (CK_INT)
frequency and the dead-time and sampling clock ( 𝑡𝐷𝑇𝑆 )used by the
dead-time generators (ETR、Tix) and the digital filters
(Tix)
00: 𝑡𝐷𝑇𝑆 = 𝑡𝐶𝐾_𝐼𝑁𝑇
01: 𝑡𝐷𝑇𝑆 = 2 ∗ 𝑡𝐶𝐾_𝐼𝑁𝑇
10: 𝑡𝐷𝑇𝑆 = 4 ∗ 𝑡𝐶𝐾_𝐼𝑁𝑇
11: Reserved, do not program this value.
7 ARPE Auto-reload preload enable
0: TIMx_ARR register is not buffered and it can be written directly
1: TIMx_ARR register is buffered
6:5 NA Reserved, undefined
4 DIR Direction
0: Counter used as upcounter
1: Counter used as downcounter
3 OPM One-pulse mode
0: Counter is not stopped at update event
1: Counter stops counting at the next update event (clearing the bit CEN)
2 URS Update request source
This bit is set and cleared by software to select the UEV event sources.
0: if UDIS allows to generate an update event, Any of the following events
generate an update interrupt or DMA request if enabled.
− Counter overflow/underflow
− Setting the UG bit
− Update generation by reset trigger
1: Only counter overflow/underflow generates an update interrupt or DMA
request if enabled.

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1 UDIS Update disable


This bit is set and cleared by software to enable/disable UEV event
generation.
0: UEV enabled. The Update (UEV) event is generated by one of the
following events:
− Counter overflow/underflow
− Setting the UG bit
− Update generation by reset trigger
1: UEV disabled. The Update event is not generated, shadow registers keep
their value (ARR, PSC, CCRx). However the counter and the prescaler are
reinitialized if the UG bit is set.
0 CEN Counter enable
0: Counter disabled
1: Counter enabled
Note: External clock and gated mode can work only if the CEN bit has been
previously set by software. However trigger mode can set the CEN bit
automatically by hardware.

20.5.2. TIM15 control register 2(TIM15_CR2)

Address offset: 0x04


Reset value: 0x0000
bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 — OIS2 OIS1N OIS1
type RO-0 RO-0 RO-0 RO-0 RO-0 RW RW RW
7:0 — MMS[2:0] CCDS CCUS — CCPC
type RO-0 RW RW RW RW RW RO-0 RW

Bit Name Function


31:11 NA Reserved, undefined
10 OIS2 Output idle state 2 (OC2 output) Refer to OIS1bit
9 OIS1N Output Idle state 1 (OC1N output)
0: OC1N=0 after a dead-time when MOE=0
1: OC1N=1 after a dead-time when MOE=0
Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been
programmed (LOCK bits in TIMx_BKR register).
8 OIS1 Output Idle state 1 (OC1 output)
0: OC1=0 (after a dead-time if OC1N is implemented) when MOE=0
1: OC1=1 (after a dead-time if OC1N is implemented) when MOE=0
Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been
programmed (LOCK bits in TIMx_BKR register).

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7 NA Reserved, undefined
6:4 MMS[2:0] Master mode selection
These bits allow to select the information to be sent in master mode to slave
timers for synchronization (TRGO). The combination is as follows:
000: Reset – the UG bit from the TIMx_EGR register is used as trigger
output (TRGO). If the reset is generated by the trigger input
(SMS[2:0]=100) then the signal on TRGO is delayed compared to the
actual reset.
001: Enable – the Counter Enable signal CNT_EN is used as trigger output
(TRGO). It is useful to start several timers at the same time or to control a
window in which a slave timer is enable. The Counter Enable signal is
generated by a logic OR between CEN control bit and the trigger input when
configured in gated mode. When the Counter Enable signal is controlled by
the trigger input, there is a delay on TRGO, except if the master/slave mode
is selected (see the MSM bit description in TIMx_SMCR register).
010: Update – The update event is selected as trigger output (TRGO). For
instance a master timer can then be used as a prescaler for a slave timer.
011: Compare Pulse – The trigger output send a positive pulse when the
CC1IF flag is to be set (even if it was already high), as soon as a capture or
a compare match occurred. (TRGO).
100: Compare – OC1REF signal is used as trigger output (TRGO).
101: Compare – OC2REF signal is used as trigger output (TRGO).
110: Reserved
111: Reserved
3 CCDS Capture/compare DMA selection
0: CCx DMA request sent when CCx event occurs
1: CCx DMA requests sent when update event occurs
2 CCUS Capture/compare control update selection
0: When capture/compare control bits are preloaded (CCPC=1), they are
updated by setting the COMG bit only.
1: When capture/compare control bits are preloaded (CCPC=1), they are
updated by setting the COMG bit or when an rising edge occurs on TRGI.
Note: This bit acts only on channels that have a complementary output.
1 NA Reserved, undefined
0 CCPC Capture/compare preloaded control
0: CcxE, CcxNE, CCxP, CCxNP and OcxM bits are not preloaded
1: CcxE, CcxNE, CCxP, CCxNP and OcxM bits are preloaded, after having
been written, they are updated only when COMG bit set or rising edge detected
on TRGI, depending on the CCUS bit)
Note: This bit acts only on channels that have a complementary output.

20.5.3. TIM15 slave mode control register(TIM15_SMCR)

Address offset: 0x08


Reset value: 0x0000
bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —

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type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0


23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
7:0 MSM TS[2:0] — SMS[2:0]
type RW RW RW RW RO-0 RW RW RW

Bit Name Function


31:8 NA Reserved, undefined
7 MSM Master/slave mode
0: No action
1: The effect of an event on the trigger input (TRGI) is delayed to allow a
perfect synchronization between the current timer and its slaves (through
TRGO). It is useful if we want to synchronize several timers on a single
external event.
6:4 TS[2:0] Trigger selection
This bit field selects the trigger input to be used to synchronize the counter.
000: Reserved
001: Internal Trigger 1 (ITR1)
010: Internal Trigger 2 (ITR2)
011: Internal Trigger 3 (ITR3)
100: TI1 Edge Detector (TI1F_ED)
101: Filtered Timer Input 1 (TI1FP1)
110: Filtered Timer Input 2 (TI2FP2)
111: External trigger (ETRF)
Note: These bits must be changed only when they are not used (e.g. when
SMS=000) to avoid wrong edge detections at the transition.
3 NA Reserved, undefined
2:0 SMS[2:0] Clock/trigger/Slave mode selection
When external signals are selected the active edge of the trigger signal
(TRGI) is linked to the polarity selected on the external input (see Input
Control register and Control Register description.
000: clock/trigger controller disabled
–if CEN = ‘1’ then the prescaler is clocked directly by the internal clock.
100: Reset Mode
–Rising edge of the selected trigger input (TRGI) reinitializes the counter
and generates an update of the registers.
101: Gated Mode
–The counter clock is enabled when the trigger input (TRGI) is high. The
counter stops (but is not reset) as soon as the trigger becomes low. Both
start and stop of the counter are controlled.
110: Trigger Mode
–The counter starts at a rising edge of the trigger TRGI (but it is not
reset). Only the start of the counter is controlled.
111: External Clock Mode 1
–Rising edges of the selected trigger (TRGI) clock the counter.

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Note: The gated mode must not be used if TI1F_ED is selected as the
trigger input (TS=’100’). Indeed, TI1F_ED outputs 1 pulse for each transition
on TI1F, whereas the gated mode checks the level of the trigger signal.

Table 20-1 TIMx Internal trigger connection


Slave TIM ITR1(TS=001) ITR2(TS=010) ITR3(TS=011)
TIM15 TIM3 TIM16_OC TIM17_OC

20.5.4. TIM15 DMA/interrupt enable register(TIM15_DIER)

Address offset: 0x0C


Reset value: 0x0000
bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 — TDE COMDE — CC1DE UDE
type RO-0 RW RO-0 RO-0 RO-0 RW RW RW
7:0 BIE TIE COMIE — CC2IE CC1IE UIE
type RW RW RW RO-0 RO-0 RW RW RW

Bit Name Function


31:15 NA Reserved, undefined
14 TDE Trigger DMA request enable
0: Trigger DMA request disabled
1: Trigger DMA request enabled
13 COMDE COM DMA request enable
0: COM DMA request disabled
1: COM DMA request enabled
12:10 NA Reserved, undefined
9 CC1DE Capture/Compare 1 DMA request enable
0: CC1 DMA request disabled
1: CC1 DMA request enabled
8 UDE Update DMA request enable
0: Update DMA request disabled
1: Update DMA request enabled
7 BIE Break interrupt enable
0: Break interrupt disabled
1: Break interrupt enabled
6 TIE Trigger interrupt enable
0: Trigger interrupt disabled

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1: Trigger interrupt enabled


5 COMIE 0: COM interrupt disabled
1: COM interrupt enabled
4:3 NA Reserved, undefined
2 CC2IE Capture/Compare 2 interrupt enable
0: CC2 interrupt disabled
1: CC2 interrupt enabled
1 CC1IE Capture/Compare 1 interrupt enable
0: CC1 interrupt disabled
1: CC1 interrupt enabled
0 UIE Update interrupt enable
0: Update interrupt disabled
1: Update interrupt enabled

20.5.5. TIM15 status register(TIM15_SR)

Address offset: 0x10


Reset value: 0x0000
bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 — CC2OF CC1OF —
type RO-0 RO-0 RO-0 RO-0 RO-0 RC_W0 RC_W0 RO-0
7:0 BIF TIF COMIF — CC2IF CC1IF UIF
type RC_W0 RC_W0 RC_W0 RO-0 RO-0 RC_W0 RC_W0 RC_W0

Bit Name Function


31:11 NA Reserved, undefined
10 CC2OF Capture/Compare 2 overcapture flag. Refer to CC1OF description
9 CC1OF Capture/Compare 1 overcapture flag
This flag is set by hardware only when the corresponding channel is
configured in input capture mode. It is cleared by software by writing it to ‘0’.
0: No overcapture has been detected
1: The counter value has been captured in TIMx_CCR1 register while CC1IF
flag was already set
8 NA Reserved, undefined
7 BIF Break interrupt flag
This flag is set by hardware as soon as the break input goes active. It can be
cleared by software if the break input is not active.
0: No break event occurred
1: An active level has been detected on the break input

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6 TIF Trigger interrupt flag


This flag is set by hardware on trigger event (active edge detected on TRGI
input when the slave mode controller is enabled in all modes but gated
mode, both edges in case gated mode is selected). It is cleared by software.
0: No trigger event occurred
1: Trigger interrupt pending
5 COMIF COM interrupt flag
This flag is set by hardware on a COM event (once the capture/compare
control bits –CcxE, CcxNE, OcxM– have been updated). It is cleared by
software.
0: No COM event occurred
1: COM interrupt pending
4:3 NA Reserved, undefined
2 CC2IF Capture/Compare 2 interrupt flag refer to CC1IF description
1 CC1IF Capture/Compare 1 interrupt flag
If channel CC1 is configured as output:
This flag is set by hardware when the counter matches the compare value,
with some exception in center-aligned mode (refer to the CMS bits in the
TIMx_CR1 register description). It is cleared by software.
0: No match.
1: The content of the counter TIMx_CNT matches the content of the
TIMx_CCR1 register.
When the contents of TIMx_CCR1 are greater than the contents of
TIMx_ARR, the CC1IF bit goes high on the counter overflow (in upcounting
and up/down-counting modes) or underflow (in downcounting mode)
If channel CC1 is configured as input:
This bit is set by hardware on a capture. It is cleared by software or by
reading the TIMx_CCR1 register.
0: No input capture occurred
1: The counter value has been captured in TIMx_CCR1 register (An edge
has been detected on IC1 which matches the selected polarity)
0 UIF Update interrupt flag
This bit is set by hardware on an update event. It is cleared by software.
0: No update occurred.
1: Update interrupt pending. This bit is set by hardware when the registers
are updated:
− When counter overflows, if the UDIS=0 in the TIMx_CR1 register
− When CNT is reinitialized by software using the UG bit in TIMx_EGR
register, if URS=0 and UDIS=0 in the TIMx_CR1 register
− When CNT is reinitialized by a trigger event (refer to Section 20.5.3: TIM15
slave mode control register (TIM15_SMCR)), if URS=0 and UDIS=0 in the
TIMx_CR1 register.

20.5.6. TIM15 event generation register(TIM15_EGR)

Address offset: 0x14


Reset value: 0x0000

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bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0


31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
7:0 BG TG COMG — CC2G CC1G UG
type W W W RO-0 RO-0 W W W

Bit Name Function


31:8 NA Reserved, undefined
7 BG This bit is set by software in order to generate an event, it is automatically
cleared by hardware.
0: No action
1: A break event is generated. MOE bit is cleared and BIF flag is set. Related
interrupt or DMA transfer can occur if enabled.
6 TG Trigger generation
This bit is set by software in order to generate an event, it is automatically
cleared by hardware.
0: No action
1: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer
can occur if enabled
5 COMG Capture/Compare control update generation
This bit can be set by software, it is automatically cleared by hardware.
0: No action
1: When the CCPC bit is set, it is possible to update the CcxE、CcxNE、
CCxP、CCxNP and OCIM bits
Note: This bit acts only on channels that have a complementary output.
4:3 NA Reserved, undefined
2 CC2G Capture/Compare 2 generation Refer to CC1G description
1 CC1G Capture/Compare 1 generation
This bit is set by software in order to generate an event, it is automatically
cleared by hardware.
0: No action
1: A capture/compare event is generated on channel 1:
If channel CC1 is configured as output:
CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled.
If channel CC1 is configured as input:
The current value of the counter is captured in TIMx_CCR1 register. The
CC1IF flag is set, the corresponding interrupt or DMA request is sent if
enabled. The CC1OF flag is set if the CC1IF flag was already high.
0 UG Update generation
This bit can be set by software, it is automatically cleared by hardware.
0: No action.
1: Reinitialize the counter and generates an update of the registers. Note
that the prescaler counter is cleared too (anyway the prescaler ratio is not

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affected). The counter is cleared if the center-aligned mode is selected or if


DIR=0 (upcounting), else it takes the auto-reload value (TIMx_ARR) if
DIR=1 (downcounting).

20.5.7. TIM15 capture/compare mode register1


(TIM15_CCMR1)

Address offset: 0x18


Reset value: 0x0000
The channels can be used in input (capture mode) or in output (compare mode). The direction of a channel
is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different
function in input and in output mode. For a given bit, Ocxx describes its function when the channel is
configured in output, Icxx describes its function when the channel is configured in input. So you must take
care that the same bit can have a different meaning for the input stage and for the output stage.
Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
— OC2M[2:0] OC2PE OC2FE
15:8 CC2S[1:0]
IC2F[3:0] IC2PSC[1:0]
type RW RW RW RW RW RW RW RW
— OC1M[2:0] OC1PE OC1FE
7:0 CC1S[1:0]
IC1F[3:0] IC1PSC[1:0]
type RW RW RW RW RW RW RW RW

Output compare mode:


Bit Name Function
31:15 NA Reserved, undefined
14:12 OC2M[2:0] Output Compare 2 mode
11 OC2PE Output Compare 2 preload enable
10 OC2FE Output Compare 2 fast enable
9:8 CC2S Capture/Compare 2 selection
This bit-field defines the direction of the channel (input/output) as well as the
used input.
00: CC2 channel is configured as output.
01: CC2 channel is configured as input, IC2 is mapped on TI2.
10: CC2 channel is configured as input, IC2 is mapped on TI1.
11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode
is working only if an internal trigger input is selected through the TS bit
(TIMx_SMCR register)
Note: CC2S bits are writable only when the channel is OFF

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(CC2E=0,CC2NE=0 in the TIMx_CCER and and have been updated)


7 NA Reserved, undefined
6:4 OC1M[2:0] Output Compare 1 mode
These bits define the behavior of the output reference signal OC1REF from
which OC1 and OC1N are derived. OC1REF is active high whereas OC1
and OC1N active level depends on CC1P and CC1NP bits.
000: Frozen – The comparison between the output compare register
TIMx_CCR1 and the counter TIMx_CNT has no effect on the OC1REF;
001: Set channel 1 to active level on match. OC1REF signal is forced high
when the counter TIMx_CNT matches the capture/compare register 1
(TIMx_CCR1).
010:Set channel 1 to inactive level on match. OC1REF signal is forced low
when the counter TIMx_CNT matches the capture/compare register 1
(TIMx_CCR1).
011: Toggle – OC1REF toggles when TIMx_CNT=TIMx_CCR1.
100: Force inactive level – OC1REF is forced low.
101: Force active level – OC1REF is forced high.
110: PWM mode 1
－ In upcounting, channel 1 is active as long as TIMx_CNT<TIMx_CCR1
else inactive.
In downcounting, channel 1 is inactive (OC1REF=‘0’) as long as
TIMx_CNT>TIMx_CCR1 else active (OC1REF=’1’).
111: PWM mode 2
－ In upcounting, channel 1 is inactive as long as TIMx_CNT<TIMx_CCR1
else active.
In downcounting, channel 1 is active as long as TIMx_CNT>TIMx_CCR1
else inactive.
Note1: These bits can not be modified as long as LOCK level 3 has been
programmed (LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the
channel is configured in output).
Note2: In PWM mode 1 or 2, the OCREF level changes only when the result
of the comparison changes or when the output compare mode switches from
“frozen” mode to “PWM” mode.
Note3: On channels having a complementary output, this bit field is
preloaded. If the CCPC bit is set in the TIMx_CR2 register then the OC1M
active bits take the new value from the preloaded bits only when a COM
event is generated.
3 OC1PE Output Compare 1 preload enable
0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at
anytime, the ew value is taken in account immediately.
1: Preload register on TIMx_CCR1 enabled. Read/Write operations access
the preload egister. TIMx_CCR1 preload value is loaded in the active
register at each update event.
Note1: These bits can not be modified as long as LOCK level 3 has been
programmed (LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the
channel is configured in output).
Note2: The PWM mode can be used without validating the preload register
only in one pulse mode (OPM bit set in TIMx_CR1 register). Else the
behavior is not guaranteed

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Fremont Micro Devices FT32F0xxx8 RM

2 OC1FE Output Compare 1 fast enable


This bit is used to accelerate the effect of an event on the trigger in input on
the CC output.
0: CC1 behaves normally depending on counter and CCR1 values even
when the trigger is ON. The minimum delay to activate CC1 output when an
edge occurs on the trigger input is 5 clock cycles.
1: An active edge on the trigger input acts like a compare match on CC1
output. Then, OC is set to the compare level independently of the result of
the comparison. Delay to sample the trigger input and to activate CC1 output
is reduced to 3 clock cycles.
Note: OC1FE acts only if the channel is configured in PWM1 or PWM2
mode.
1:0 CC1S[1:0] Capture/Compare 1 selection
This bit-field defines the direction of the channel (input/output) as well as the
used input.
00: CC1 channel is configured as output.
01: CC1 channel is configured as input, IC1 is mapped on TI1.
10: CC1 channel is configured as input, IC1 is mapped on TI2.
11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode
is working only if an internal trigger input is selected through TS bit
(TIMx_SMCR register)
Note: CC1S bits are writable only when the channel is OFF (CC1E = ‘0’ in
TIMx_CCER).

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Input capture mode:


Bit Name Function
31:16 NA Reserved, undefined
15:12 IC2F[3:0] Input capture 2 filter
11:10 IC2PSC[1:0] Input capture 2 prescaler
9:8 CC2S[1:0] Capture/Compare 2 selection
This bit-field defines the direction of the channel (input/output) as well as the
used input.
00: CC2 channel is configured as output
01: CC2 channel is configured as input, IC2 is mapped on TI2
10: CC2 channel is configured as input, IC2 is mapped on TI1
11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode
is working only if an internal trigger input is selected through TS bit
(TIMx_SMCR register)
Note: CC2S bits are writable only when the channel is OFF
(CC2E=0,CC2NE=0 in the TIMx_CCER and and have been updated)
7:4 IC1F[3:0] Input capture 1 filter
This bit-field defines the frequency used to sample TI1 input and the length
of the digital filter applied to TI1. The digital filter is made of an event counter
in which N consecutive events are needed to validate a transition on the
output:
0000: No filter, sampling is done at 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐶𝐾_𝐼𝑁𝑇
0001: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐶𝐾_𝐼𝑁𝑇 , N=2
0010: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐶𝐾_𝐼𝑁𝑇 , N=4
0011: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐶𝐾_𝐼𝑁𝑇 , N=8
0100: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐷𝑇𝑆 /2, N=6
0101: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐷𝑇𝑆 /2, N=8
0110: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐷𝑇𝑆 /4, N=6
0111: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐷𝑇𝑆 /4, N=8
1000: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐷𝑇𝑆 /8, N=6
1001: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐷𝑇𝑆 /8, N=8
1010: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐷𝑇𝑆 /16, N=5
1011: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐷𝑇𝑆 /16, N=6
1100: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐷𝑇𝑆 /16, N=8
1101: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐷𝑇𝑆 /32, N=5
1110: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐷𝑇𝑆 /32, N=6
1111: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐷𝑇𝑆 /32, N=8
3:2 IC1PSC[1:0] Input capture 1 prescaler
This bit-field defines the ratio of the prescaler acting on CC1 input (IC1).
The prescaler is reset as soon as CC1E=’0’ (TIMx_CCER register).
00: no prescaler, capture is done each time an edge is detected on the
capture input
01: capture is done once every 2 events
10: capture is done once every 4 events
11: capture is done once every 8 events
1:0 CC1S[1:0] Capture/Compare 1 Selection
This bit-field defines the direction of the channel (input/output) as well as the
used input.

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Fremont Micro Devices FT32F0xxx8 RM

00: CC1 channel is configured as output


01: CC1 channel is configured as input, IC1 is mapped on TI1
10: CC1 channel is configured as input, IC1 is mapped on TI2
11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode
is working only if an internal trigger input is selected through TS bit
(TIMx_SMCR register)
Note: CC1S bits are writable only when the channel is OFF (CC1E = ‘0’ in
TIMx_CCER).

20.5.8. TIM15 capture/compare enable register(TIM15_CCER)

Address offset: 0x20


Reset value: 0x0000
bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
7:0 CC2NP — CC2P CC2E CC1NP CC1NE CC1P CC1E
type RW RO-0 RW RW RW RW RW RW

Bit Name Function


31:8 NA Reserved, undefined
7 CC2NP Capture/Compare 2 complementary output polarity
refer to CC1NP description
6 NA Reserved, undefined
5 CC2P Capture/Compare 2 output polarity. Refer to CC1P description
4 CC2E Capture/Compare 2 output enable. Refer to CC1E description
3 CC1NP Capture/Compare 1 complementary output polarity
CC1 channel configuration as output:
0: OC1N active high
1: OC1N active low
CC1 channel configuration as input:
This bit is used in conjunction with CC1P to define the polarity of TI1FP1 and
TI2FP1. Refer to CC1P description.
Note1: This bit is not writable as soon as LOCK level 2 or 3 has been
programmed (LOCK bits in TIMx_BDTR register) and CC1S=”00” (the channel is
configured in output).
Note2: On channels having a complementary output, this bit is preloaded. If the
CCPC bit is set in the TIMx_CR2 register then the CC1NP active bit takes the
new value from the
preloaded bits only when a Commutation event is generated.
2 CC1NE Capture/Compare 1 complementary output enable

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0: Off
－ OC1N is not active. OC1N level is then function of MOE, OSSI, OSSR, OIS1,
OIS1N and CC1E bits.
1: On
－ OC1N signal is output on the corresponding output pin depending on MOE,
OSSI, OSSR, OIS1, OIS1N and CC1E bits.
Note: On channels having a complementary output, this bit is preloaded. If the
CCPC bit is set in the TIMx_CR2 register then the CC1NE active bit takes the
new value from the preloaded bits only when a Commutation event is generated.
1 CC1P Capture/Compare 1 output polarity
CC1 channel configured as output:
0: OC1 active high
1: OC1 active low
CC1 channel configured as input:
The CC1NP/CC1P bits select the polarity of TI1FP1 and TI2FP1 for trigger or
capture operations.
00: noninverted/rising edge
circuit is sensitive to TixFP1’s rising edge (capture, trigger in reset or trigger
mode), TixFP1 is not inverted (in gated mode).
01: inverted/falling edge
circuit is sensitive to TixFP1’s falling edge (capture, trigger in reset,
or trigger mode), TixFP1 is inverted (in gated mode ).
10: reserved, do not use this configuration.
11: noninverted/both edges
The circuit is sensitive to both TixFP1 rising and falling edges((capture, trigger in
reset or trigger mode), TixFP1is not inverted (in gated mode ).
Note1: This bit is not writable as soon as LOCK level 2 or 3 has been
programmed (LOCK bits in TIMx_BDTR register).
Note2: On channels having a complementary output, this bit is preloaded. If the
CCPC bit is set in the TIMx_CR2 register then the CC1P active bit takes the new
value from the preloaded bits only when a Commutation event is generated
0 CC1E Capture/Compare 1 output enable
CC1 channel configured as output:
0: Off
－ OC1 is not active. OC1 level is then function of MOE, OSSI, OSSR, OIS1,
OIS1N and CC1NE bits.
1: On
－ OC1 signal is output on the corresponding output pin depending on MOE,
OSSI, OSSR, OIS1, OIS1N and CC1NE bits.
CC1 channel configured as input:
This bit determines if a capture of the counter value can actually be done into the
input capture/compare register 1 (TIMx_CCR1) or not.
0: Capture disabled.
1: Capture enabled.
Note: On channels having a complementary output, this bit is preloaded. If the
CCPC bit is set in the TIMx_CR2 register then the CC1E active bit takes the new
value from the preloaded bits only when a Commutation event is generated.

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Fremont Micro Devices FT32F0xxx8 RM

Table 20-2 Output control bits for complementary Ocx and OcxN channels with break feature
Control bits Output states(1)
MOE OSSI OSSR CcxE CcxNE Ocx output state OcxN output state
Output Disabled (not driven Output Disabled (not driven
0 0 0 by the timer) by the timer)
Ocx=0, Ocx_EN=0 OcxN=0, OcxN_EN=0
Output Disabled (not driven OCxREF + Polarity
0 0 1 by the timer) OcxN=OCxREF ^ CCxNP
Ocx=0, Ocx_EN=0 OcxN_EN=1
OCxREF + Polarity Output Disabled (not driven
0 1 0 Ocx=OCxREF ^ CCxNP by the timer)
Ocx_EN=1 OcxN=0, OcxN_EN=0
Complementary to OCxREF +
OCxREF + Polarity + deadtime
0 1 1 Polarity + deadtime
Ocx_EN=1
OcxN_EN=1
1 X
Output Disabled (not driven Output Disabled (not driven
1 0 0 by the timer) by the timer)
Ocx=CCxP, Ocx_EN=0 OcxN=CCxNP,OcxN_EN=0
Off-State (output enabled with OCxREF + Polarity
1 0 1 run mode) OcxN=OCxREF ^ CCxNP
Ocx=CCxP, Ocx_EN=1 OcxN_EN=1
OCxREF + Polarity Off-State (output enabled with run
1 1 0 Ocx=OCxREF ^ T1CCxNP mode)
Ocx_EN=1 OcxN=T1CCxNP, Ocx_EN=1
Complementary to OCxREF +
OCxREF + Polarity + deadtime
1 1 1 Polarity + deadtime
Ocx_EN=1
OcxN_EN=1
Output Disabled (not driven Output Disabled (not driven
0 0 0 by the timer) by the timer)
Ocx=CCxP, Ocx_EN=0 OcxN=CCxNP,OcxN_EN=0
0 0 1 Output Disabled (not driven by the timer)
0 1 0 Asynchronously: Ocx=CCxP, Ocx_EN=0, OcxN=CCxNP,
OcxN_EN=0
Then if the clock is present: Ocx=OISx and OcxN=OISxN after a
0 1 1
dead-time, assuming that OISx and OISxN do not correspond to OCX
0 X and OcxN both in active state.
Output Disabled (not driven Output Disabled (not driven
1 0 0 by the timer) by the timer)
Ocx=CCxP, Ocx_EN=0 OcxN=CCxNP,OcxN_EN=0
1 0 1 Off-State (output enabled with inactive state)
1 1 0 Asynchronously:Ocx=CCxP,Ocx_EN=1,OcxN=CCxNP,OcxN_EN=1
Then if the clock is present: Ocx=OISx and OcxN=OISxN
1 1 1 after a dead-time, assuming that OISx and OISxN do not
correspond to OCX and OcxN both in active state
（1） When both outputs of a channel are not used (CcxE = CcxNE = 0), the OISx, OISxN, CCxP and

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CCxNP bits must be kept cleared.


Note:The state of the external I/O pins connected to the complementary Ocx and OcxN channels depends
on the Ocx and OcxN channel state and the GPIO and AFIO registers.

20.5.9. TIM15 counter(TIM15_CNT)

Address offset: 0x24


Reset value: 0x0000
bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 CNT[15:8]
type RW RW RW RW RW RW RW RW
7:0 CNT[7:0]
type RW RW RW RW RW RW RW RW

Bit Name Function


31:16 NA Reserved, undefined
15:0 CNT[15:0] Counter value

20.5.10. TIM15 prescaler(TIM15_PSC)

Address offset: 0x28


Reset value: 0x0000
bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 PSC[15:8]
type RW RW RW RW RW RW RW RW
7:0 PSC[7:0]
type RW RW RW RW RW RW RW RW

Bit Name Function


31:16 NA Reserved, undefined
15:0 PSC[15:0] Prescaler value
The counter clock frequency (CK_CNT) is equal to 𝑓𝐶𝐾_𝑃𝑆𝐶 /(PSC[15:0]+1).
PSC contains the value to be loaded in the active prescaler register at each
update event

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20.5.11. TIM15 auto-reload register(TIM15_ARR)

Address offset: 0x2C


Reset value: 0xFFFF
bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 ARR[15:8]
type RW RW RW RW RW RW RW RW
7:0 ARR[7:0]
type RW RW RW RW RW RW RW RW

Bit Name Function


31:16 NA Reserved, undefined
15:0 ARR[15:0] Auto-reload value
ARR is the value to be loaded in the actual auto-reload register.
The counter is blocked while the auto-reload value is null.

20.5.12. TIM15 repetition counter register(TIM15_RCR)

Address offset: 0x30


Reset value: 0x0000
bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
7:0 REP[7:0]
type RW RW RW RW RW RW RW RW

Bit Name Function


31:8 NA Reserved, undefined
7:0 REP[7:0] Repetition counter value
These bits allow the user to set-up the update rate of the compare registers
(i.e. periodic transfers from preload to active registers) when preload
registers are enable, as well as the update interrupt generation rate, if this
interrupt is enable.
Each time the REP_CNT related downcounter reaches zero, an update

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event is generated and it restarts counting from REP value. As REP_CNT is


reloaded with REP value only at the repetition update event U_RC, any write
to the TIMx_RCR register is not taken in account until the next repetition
update event.
It means in PWM mode (REP+1) corresponds to the number of PWM
periods in edge-aligned mode.

20.5.13. TIM15 capture/compare register 1(TIM15_CCR1)

Address offset: 0x34


Reset value: 0x0000
bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 CCR1[15:8]
type RW RW RW RW RW RW RW RW
7:0 CCR1[7:0]
type RW RW RW RW RW RW RW RW

Bit Name Function


31:16 NA Reserved, undefined
15:0 CCR1[15:0] Capture/Compare 1 value
If channel CC1 is configured as output:
CCR1 is the value to be loaded in the actual capture/compare 1 register
(preload value). It is loaded permanently if the preload feature is not selected
in the TIMx_CCMR1 register (bit OC1PE). Else the preload value is copied
in the active capture/compare 1 register when an update event occurs.
The active capture/compare register contains the value to be compared to
the counter TIMx_CNT and signaled on OC1 output.

If channel CC1 is configured as input:


CCR1 is the counter value transferred by the last input capture 1 event (IC1).

20.5.14. TIM15 capture/compare register 2 (TIM15_CCR2)

Address offset: 0x38


Reset value: 0x0000
bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —

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type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0


15:8 CCR2[15:8]
type RW RW RW RW RW RW RW RW
7:0 CCR2[7:0]
type RW RW RW RW RW RW RW RW

Bit Name Function


31:16 NA Reserved, undefined
15:0 CCR2[15:0] Capture/Compare 2 value
If channel CC2 is configured as output:
CCR2 is the value to be loaded in the actual capture/compare 2 register
(preload value). It is loaded permanently if the preload feature is not selected
in the TIMx_CCMR2 register (bit OC2PE). Else the preload value is copied
in the active capture/compare 2 register when an update event occurs. The
active capture/compare register contains the value to be compared to the
counter TIMx_CNT and 418ffectiv on OC2 output.
If channel CC2 is configured as input:
CCR2 is the counter value transferred by the last input capture 2 event (IC2).

20.5.15. TIM15 break and dead-time register(TIM15_BDTR)

Address offset: 0x44


Reset value: 0x0000
bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 MOE AOE BKP BKE OSSR OSSI LOCK[1:0]
type RW RW RW RW RW RW RW RW
7:0 DTG[7:0]
type RW RW RW RW RW RW RW RW

Bit Name Function


31:16 NA Reserved, undefined
15 MOE Main output enable
This bit is cleared asynchronously by hardware as soon as the break input is
active. It is set by software or automatically depending on the AOE bit. It is
acting only on the channels which are configured in output.
0: Ocx and OcxN outputs are disabled or forced to idle state
1: Ocx and OcxN outputs are enabled if their respective enable bits are set
(CcxE in TIMx_CCER register)
14 AOE Automatic output enable
0: MOE can be set only by software

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1: MOE can be set by software or automatically at the next update event (if
the break input is not be active)
Note: This bit can not be modified as long as LOCK level 1 has been
programmed (LOCK bits in TIMx_BDTR register).
13 BKP Break polarity
0: Break input BRK is active low
1: Break input BRK is active high
Note: This bit can not be modified as long as LOCK level 1 has been
programmed (LOCK bits in TIMx_BDTR register).
Note: Any write operation to this bit takes a delay of 1 APB clock cycle to
become effective
12 BKE Break enable
0: Break inputs (BRK and internal break sources) disabled
1: Break inputs (BRK and internal break sources) enabled
Note: This bit cannot be modified when LOCK level 1 has been programmed
(LOCK bits in TIMx_BDTR register).
Note: Any write operation to this bit takes a delay of 1 APB clock cycle to
become effective.
11 OSSR Off-state selection for Run mode
This bit is used when MOE=1 on channels having a complementary output
which are configured as outputs.
0: When inactive, Ocx/OcxN outputs are disabled (Ocx/OcxN enable output
signal =0)
1: When inactive, Ocx/OcxN outputs are enabled with their inactive level as
soon as CcxE=1 or CcxNE=1. Then, Ocx/OcxN enable output signal=1.
Note: This bit can not be modified as soon as the LOCK level 2 has been
programmed (LOCK bits in TIMx_BDTR register).
10 OSSI Off-state selection for Idle mode
This bit is used when MOE=0 on channels configured as outputs.
0: When inactive, Ocx/OcxN outputs are disabled (Ocx/OcxN enable output
signal=0).
1: When inactive, Ocx/OcxN outputs are forced first with their idle level as
soon as CcxE=1 or CcxNE=1. Ocx/OcxN enable output signal=1)
Note: This bit can not be modified as soon as the LOCK level 2 has been
programmed (LOCK bits in TIMx_BDTR register).
9:8 LOCK Lock configuration
These bits offer a write protection against software errors.
00: LOCK OFF – No bit is write protected
01: LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits
in TIMx_CR2 register and BKE/BKP/AOE bits in TIMx_BDTR register can no
longer be written
10: LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in
TIMx_CCER register, as long as the related channel is configured in output
through the CCxS bits) as well as OSSR and OSSI bits can no longer be
written.
11: LOCK Level 3 = LOCK Level 2 + CC Control bits (OcxM and OcxPE bits
in TIMx_CCMRx registers, as long as the related channel is configured in

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output through the CCxS bits) can no longer be written.


Note: The LOCK bits can be written only once after the reset. Once the
TIMx_BDTR register has been written, their content is frozen until the next
reset.
7:0 DTG[7:0] Dead-time generator setup
This bit-field defines the duration of the dead-time inserted between the
complementary outputs. DT correspond to this duration.
DTG[7:5]=0xx => DT=DTG[7:0]* tdtg, with tdtg=tDTS
DTG[7:5]=10x => DT=(64+DTG[5:0]) * tdtg, with tdtg= 2*tDTS
DTG[7:5]=110 => DT=(32+DTG[4:0]) * tdtg, with tdtg=8* tDTS
DTG[7:5]=111 => DT=(32+DTG[4:0]) * tdtg, with tdtg= 16*tDTS
Example if tDTS=125ns (8MHz), dead-time possible values are:
DTG[7:0] = 0~7Fh, 0 to 15875 ns by 125 ns steps
DTG[7:0] = 80h~BFh, 16 μs to 31750 ns by 250 ns steps
DTG[7:0] = C0h~DFh, 32 μs to 63 μs by 1 μs steps
DTG[7:0] = E0h~FFh, 64 μs to 126 μs by 2 μs steps
Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has
been programmed (LOCK bits in TIMx_BDTR register).

20.5.16. TIM15 DMA control register(TIM15_DCR)

Address offset: 0x48


Reset value: 0x0000
bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 — DBL[4:0]
type RO-0 RO-0 RO-0 RW RW RW RW RW
7:0 — DBA[4:0]
type RO-0 RO-0 RO-0 RW RW RW RW RW

Bit Name Function


31:13 NA Reserved, undefined
12:8 DBL[4:0] DMA burst length
This 5-bit vector defines the length of DMA transfers (the timer recognizes a
burst transfer when a read or a write access is done to the TIMx_DMAR
address).
00000: 1 transfer,
00001: 2 transfers,
00010: 3 transfers,
...
10001: 18 transfers.

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7:5 NA Reserved, undefined


4:0 DBA[4:0] DMA base address
This 5-bits vector defines the base-address for DMA transfers (when
read/write access are done through the TIMx_DMAR address). DBA is
defined as an offset starting from the address of the TIMx_CR1 register.
Example:
00000: TIMx_CR1,
00001: TIMx_CR2,
00010: TIMx_SMCR,
...
Example:Let us consider the following transfer: DBL=7, DBA=TIMx_CR1
In this case the transfer is done to/from 7 registers starting from the
TIMx_CR1 address.

20.5.17. TIM15 address for full transfer(TIM15_DMAR)

Address offset: 0x4C


Reset value: 0x0000
bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 DMAB[15:8]
type RW RW RW RW RW RW RW RW
7:0 DMAB[7:0]
type RW RW RW RW RW RW RW RW

Bit Name Function


31:16 NA Reserved, undefined
15:0 DMAB[15:0] DMA register for burst accesses
A read or write operation to the DMAR register accesses the register located
at the address (TIMx_CR1 address) + (DBA + DMA index) x 4
where TIMx_CR1 address is the address of the control register 1, DBA is the
DMA base address configured in TIMx_DCR register, DMA index is
automatically controlled by the DMA transfer, and ranges from 0 to DBL
(DBL configured in TIMx_DCR).

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Example of how to use the DMA burst feature


In this example the timer DMA burst feature is used to update the contents of the CCRx registers (x = 2, 3, 4)
with the DMA transferring half words into the CCRx registers.
This is done in the following steps:
1. Configure the corresponding DMA channel as follows:
− DMA channel peripheral address is the DMAR register address
− DMA channel memory address is the address of the buffer in the RAM containing the data to be
transferred by DMA into CCRx registers.
− Number of data to transfer = 3
− Circular mode disabled.
2. Configure the DCR register by configuring the DBA and DBL bit fields: DBL=3, DMA burst length of the
transfer is 3 , DBA=0xE, the initial transfer address offset is 0x38(TIMx_CCR2).
3. Enable the TIMx update DMA request
4. Enable TIMx
5. Enable the DMA channel
Note:This example is for the case where every CCRx register to be updated once. If every CCRx register is
to be updated twice for example, the number of data to transfer should be 6. Let us take the example of a
buffer in the RAM containing data1, data2, data3, data4, data5 and data6. The data is transferred to the
CCRx registers as follows: on the first update DMA request, data1 is transferred to CCR2, data2 is
transferred to CCR3, data3 is transferred to CCR4 and on the second update DMA request, data4 is
transferred to CCR2, data5 is transferred to CCR3 and data6 is transferred to CCR4.

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20.6. TIM16 and TIM17 register map

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10
Address offset Name

0
CKD[1:0]

ARPE

UDIS
OPM

URS

CEN
TIMx_CR1
–

–
0x00

Reset x x x x x x x x x x x x x x x x x x x x x x 0 0 0 x x x 0 0 0 0

OIS1N

CCDS

CCPC
OIS1
TIMx_CR2
–

–
0x04

Reset x x x x x x x x x x x x x x x x x x x x x x 1 1 x x x x 0 x x 0

COMIE
CC1DE

CC1IE
UDE

UIE
BIE
TIMx_DIER
–

–
0x0C

Reset x x x x x x x x x x x x x x x x x x x x x x 0 0 0 x 0 x x x 0 0

CC1OF

COMIF

CC1IF

UIF
BIF
TIMx_SR
–

–
0x10

Reset x x x x x x x x x x x x x x x x x x x x x x 0 x 0 x 0 x x x 0 0

COMG

CC1G
BG

UG
TIMx_EGR
–

–
0x14

Reset x x x x x x x x x x x x x x x x x x x x x x x x 0 x 0 x x x 0 0

CC1S[1:0]
TIMx_CCMR

CC1PE

CC1FE
1 OC1M[2:0]
–

–
(output mode)

Reset x x x x x x x x x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0
0x18

CC2S[1:0]

CC1S[1:0]
IC2F[3:0]

IC1F[3:0]
TIMx_CCMR
IC2PSC IC1PSC
1
–

[1:0] [1:0]
(input mode)

Reset x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CC1NP

CC1NE

CC1P

CC1E
TIMx_CCER
–

–
0x20

Reset x x x x x x x x x x x x x x x x x x x x x x x x x x x x 0 0 0 0

TIMx_CNT CNT[15:0]
–

0x24

Reset x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TIMx_PSC PSC[15:0]
–

0x28

Reset x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TIMx_ARR ARR[15:0]
–

0x2C

Reset x x x x x x x x x x x x x x x x 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

TIMx_RCR REP[7:0]
–

0x30

Reset x x x x x x x x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0

TIMx_CCR1 CCR1[15:0]
–

0x34

Reset x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
LOCK[1:0]
OSSR
MOE

OSSI
AOE

BKP

BKE

TIM15_BDTR DTG[7:0]
–

0x44

Reset x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

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TIMx_DCR DBL[4:0] DBA[4:0]

–
0x48

Reset x x x x x x x x x x x x x x x x x x x 0 0 0 0 0 x x x 0 0 0 0 0

TIMx_DMAR – DMAB[15:0]

–
0x4C

Reset x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

20.6.1. TIM16 and TIM17 control register 1(TIM16_CR1 and


TIM17_CR1)

Address offset: 0x00


Reset value: 0x0000
bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 — CKD[1:0]
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RW RW
7:0 ARPE — OPM URS UDIS CEN
type RW RO-0 RO-0 RO-0 RW RW RW RW

Bit Name Function


31:10 NA Reserved, undefined
9:8 CKD[1:0] Clock division
This bit-field indicates the division ratio between the timer clock (CK_INT)
frequency and the dead-time and sampling clock ( 𝑡𝐷𝑇𝑆 )used by the
dead-time generators and the digital filters (ETR、Tix).
00: 𝑡𝐷𝑇𝑆 = 𝑡𝐶𝐾_𝐼𝑁𝑇
01: 𝑡𝐷𝑇𝑆 = 2 ∗ 𝑡𝐶𝐾_𝐼𝑁𝑇
10: 𝑡𝐷𝑇𝑆 = 4 ∗ 𝑡𝐶𝐾_𝐼𝑁𝑇
11: Reserved, do not program this value
7 ARPE Auto-reload preload enable
0: TIMx_ARR register is not buffered and it can be written directly
1: TIMx_ARR register is buffered
6:5 NA Reserved, undefined
4 DIR Direction
0: Counter used as upcounter
1: Counter used as downcounter
3 OPM One pulse mode
0: Counter is not stopped at update event
1: Counter stops counting at the next update event (clearing the bit CEN)

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2 URS Update request source


This bit is set and cleared by software to select the UEV event sources.
0: if UDIS allows to generate an update event, Any of the following events
generate an update interrupt or DMA request if enabled.
− Counter overflow
− Setting the UG bit
− Update generation by reset trigger
1: Only counter overflow/underflow generates an update interrupt or DMA
request if enabled.
1 UDIS Update disable
This bit is set and cleared by software to enable/disable UEV event
generation.
0: UEV enabled. The Update (UEV) event is generated by one of the
following events
− Counter overflow/underflow
− Setting the UG bit
− Update generation by reset trigger
1: UEV disabled. The Update event is not generated, shadow registers keep
their value (ARR, PSC, CCRx). However the counter and the prescaler are
reinitialized if the UG bit is set or if a trigger event occurred in reset mode.
0 CEN Counter enable
0: Counter disabled
1: Counter enabled
Note: External clock, gated mode and encoder mode can work only if the
CEN bit has been previously set by software. However trigger mode can set
the CEN bit automatically by hardware.

20.6.2. TIM16 and TIM17control register 2(TIM16_CR2 and


TIM17_CR2)

Address offset: 0x04


Reset value: 0x0000
bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 — OIS1N OIS1
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RW RW
7:0 — CCDS — CCPC
type RO-0 RO-0 RO-0 RO-0 RW RO-0 RO-0 RW

Bit Name Function


31:10 NA Reserved, undefined

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9 OIS1N Output Idle state 1 (OC1N output)


0: OC1N=0 after a dead-time when MOE=0
1: OC1N=1 after a dead-time when MOE=0
Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been
programmed (LOCK bits in TIMx_BKR register)
8 OIS1 Output Idle state 1 (OC1 output)
0: OC1=0 (after a dead-time if OC1N is implemented) when MOE=0
1: OC1=1 (after a dead-time if OC1N is implemented) when MOE=0
Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been
programmed (LOCK bits in TIMx_BKR register).
7:4 NA Reserved, undefined
3 CCDS Capture/compare DMA selection
0: CCx DMA request sent when CCx event occurs
1: CCx DMA requests sent when update event occurs
2:1 NA Reserved, undefined
0 CCPC Capture/compare preloaded control
0: CcxE, CcxNE, CCxP, CCxNP and OcxM bits are not preloaded
1: CcxE, CcxNE, CCxP, CCxNP and OcxM are preloaded, after having been
written, they are updated only when COMG bit set or rising edge detected on
TRGI, depending on the CCUS bit)
Note: This bit acts only on channels that have a complementary output.

20.6.3. TIM16 and TIM17 DMA/ interrupt enable


register(TIM16_DIER and TIM17_DIER)

Address offset: 0x0C


Reset value: 0x0000
bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 — CC1DE UDE
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RW RW
7:0 BIE — COMIE — CC1IE UIE
type RW RO-0 RW RO-0 RO-0 RO-0 RW RW

Bit Name Function


31:10 NA Reserved, undefined
9 CC1DE Capture/Compare 1 DMA request enable
0: CC1 DMA request disabled
1: CC1 DMA request enabled
8 UDE Update DMA request enable

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Fremont Micro Devices FT32F0xxx8 RM

0: Update DMA request disabled


1: Update DMA request enabled
7 BIE Break interrupt enable
0: Break interrupt disabled
1: Break interrupt enabled
6 NA Reserved, undefined
5 COMIE 0: COM interrupt disabled
1: COM interrupt enabled
4:2 NA Reserved, undefined
1 CC1IE Capture/Compare 1 interrupt enable
0: CC1 interrupt disabled
1: CC1 interrupt enabled
0 UIE Update interrupt enable
0: Update interrupt disabled
1: Update interrupt enabled

20.6.4. TIM16 and TIM17 status register(TIM16_SR and


TIM17_SR)

Address offset: 0x10


Reset value: 0x0000
bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 — CC1OF —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RC_W0 RO-0
7:0 BIF — COMIF — CC1IF UIF
type RC_W0 RO-0 RC_W0 RO-0 RO-0 RO-0 RC_W0 RC_W0

Bit Name Function


31:10 NA Reserved, undefined
9 CC1OF Capture/Compare 1 overcapture flag
This flag is set by hardware only when the corresponding channel is
configured in input capture mode. It is cleared by software by writing it to ‘0’.
0: No overcapture has been detected
1: The counter value has been captured in TIMx_CCR1 register while CC1IF
flag was already set
8 NA Reserved, undefined
7 BIF Break interrupt flag
This flag is set by hardware as soon as the break input goes active. It can be

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Fremont Micro Devices FT32F0xxx8 RM

cleared by software if the break input is not active.


0: No break event occurred
1: An active level has been detected on the break input
6 NA Reserved, undefined
5 COMIF COM interrupt flag
This flag is set by hardware on a COM event (once the capture/compare
control bits –CcxE, CcxNE, OcxM– have been updated). It is cleared by
software.
0: No COM event occurred
1: COM interrupt pending
4:2 NA Reserved, undefined
1 CC1IF Capture/Compare 1 interrupt flag
If channel CC1 is configured as output:
This flag is set by hardware when the counter matches the compare value,
with some exception in center-aligned mode (refer to the CMS bits in the
TIMx_CR1 register description). It is cleared by software.
0: No match.
1: The content of the counter TIMx_CNT matches the content of the
TIMx_CCR1 register. When the contents of TIMx_CCR1 are greater than
the contents of TIMx_ARR, the CC1IF bit goes high on the counter overflow
(in upcounting and up/down-counting modes) or underflow (in downcounting
mode)
If channel CC1 is configured as input:
This bit is set by hardware on a capture. It is cleared by software or by
reading the TIMx_CCR1 register.
0: No input capture occurred
1: The counter value has been captured in TIMx_CCR1 register (An edge
has been detected on IC1 which matches the selected polarity)
0 UIF Update interrupt flag
This bit is set by hardware on an update event. It is cleared by software.
0: No update occurred.
1: Update interrupt pending. This bit is set by hardware when the registers
are updated:
− When counter overflows, if the UDIS=0 in the TIMx_CR1 register
− When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if
URS=0 and UDIS=0 in the TIMx_CR1 register.
− When CNT is reinitialized by a trigger event (refer to Section slave mode control
register (TIMx_SMCR)), if URS=0 and UDIS=0 in the TIMx_CR1 register.

20.6.5. TIM16 and TIM17 event generation register(TIM16_EGR


and TIM17_EGR)

Address offset: 0x14


Reset value: 0x0000
bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —

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type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0


23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
7:0 BG — COMG — CC1G UG
type W RO-0 W RO-0 RO-0 RO-0 W W

Bit Name Function


31:8 NA Reserved, undefined
7 BG Break generation
This bit is set by software in order to generate an event, it is automatically
cleared by hardware.
0: No action.
1: A break event is generated. MOE bit is cleared and BIF flag is set. Related
interrupt or DMA transfer can occur if enabled.
6 NA Reserved, undefined
5 COMG Capture/Compare control update generation
This bit can be set by software, it is automatically cleared by hardware.
0: No action
1: When the CCPC bit is set, it is possible to update the CcxE、CcxNE、
CCxP、CCxNP and OCIM bits
Note: This bit acts only on channels that have a complementary output.
4:2 NA Reserved, undefined
1 CC1G Capture/Compare 1 generation
This bit is set by software in order to generate an event, it is automatically
cleared by hardware.
0: No action.
1: A capture/compare event is generated on channel 1:
If channel CC1 is configured as output:
CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled.
If channel CC1 is configured as input:
The current value of the counter is captured in TIMx_CCR1 register. The
CC1IF flag is set, the corresponding interrupt or DMA request is sent if
enabled. The CC1OF flag is set if the CC1IF flag was already high.
0 UG Update generation
This bit can be set by software, it is automatically cleared by hardware.
0: No action.
1: Reinitialize the counter and generates an update of the registers.
Note that the prescaler counter is cleared too (anyway the prescaler ratio is
not affected). The counter is cleared if the center-aligned mode is selected
or if DIR=0 (upcounting), else it takes the auto-reload value (TIMx_ARR) if
DIR=1 (downcounting).

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20.6.6. TIM16 and TIM17 capture/compare mode register


1(TIM16_CCMR1 and TIM17_CCMR1)

Address offset: 0x18


Reset value: 0x0000
The channels can be used in input (capture mode) or in output (compare mode). The direction of a channel
is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different
function in input and in output mode. For a given bit, Ocxx describes its function when the channel is
configured in output, Icxx describes its function when the channel is configured in input. So you must take
care that the same bit can have a different meaning for the input stage and for the output stage.
Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
— OC1M[2:0] OC1PE OC1FE
7:0 CC1S[1:0]
IC1F[3:0] IC1PSC[1:0]
type RW RW RW RW RW RW RW RW

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Output compare mode:


Bit Name Function
31:7 NA Reserved, undefined
6:4 OC1M[2:0] Output Compare 1 mode
These bits define the behavior of the output reference signal OC1REF from
which OC1 and OC1N are derived. OC1REF is active high whereas OC1
and OC1N active level depends on CC1P and CC1NP bits.
000: Frozen – The comparison between the output compare register
TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs.
001: Set channel 1 to active level on match. OC1REF signal is forced high
when the counter TIMx_CNT matches the capture/compare register 1
(TIMx_CCR1).
010: Set channel 1 to inactive level on match. OC1REF signal is forced low
when the counter TIMx_CNT matches the capture/compare register 1
(TIMx_CCR1).
011: Toggle – OC1REF toggles when TIMx_CNT=TIMx_CCR1.
100: Force inactive level – OC1REF is forced low.
101: Force active level – OC1REF is forced high.
110: PWM mode 1
－ In upcounting, channel 1 is active as long as TIMx_CNT<TIMx_CCR1
else inactive.
In downcounting, channel 1 is inactive (OC1REF=‘0’) as long as
TIMx_CNT>TIMx_CCR1 else active (OC1REF=’1’).
111: PWM mode 2
－ In upcounting, channel 1 is inactive as long as TIMx_CNT<TIMx_CCR1
else active.
In downcounting, channel 1 is active as long as TIMx_CNT>TIMx_CCR1
else inactive.
Note1: These bits can not be modified as long as LOCK level 3 has been
programmed (LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the
channel is configured in output).
Note2: In PWM mode 1 or 2, the OCREF level changes only when the result
of the comparison changes or when the output compare mode switches from
“frozen” mode to “PWM” mode.
Note3: On channels having a complementary output, this bit field is
preloaded. If the CCPC bit is set in the TIMx_CR2 register then the OC1M
active bits take the new value from the preloaded bits only when a COM
event is generated.
3 OC1PE Output Compare 1 preload enable
0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at
anytime, the new value is taken in account immediately.
1: Preload register on TIMx_CCR1 enabled. Read/Write operations access
the preload register. TIMx_CCR1 preload value is loaded in the active
register at each update event.
Note1: These bits can not be modified as long as LOCK level 3 has been
programmed (LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the
channel is configured in output).
Note2: The PWM mode can be used without validating the preload register
only in one pulse mode (OPM bit set in TIMx_CR1 register). Else the

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behavior is not guaranteed


2 OC1FE Output Compare 1 fast enable
This bit is used to accelerate the effect of an event on the trigger in input on
the CC output.
0: CC1 behaves normally depending on counter and CCR1 values even
when the trigger is ON. The minimum delay to activate CC1 output when an
edge occurs on the trigger input is 5 clock cycles.
1: An active edge on the trigger input acts like a compare match on CC1
output. Then, OC is set to the compare level independently of the result of
the comparison. Delay to sample the trigger input and to activate CC1 output
is reduced to 3 clock cycles.
OC1FE acts only if the channel is configured in PWM1 or PWM2 mode.
1:0 CC1S[1:0] Capture/Compare 1 selection
This bit-field defines the direction of the channel (input/output) as well as the
used input.
00: CC1 channel is configured as output
01: CC1 channel is configured as input, IC1 is mapped on TI1
10: Reserved
11: Reserved
Note: CC1S bits are writable only when the channel is OFF (CC1E = ‘0’ in
TIMx_CCER).

Input capture mode


Bit Name Function
31:16 NA Reserved, undefined
15:12 IC2F[3:0] Input capture 2 filter
11:10 IC2PSC[1:0] Input capture 2 prescaler
9:8 CC2S[1:0] Capture/Compare 2 selection
This bit-field defines the direction of the channel (input/output) as well as the
used input.
00: CC2 channel is configured as output
01: CC2 channel is configured as input, IC2 is mapped on TI2
10: CC2 channel is configured as input, IC2 is mapped on TI1
11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode
is working only if an internal trigger input is selected through TS bit
(TIMx_SMCR register)
Note: CC2S bits are writable only when the channel is OFF (CC2E=0 and
CC2NE=0 in TIMx_CCER and have been updated)
7:4 IC1F[3:0] Input capture 1 filter
This bit-field defines the frequency used to sample TI1 input and the length
of the digital filter applied to TI1. The digital filter is made of an event counter
in which N consecutive events are needed to validate
a transition on the output:
0000: No filter, sampling is done at 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓C𝐾_𝐼𝑁𝑇
0001: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐶𝐾_𝐼𝑁𝑇 , N=2
0010: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐶𝐾_𝐼𝑁𝑇 , N=4
0011: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐶𝐾_𝐼𝑁𝑇 , N=8
0100: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐷𝑇𝑆 /2, N=6

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0101: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐷𝑇𝑆 /2, N=8


0110: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐷𝑇𝑆 /4, N=6
0111: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐷𝑇𝑆 /4, N=8
1000: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐷𝑇𝑆 /8, N=6
1001: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐷𝑇𝑆 /8, N=8
1010: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐷𝑇𝑆 /16, N=5
1011: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐷𝑇𝑆 /16, N=6
1100: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐷𝑇𝑆 /16, N=8
1101: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐷𝑇𝑆 /32, N=5
1110: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐷𝑇𝑆 /32, N=6
1111: 𝑓𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 = 𝑓𝐷𝑇𝑆 /32, N=8
3:2 IC1PSC[1:0] Input capture 1 prescaler
This bit-field defines the ratio of the prescaler acting on CC1 input (IC1).
The prescaler is reset as soon as CC1E=’0’ (TIMx_CCER register).
00: no prescaler, capture is done each time an edge is detected on the
capture input
01: capture is done once every 2 events
10: capture is done once every 4 events
11: capture is done once every 8 events
1:0 CC1S[1:0] Capture/Compare 1 Selection
This bit-field defines the direction of the channel (input/output) as well as the
used input.
00: CC1 channel is configured as output
01: CC1 channel is configured as input, IC1 is mapped on TI1
10: Reserved
11: Reserved
Note: CC1S bits are writable only when the channel is OFF (CC1E = ‘0’ in
TIMx_CCER).

20.6.7. TIM16 and TIM17 capture/compare enable


register(TIM16_CCER and TIM17_CCER)

Address offset: 0x20


Reset value: 0x0000
bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
7:0 — CC1NP CC1NE CC1P CC1E
type RO-0 RO-0 RO-0 RO-0 RW RW RW RW

Bit Name Function

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31:4 NA Reserved, undefined


3 CC1NP Capture/Compare 1 complementary output polarity
CC1 channel configuration as output:
0: OC1N active high.
1: OC1N active low.
CC1 channel configuration as input:
This bit is used in conjunction with CC1P to define the polarity of TI1FP1 and
TI2FP1. Refer to CC1P description.
Note1: This bit is not writable as soon as LOCK level 2 or 3 has been
programmed (LOCK bits in TIMx_BDTR register) and CC1S=”00” (the
channel is configured in output).
Note2: On channels having a complementary output, this bit is preloaded. If
the CCPC bit is set in the TIMx_CR2 register then the CC1NP active bit
takes the new value from the preloaded bits only when a Commutation event
is generated.
2 CC1NE Capture/Compare 1 complementary output enable
0: Off
－OC1N is not active. OC1N level is then function of MOE, OSSI, OSSR,
OIS1, OIS1N and CC1E bits.
1: On
－OC1N signal is output on the corresponding output pin depending on
MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits.
Note: On channels having a complementary output, this bit is preloaded. If
the CCPC bit is set in the TIMx_CR2 register then the CC1NE active bit
takes the new value from the preloaded bits only when a Commutation event
is generated
1 CC1P Capture/Compare 1 output polarity
CC1 channel configured as output:
0: OC1 active high
1: OC1 active low
CC1 channel configured as input:
CC1NP/CC1P bits select the active polarity of TI1FP1 and TI2FP1 for trigger
or capture operations.
00: Non-inverted/rising edge
circuit is sensitive to TixFP1’s rising edge (capture or trigger operations in
reset, external clock or trigger mode), TixFP1 is not inverted (in gated mode
or encoder mode).
01: Inverted/falling edge
The circuit is sensitive to TixFP1 falling edge (capture or trigger operations in
reset, external clock or trigger mode), TixFP1 is inverted (in gated mode or
encoder mode).
10: Reserved, do not use this configuration.
11: Non-inverted/both edges
The circuit is sensitive to both TixFP1 rising and falling edges (capture or
trigger operations in reset, external clock or trigger mode), TixFP1 is not
inverted (gated mode or encoder mode).
Note1: This bit is not writable as soon as LOCK level 2 or 3 has been
programmed (LOCK bits in TIMx_BDTR register)
Note2: On channels having a complementary output, this bit is preloaded. If

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Fremont Micro Devices FT32F0xxx8 RM

the CCPC bit is set in the TIMx_CR2 register then the CC1P active bit takes
the new value from the preloaded bits only when a Commutation event is
generated.
0 CC1E Capture/Compare 1 output enable
CC1 channel configured as output:
0: Off
－ OC1 is not active. OC1 level is then function of MOE, OSSI, OSSR,
OIS1, OIS1N and CC1NE bits.
1: On
－ OC1 signal is output on the corresponding output pin depending on
MOE, OSSI, OSSR, OIS1, OIS1N and CC1NE bits.
CC1 channel configured as input:
This bit determines if a capture of the counter value can actually be done
into the input capture/compare register 1 (TIMx_CCR1) or not.
0: Capture disabled
1: Capture enabled
Note: On channels having a complementary output, this bit is preloaded. If
the CCPC bit is set in the TIMx_CR2 register then the CC1E active bit takes
the new value from the preloaded bits only when a Commutation event is
generated.

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Table 20-3 utput control bits for complementary Ocx and OcxN channels with break feature
Control bits Output states(1)
MOE OSSI OSSR CcxE CcxNE Ocx output state OcxN output state
Output Disabled (not driven by Output Disabled (not driven by
0 0 0 the timer) the timer)
Ocx=0, Ocx_EN=0 OcxN=0, OcxN_EN=0
Output Disabled (not driven by OCxREF + Polarity
0 0 1 the timer) OcxN=OCxREF ^ CCxNP
Ocx=0, Ocx_EN=0 OcxN_EN=1
OCxREF + Polarity Output Disabled (not driven by
0 1 0 Ocx=OCxREF ^ CCxNP the timer)
Ocx_EN=1 OcxN=0, OcxN_EN=0
Complementary to OCxREF +
OCxREF + Polarity + deadtime
0 1 1 Polarity + dead-time
Ocx_EN=1
OcxN_EN=1
1 X
Output Disabled (not driven by Output Disabled (not driven by
1 0 0 the timer) the timer)
Ocx=CCxP, Ocx_EN=0 OcxN=CCxNP,OcxN_EN=0
Off-state(output enabled with Run OCxREF + Polarity
1 0 1 mode) OcxN=OCxREF ^ CCxNP
Ocx=CCxP, Ocx_EN=1 OcxN_EN=1
OCxREF + Polarity Off-state(output enabled with Run
1 1 0 Ocx=OCxREF ^ T1CCxNP mode)
Ocx_EN=1 OcxN=T1CCxNP, Ocx_EN=1
Complementary to OCxREF +
OCxREF + Polarity + deadtime
1 1 1 Polarity + dead-time
Ocx_EN=1
OcxN_EN=1
Output Disabled (not driven by Output Disabled (not driven by
0 0 0 the timer) the timer)
Ocx=CCxP, Ocx_EN=0 OcxN=CCxNP,OcxN_EN=0
0 0 1 Output Disabled (not driven by the timer)
0 1 0 Asynchronously: Ocx=CCxP, Ocx_EN=0, OcxN=CCxNP,
OcxN_EN=0
Then if the clock is present: Ocx=OISx and OcxN=OISxN after a
0 1 1
dead-time, assuming that OISx and OISxN do not correspond to OCX
0 X and OcxN both in active state.
Output Disabled (not driven by Output Disabled (not driven by
1 0 0 the timer) the timer)
Ocx=CCxP, Ocx_EN=0 OcxN=CCxNP,OcxN_EN=0
1 0 1 Off-State (output enabled with inactive state)
1 1 0 Asynchronously:Ocx=CCxP,Ocx_EN=1,OcxN=CCxNP,OcxN_EN=1
Then if the clock is present: Ocx=OISx and OcxN=OISxN
1 1 1 after a dead-time, assuming that OISx and OISxN do not
correspond to OCX and OcxN both in active state
（1） When both outputs of a channel are not used (CcxE = CcxNE = 0), the OISx, OISxN, CCxP and

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CCxNP bits must be kept cleared.


Note:The state of the external I/O pins connected to the complementary Ocx and OcxN channels depends
on the Ocx and OcxN channel state and the GPIO and AFIO registers.

20.6.8. TIM16 and TIM17 counter(TIM16_CNT and TIM17_CNT)

Address offset: 0x24


Reset value: 0x0000
bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 CNT[15:8]
type RW RW RW RW RW RW RW RW
7:0 CNT[7:0]
type RW RW RW RW RW RW RW RW

Bit Name Function


31:16 NA Reserved, undefined
15:0 CNT[15:0] Counter value

20.6.9. TIM16 and TIM17 prescaler(TIM16_PSC and


TIM17_PSC)

Address offset: 0x28


Reset value: 0x0000
bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 PSC[15:8]
type RW RW RW RW RW RW RW RW
7:0 PSC[7:0]
type RW RW RW RW RW RW RW RW

Bit Name Function


31:16 NA Reserved, undefined
15:0 PSC[15:0] Prescaler value

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The counter clock frequency (CK_CNT) is equal to 𝑓𝐶𝐾_𝑃𝑆𝐶 /(PSC[15:0]+1).


PSC contains the value to be loaded in the active prescaler register at each
update event.

20.6.10. TIM16 and TIM17 auto-reload register(TIM16_ARR and


TIM17_ARR)

Address offset: 0x2C


Reset value: 0x0000
bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 ARR[15:8]
type RW RW RW RW RW RW RW RW
7:0 ARR[7:0]
type RW RW RW RW RW RW RW RW

Bit Name Function


31:16 NA Reserved, undefined
15:0 ARR[15:0] Auto-reload value
ARR is the value to be loaded in the actual auto-reload register.
The counter is blocked while the auto-reload value is null.

20.6.11. TIM16 and TIM17 repetition counter


register(TIM16_RCR and TIM17_RCR)

Address offset: 0x30


Reset value: 0x0000
bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
7:0 REP[7:0]
type RW RW RW RW RW RW RW RW

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Bit Name Function


31:8 NA Reserved, undefined
7:0 REP[7:0] Repetition counter value
These bits allow the user to set-up the update rate of the compare registers
(i.e. periodic transfers from preload to active registers) when preload
registers are enable, as well as the update interrupt generation rate, if this
interrupt is enable. Each time the REP_CNT related downcounter reaches
zero, an update event is generated and it restarts counting from REP value.
As REP_CNT is reloaded with REP value only at the repetition update event
U_RC, any write to the TIMx_RCR register is not taken in account until
the next repetition update event.It means in PWM mode (REP+1)
corresponds to the number of PWM periods in edge-aligned mode.

20.6.12. TIM16 and TIM17 capture/compare register


1(TIM16_CCR1 and TIM17_CCR1)

Address offset: 0x34


Reset value: 0x0000
bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 CCR1[15:8]
type RW RW RW RW RW RW RW RW
7:0 CCR1[7:0]
type RW RW RW RW RW RW RW RW

Bit Name Function


31:16 NA Reserved, undefined
15:0 CCR1[15:0] Capture/Compare 1 value
If channel CC1 is configured as output:
CCR1 is the value to be loaded in the actual capture/compare 1 register
(preload value). It is loaded permanently if the preload feature is not selected
in the TIMx_CCMR1 register (bit OC1PE). Else the preload value is copied
in the active capture/compare 1 register when an update event occurs.
The active capture/compare register contains the value to be compared to
the counter TIMx_CNT and signaled on OC1 output.
If channel CC1 is configured as input:
CCR1 is the counter value transferred by the last input capture 1 event (IC1).

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20.6.13. TIM16 and TIM17 break and dead-time


register(TIM16_BDTR and TIM17_BDTR)

Address offset: 0x44


Reset value: 0x0000
bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 MOE AOE BKP BKE OSSR OSSI LOCK[1:0]
type RW RW RW RW RW RW RW RW
7:0 DTG[7:0]
type RW RW RW RW RW RW RW RW

Bit Name Function


31:16 NA Reserved, undefined
15 MOE Main output enable
This bit is cleared asynchronously by hardware as soon as the break input is
active. It is set by software or automatically depending on the AOE bit. It is
acting only on the channels which are configured in output.
0: outputs are disabled or forced to idle state
1: OC and OCN outputs are enabled if their respective enable bits are set
(CcxE in TIMx_CCER register)
14 AOE Automatic output enable
0: MOE can be set only by software
1: MOE can be set by software or automatically at the next update event (if
the break input is not be active)
Note: This bit can not be modified as long as LOCK level 1 has been
programmed (LOCK bits in TIMx_BDTR register).
13 BKP Break polarity
0: Break input BRK is active low
1: Break input BRK is active high
Note1: This bit can not be modified as long as LOCK level 1 has been
programmed (LOCK bits in TIMx_BDTR register).
Note2: Any write operation to this bit takes a delay of 1 APB clock cycle to
become effective.
12 BKE Break enable
0: Break inputs (BRK and internal break sources) disabled
1: Break inputs (BRK and internal break sources) enabled
Note1: This bit cannot be modified when LOCK level 1 has been
programmed (LOCK bits in
TIMx_BDTR register).

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Note2: Any write operation to this bit takes a delay of 1 APB clock cycle to
become effective.
11 OSSR Off-state selection for Run mode
This bit is used when MOE=1 on channels having a complementary output
which are configured as outputs.
0: When inactive, Ocx/OcxN outputs are disabled (Ocx/OcxN enable output
signal=0)
1: When inactive, Ocx/OcxN outputs are enabled with their inactive level as
soon as CcxE=1 or CcxNE=1. Then, Ocx/OcxN enable output signal=1
Note: This bit can not be modified as soon as the LOCK level 2 has been
programmed (LOCK bits in TIMx_BDTR register).
10 OSSI Off-state selection for Idle mode
This bit is used when MOE=0 on channels configured as outputs.
0: When inactive, Ocx/OcxN outputs are disabled (Ocx/OcxN enable output
signal=0)
1: When inactive, Ocx/OcxN outputs are forced first with their idle level as
soon as CcxE=1 or CcxNE=1. Ocx/OcxN enable output signal=1)
Note: This bit can not be modified as soon as the LOCK level 2 has been
programmed (LOCK bits in TIMx_BDTR register).
9:8 LOCK Lock configuration
These bits offer a write protection against software errors.
00: LOCK OFF – No bit is write protected
01: LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits
in TIMx_CR2 register and BKE/BKP/AOE bits in TIMx_BDTR register can no
longer be written.
10: LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in
TIMx_CCER register, as long as the related channel is configured in output
through the CCxS bits) as well as OSSR and OSSI bits can no longer be
written.
11: LOCK Level 3 = LOCK Level 2 + CC Control bits (OcxM and OcxPE bits
in TIMx_CCMRx registers, as long as the related channel is configured in
output through the CCxS bits) can no longer be written.
Note: The LOCK bits can be written only once after the reset. Once the
TIMx_BDTR register has been written, their content is frozen until the
next reset.
7:0 DTG[7:0] Dead-time generator setup
This bit-field defines the duration of the dead-time inserted between the
complementary outputs. DT correspond to this duration
DTG[7:5]=0xx => DT=DTG[7:0]* tdtg with tdtg=tDTS
DTG[7:5]=10x => DT=(64+DTG[5:0]) * tdtg with tdtg= 2*tDTS
DTG[7:5]=110 => DT=(32+DTG[4:0]) * tdtg with tdtg=8* tDTS
DTG[7:5]=111 => DT=(32+DTG[4:0]) * tdtg with tdtg= 16*tDTS
Example if TDTS=125ns (8MHz), dead-time possible values are:
DTG[7:0] = 0~7Fh,0 to 15875 ns by 125 ns steps
DTG[7:0] = 80h~BFh,16 μs to 31750 ns by 250 ns steps,
DTG[7:0] = C0h~DFh,32 μs to 63 μs by 1 μs steps,
DTG[7:0] = E0h~FFh,64 μs to 126 μs by 2 μs steps

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Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has
been programmed (LOCK bits in TIMx_BDTR register).

20.6.14. TIM16 and TIM17 DMA control register(TIM16_DCR


and TIM17_DCR)

Address offset: 0x48


Reset value: 0x0000
bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 — DBL[4:0]
type RO-0 RO-0 RO-0 RW RW RW RW RW
7:0 — DBA[4:0]
type RO-0 RO-0 RO-0 RW RW RW RW RW

Bit Name Function


31:13 NA Reserved, undefined
12:8 DBL[4:0] DMA burst length
This 5-bit vector defines the length of DMA transfers (the timer recognizes a
burst transfer when a read or a write access is done to the TIMx_DMAR
address)
00000: 1 transfer,
00001: 2 transfers,
00010: 3 transfers,
...
10001: 18 transfers.
7:5 NA Reserved, undefined
4:0 DBA[4:0] This 5-bits vector defines the base-address for DMA transfers (when
read/write access are done through the TIMx_DMAR address). DBA is
defined as an offset starting from the address of the TIMx_CR1 register.
Example:
00000: TIMx_CR1,
00001: TIMx_CR2,
00010: TIMx_SMCR,
...
Example: Let us consider the following transfer: DBL = 7 transfers and DBA
= TIMx_CR1. In this case the transfer is done to/from 7 registers starting
from the TIMx_CR1 address.

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20.6.15. TIM16 and TIM17 address for full


transfer(TIM16_DMAR and TIM17_DMAR)

Address offset: 0x4C


Reset value: 0x0000
bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0

31:24 —

type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0

23:16 —

type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0

15:8 DMAB[15:8]

type RW RW RW RW RW RW RW RW

7:0 DMAB[7:0]

type RW RW RW RW RW RW RW RW

Bit Name Function


31:16 NA Reserved, undefined
15:0 DMAB[15:0] DMA register for burst accesses
A read or write access to the DMAR register accesses the register located at
the address: (TIMx_CR1 address)+(DBA + DMA index)*4
in which:
TIMx_CR1 address is the address of the control register 1;
DBA is the DMA base address configured in TIMx_DCR register;
DMA index is the offset automatically controlled by the DMA transfer,
depending on the length of the transfer DBL in the TIMx_DCR register.

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Example of how to use the DMA burst feature


In this example the timer DMA burst feature is used to update the contents of the CCRx registers (x = 2, 3, 4)
with the DMA transferring half words into the CCRx registers.
This is done in the following steps:
1. Configure the corresponding DMA channel as follows:
− DMA channel peripheral address is the DMAR register address
− DMA channel memory address is the address of the buffer in the RAM containing the data to be
transferred by DMA into CCRx registers.
− Number of data to transfer = 3
− Circular mode disabled.
2. Configure the DCR register by configuring the DBA and DBL bit fields: DBL=3, DMA burst length of the
transfer is 3 , DBA=0xE, the initial transfer address offset is 0x38(TIMx_CCR2).
3. Enable the TIMx update DMA request
4. Enable TIMx
5. Enable the DMA channel
6. Note:This example is for the case where every CCRx register to be updated once. If every CCRx
register is to be updated twice for example, the number of data to transfer should be 6. Let us take the
example of a buffer in the RAM containing data1, data2, data3, data4, data5 and data6. The data is
transferred to the CCRx registers as follows: on the first update DMA request, data1 is transferred to
CCR2, data2 is transferred to CCR3, data3 is transferred to CCR4 and on the second update DMA
request, data4 is transferred to CCR2, data5 is transferred to CCR3 and data6 is transferred to CCR4.

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21. Infrared interface(IRTIM)


An infrared interface (IRTIM) for remote control is available on the device. It can be used with an infrared
LED to perform remote control functions.
It uses internal connections with USART1, USART2, TIM16 and TIM17 as shown in Figure 21-1
To generate the infrared remote control signals, the IR interface must be enabled and TIM16 and TIM17 must
be properly configured to generate correct waveforms.
The infrared receiver can be implemented easily through a basic input capture mode.

TIM17_CH1
IR_OUT
TIM16_CH1

USART1

USART2
SYSCFG_CFGR1[7:6]

Figure 21-1 IR internal hardware connections

All standard IR pulse modulation modes can be obtained by programming the two timer output compare
channels.
TIM17 generates high frequency carrier signal TIM16 generates the modulation envelope.
The infrared function is output on the IR_OUT pin. The activation of this function is done through the
GPIOx_AFRx register by enabling the related alternate function bit.

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22. Independent watchdog(IWDG)

22.1. Introduction

The devices feature an embedded watchdog peripheral which offers a combination of high safety level,
timing accuracy and flexibility of use. The Independent watchdog peripheral serves to detect and resolve
malfunctions due to software failure, and to trigger system reset when the counter reaches a given timeout
value.

22.2. IWDG main features

 Free-running downcounter
 Clocked from an independent RC oscillator (can operate in Standby and Stop modes)
 Conditional Reset
− Reset (if watchdog activated) when the downcounter value becomes less than 0
− Reset (if watchdog activated) if the downcounter is reloaded outside the window

22.3. IWDG functional description

22.3.1. IWDG block diagram

Figure 22-1 shows the functional blocks of the independent watchdog module.

PCLK 1.6V ___domain

IWDG_PR IWDG_SR IWDG_RLR IWDG_KR IWDG_WINR

TCLK
5V ___domain
12-bit reload
value
12-bit
8-bit window
LSI
prescaler value
40KHz

12-bit IWDG_RESET
downcounter

Figure 22-1 Independent watchdog block diagram


When the independent watchdog is started by writing the value 0x0000 CCCC in the Key register, the

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counter starts counting down from the reset value of 0xFFF. When it reaches the end of count value (0x000)
a reset signal is generated (IWDG reset).
Whenever the key value 0x0000 AAAA is written in the IWDG_KR register, the IWDG_RLR value is reloaded
in the counter and the watchdog reset is prevented. It should have at least three 40kHz LSI clock cycles
between two write operation.

22.3.2. Window option

The IWDG can also work as a window watchdog by setting the appropriate window in the IWDG_WINR
register.
If the reload operation is performed while the counter is greater than the value stored in the window register
(IWDG_WINR), then a reset is provided.
The default value of the IWDG_WINR is 0x0000 0FFF, so if it is not updated, the window option is disabled.
As soon as the window value is changed, a reload operation is performed in order to reset the downcounter
to the IWDG_RLR value and ease the cycle number calculation to generate the next reload.

Configuring the IWDG when the window option is enabled


1. Enable the IWDG by writing 0x0000 CCCC in the IWDG_KR register;
2. Enable register access by writing 0x0000 5555 in the IWDG_KR register;
3. Write the IWDG prescaler by programming IWDG_PR from 0 to 7;
4. Write the reload register (IWDG_RLR);
5. Wait for the registers to be updated (IWDG_SR = 0x0000 0000);
6. Write to the window register IWDG_WINR. This automatically refreshes the counter value IWDG_RLR;
Note: Writing the window value allows to refresh the Counter value by the RLR when IWDG_SR is set to
0x0000 0000.

Configuring the IWDG when the window option is disabled


When the window option it is not used, the IWDG can be configured as follows:
1. Enable the IWDG by writing 0x0000 CCCC in the IWDG_KR register;
2. Enable register access by writing 0x0000 5555 in the IWDG_KR register;
3. Write the IWDG prescaler by programming IWDG_PR from 0 to 7;
4. Write the reload register (IWDG_RLR);
5. Wait for the registers to be updated (IWDG_SR = 0x0000 0000);
6. Refresh the counter value with IWDG_RLR (IWDG_KR = 0x0000 AAAA)

22.3.3. Hardware watchdog

If the DBG_IWDG_STOP in DBG module is 1, then the IWDG will be enabled automatically turn on when the
device is power up. A hardware reset will be generated if the 0x0000AAAA not been wrote into IWDG_KR
before conter count to 0 or before the down counter greater than the window value.s

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22.3.4. Stop/Standby mode behavior

IWDG register cannot be configured in Stop or Standby mode, but the counter can still run and the reset
signal can also be generated.

22.3.5. Register access protection

Write access to the IWDG_PR, IWDG_RLR and IWDG_WINR registers is protected. To modify them, you
must first write the code 0x0000 5555 in the IWDG_KR register. A write access to this register with a
different value will break the sequence and register access will be protected again. This implies that it is the
case of the reload operation(writing 0x0000 AAAA).
A status register(IWDG_SR) is available to indicate that an update of the prescaler or the down-counter
reload value or the window value is on going.

22.3.6. Debug mode

When the microcontroller enters debug mode (core halted), the IWDG counter either continues to work
normally or stops, depending on DBG_IWDG_STOP configuration bit in DBG module

22.4. IWDG register map


31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10

Offset Register
9
8
7
6
5
4
3
2
1
0
IWDG_KR KEY[15:0]
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–

0x00

Reset x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IWDG_PR PR[2:0]
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–

0x04

Reset x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 0 0 0

IWDG_RLR RL[11:0]
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–

0x08

Reset x x x x x x x x x x x x x x x x x x x x 1 1 1 1 1 1 1 1 1 1 1 1
WVU
RVU
PVU

IWDG_SR
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–

0x0C

Reset x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 0 0 0

IWDG_WINR WIN[11:0]
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–

0x10

Reset x x x x x x x x x x x x x x x x x x x x 1 1 1 1 1 1 1 1 1 1 1 1

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22.4.1. IWDG_KR

Address offset: 0x00


Reset value: 0x0000 0000(reset by Standby mode)
Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 KEY[15:8]
Type W W W W W W W W
7:0 KEY[7:0]
Type W W W W W W W W

Bit Name Function


31:16 NA Reserved
15:0 KEY[15:0] write only, read 0x0000
These bits must be written by software at regular intervals with the key value
0xAAAA, otherwise the watchdog generates a reset when the counter
reaches 0
Writing the key value 0x5555 to enable access to the IWDG_PR,
IWDG_RLR and IWDG_WINR registers
Writing the key value CCCCh starts the watchdog (except if the hardware
watchdog option is selected)

22.4.2. IWDG_PR

Address offset: 0x04


Reset value: 0x0000 0000
Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
7:0 — PR
Type RO-0 RO-0 RO-0 RO-0 RO-0 RW RW RW

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Bit Name Function


31:3 NA Reserved
2:0 PR[2:0] These bits are write access protected They are written by software to select
the prescaler divider feeding the counter clock. PVU bit of IWDG_SR must
be reset in order to be able to change the prescaler divider.
000: divider /4
001: divider /8
010: divider /16
011: divider /32
100: divider /64
101: divider /128
110: divider /256
111: divider /256
Note: Reading this register returns the prescaler value from the 5V ___domain.
This value may not be up to date/valid if a write operation to this register is
ongoing. For this reason the value read from this register is valid only when
the PVU bit in the IWDG_SR register is reset.

22.4.3. IWDG_RLR

Address offset: 0x08


Reset value: 0x0000 0FFF(reset by Standby mode)
Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 — RL[11:8]
Type RO-0 RO-0 RO-0 RO-0 RO-0 RW RW RW
7:0 RL[7:0]
Type RW RW RW RW RW RW RW RW

Bit Name Function


31:12 NA Reserved
11:0 RL[11:0] These bits are write access protected They are written by software to define
the value to be loaded in the watchdog counter each time the value 0xAAAA
is written in the IWDG_KR register. The watchdog counter counts down from
this value. The timeout period is a function of this value and the clock
prescaler.
Note: Reading this register returns the prescaler value from the 5V ___domain.
This value may not be up to date/valid if a write operation to this register is
ongoing. For this reason the value read from this register is valid only when
the PVU bit in the IWDG_SR register is reset.

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22.4.4. IWDG_SR

Address offset: 0x0C


Reset value: 0x0000 0FFF(not reset by Standby mode)
Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
7:0 — WVU RVU PVU
Type RO-0 RO-0 RO-0 RO-0 RO-0 RW RW RW

Bit Name Function


31:3 NA Reserved
2 WVU Watchdog counter window value update
This bit is set by hardware to indicate that an update of the window value is
ongoing. It is reset by hardware when the reload value update operation is
completed in the 5V voltage ___domain (takes up to 3 RC 40 kHz cycles).
Indow value can be updated only when WVU bit is reset.
1 RVU Watchdog counter reload value update
This bit is set by hardware to indicate that an update of the reload value is
ongoing. It is reset by hardware when the reload value update operation is
completed in the 5V voltage ___domain (takes up to 3 RC 40 kHz cycles).
Reload value can be updated only when RVU bit is reset.
0 PVU Watchdog prescaler value update
This bit is set by hardware to indicate that an update of the prescaler value is
ongoing. It is reset by hardware when the prescaler update operation is
completed in the 5V voltage ___domain (takes up to 3 RC 40 kHz cycles).
Prescaler value can be updated only when PVU bit is reset.

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22.4.5. IWDG_WINR

Address offset: 0x0C


Reset value: 0x0000 0FFF(reset by Standby mode)
Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 — WIN[11:8]
Type RO-0 RO-0 RO-0 RO-0 RO-0 RW RW RW
7:0 WIN[7:0]
Type RW RW RW RW RW RW RW RW

Bit Name Function


31:12 NA Reserved
11:0 WIN[11:0] These bits are write access protected. These bits contain the high limit of the
window value to be compared to the downcounter.
To prevent a reset, the downcounter must be reloaded when its value is
lower than the window register value and greater than 0
The WVU bit in the IWDG_SR register must be reset in order to be able to
change the reload value.
Note: Reading this register returns the prescaler value from the 5V ___domain.
This value may not be up to date/valid if a write operation to this register is
ongoing. For this reason the value read from this register is valid only when
the PVU bit in the IWDG_SR register is reset.

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23. System window watchdog(WWDG)

23.1. Introduction

The system window watchdog (WWDG) is used to detect the occurrence of a software fault, usually
generated by external interference or by unforeseen logical conditions, which causes the application
program to abandon its normal sequence. The watchdog circuit generates an MCU reset on expiry of a
programmed time period, unless the program refreshes the contents of the downcounter before the T[6] bit
becomes cleared. An MCU reset is also generated if the 7-bit downcounter value (in the control register) is
refreshed before the downcounter has reached the window register value. This implies that the counter must
be refreshed in a limited window.
The WWDG clock is prescaled from the APB clock and has a configurable time-window that can be
programmed to detect abnormally late or early application behavior.
The WWDG is best suited for applications which require the watchdog to react within an accurate timing
window.

23.2. WWDG main features

 Programmable free-running downcounter


 Conditional reset
− Reset (if watchdog activated) when the downcounter value becomes less than 0x40.
− Reset (if watchdog activated) if the downcounter is reloaded outside the window
 Early wakeup interrupt (EWI): triggered (if enabled and the watchdog activated) when the downcounter
is equal to 0x40.

23.3. WWDG functional description

If the watchdog is activated (the WDGA bit is set in the WWDG_CR register) and when the 7-bit
downcounter (T[6:0] bits) rolls over from 0x40 to 0x3F (T[6] becomes cleared), it initiates a reset. If the
software reloads the counter while the counter is greater than the value stored in the window register, then a
reset is generated.
The application program must write in the WWDG_CR register at regular intervals during normal operation
to prevent an MCU reset. This operation must occur only when the counter value is lower than the window
register value. The value to be stored in the WWDG_CR register must be between 0xFF and 0xC0.

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W[6:0]
cmp=1 when
T[6:0] >[ W6:0]
WWDG_RESET cmp
Q D
Write WWDG_CR
RB pclk
WDGA T6 T[5:0]
presetn
7-bit downcounter

pclk
/4096 prescaler

Figure 23-1 Watchdog block diagram

23.3.1. Enabling the watchdog

The watchdog is always disabled after a reset. It is enabled by setting the WDGA bit in the WWDG_CR
register, then it cannot be disabled again except by a reset.

23.3.2. Controlling the downcounter

This downcounter is free-running, counting down even if the watchdog is disabled. When the watchdog is
enabled, the T[6] bit must be set to prevent generating an immediate reset.
The T[5:0] bits contain the number of increments which represents the time delay before the watchdog
produces a reset. The timing varies between a minimum and a maximum value due to the unknown status of
the prescaler when writing to the WWDG_CR register . The Configuration register (WWDG_CFR) contains
the high limit of the window:
To prevent a reset, the downcounter must be reloaded when its value is lower than the window register value
and greater than 0x3F. Figure 23-2 describes the window watchdog process.
Note: The T[6] bit can be used to generate a software reset (the WDGA bit is set and the T[6] bit is cleared).

23.3.3. Advanced watchdog interrupt feature

The Early Wakeup Interrupt (EWI) can be used if specific safety operations or data logging must be
performed before the actual reset is generated. The EWI interrupt is enabled by setting the EWI bit in the
WWDG_CFR register. When the downcounter reaches the value 0x40, an EWI interrupt is generated and
the corresponding interrupt service routine (ISR) can be used to trigger specific actions (such as
communications or data logging), before resetting the device.
In some applications, the EWI interrupt can be used to manage a software system check and/or system

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recovery/graceful degradation, without generating a WWDG reset. In this case, the corresponding interrupt
service routine (ISR) should reload the WWDG counter to avoid the WWDG reset, then trigger the required
actions.
Note: When the EWI interrupt cannot be served, e.g. due to a system lock in a higher priority task, the
WWDG reset will eventually be generated.

23.3.4. How to program the watchdog timeout

You can use the formula shown below to calculate the WWDG timeout.
Note: When writing to the WWDG_CR register, always write 1 in the T[6] bit to avoid generating an
immediate reset.

T[6:0] downcounter

W[6:0]

0x3F

Not allow Refresh allow Time


T[6] bit

reset

Figure 23-2 Window watchdog timing diagram


The formula to calculate the timeout value is given by:
𝑡𝑊𝑊𝐷𝐺 = 𝑡𝑃𝐶𝐿𝐾 ∗ 4096 ∗ 2𝑊𝐷𝐺𝑇𝐵[1:0] ∗ (𝑇[5: 0] + 1) (ms)
where:
𝑡𝑊𝑊𝐷𝐺 :WWDG timeout
𝑡𝑃𝐶𝐿𝐾 :APB clock period measured in ms
4096: value corresponding to internal divider
As an example, lets assume APB frequency is equal to 48 MHz, WDGTB1:0] is set to 3 and T[5:0] is set to
63:

𝑡𝑊𝑊𝐷𝐺 = 1⁄48000 ∗ 4096 ∗ 23 ∗ (63 + 1) = 43.69 (ms)

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23.3.5. Debug mode

When the microcontroller enters debug mode (Cortex®-M0 core halted), the WWDG counter either continues
to work normally or stops, depending on DBG_WWDG_STOP configuration bit in DBG module.

23.4. WWDG register map


31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
Offset Register

9
8
7
6
5
4
3
2
1
0
WWDG_CR T[6:0]

WDGA
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0x00

Reset x x x x x x x x x x x x x x x x x x x x x x x x 0 1 1 1 1 1 1 1

WDGTB1
WDGTB0
WWDG_CFR W[6:0]
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0x04

EWI
Reset x x x x x x x x x x x x x x x x x x x x x x 0 0 0 1 1 1 1 1 1 1

EWIF
WWDG_SR
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0x08

Reset x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 0

23.4.1. WWDG_CR

Address offset: 0x00


Reset value: 0x0000 007F
Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
7:0 WDGA T[6:0]
Type RS RW RW RW RW RW RW RW

Bit Name Function


31:8 NA Reserved
7 WDGA Activation bit
This bit is set by software and only cleared by hardware after a reset.
When WDGA = 1, the watchdog can generate a reset.
0: Watchdog disabled
1: Watchdog enabled
6:0 T[6:0] 7-bit counter (MSB to LSB)
These bits contain the value of the watchdog counter. It is decremented
every (4096 x 2WDGTB1:0)) PCLK cycles. A reset is produced when it rolls
over from 0x40 to 0x3F (T[6] becomes cleared).

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23.4.2. WWDG_CFR

Address offset: 0x04


Reset value: 0x0000 007F
Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 — EWI WDGTB
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RS RW
7:0 WDGTB W[6:0]
Type RW RW RW RW RW RW RW RW

Bit Name Function


31:10 NA Reserved
9 EWI Early wakeup interrupt
When set, an interrupt occurs whenever the counter reaches the value 0x40.
This interrupt is only cleared by hardware after a reset.
8:7 WDGTB[1:0] Timer base
The time base of the prescaler can be modified as follows:
00: CK Counter Clock (PCLK div 4096) div 1
01: CK Counter Clock (PCLK div 4096) div 2
10: CK Counter Clock (PCLK div 4096) div 4
11: CK Counter Clock (PCLK div 4096) div 8
6:0 W[6:0] 7-bit window value
These bits contain the window value to be compared to the downcounter.

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23.4.3. WWDG_SR

Address offset: 0x08


Reset value: 0x0000 0000
Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
7:0 — EWIF
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RC_W0

Bit Name Function


31:1 NA Reserved
0 EWIF Early wakeup interrupt flag
This bit is set by hardware when the counter has reached the value 0x40. It
must be cleared by software by writing ‘0’. A write of ‘1’ has no effect. This bit
is also set if the interrupt is not enabled.

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24. Real-time clock(RTC)

24.1. Introduction

The real-time clock (RTC) is an independent BCD timer/counter. The RTC provides a time- of-day
clock/calendar with programmable alarm interrupt.
Two 32-bit registers contain the seconds, minutes, hours (12- or 24-hour format), day (day of week), date
(day of month), month, and year, expressed in binary coded decimal format (BCD). The sub-seconds value
is also available in binary format.
Compensations for 28-, 29- (leap year), 30-, and 31-day months are performed automatically. Daylight
saving time compensation can also be performed.
Additional 32-bit registers contain the programmable alarm subseconds, seconds, minutes, hours, day, and
date.
A digital calibration feature is available to compensate for any deviation in crystal oscillator accuracy.
After RTC ___domain reset, all RTC registers are protected against possible parasitic write accesses.
As long as the supply voltage remains in the operating range, the RTC never stops, regardless of the device
status (Run mode, low-power mode or under reset).

24.2. RTC main features

The RTC unit main features are the following:


 Calendar with subseconds, seconds, minutes, hours (12 or 24 format), day (day of week), date (day of
month), month, and year.
 Daylight saving compensation programmable by software.
 Programmable alarm with interrupt function. The alarm can be triggered by any combination of the
calendar fields.
 Reference clock detection: a more precise second source clock (50 or 60 Hz) can be used to enhance
the calendar precision.
 Accurate synchronization with an external clock using the subsecond shift feature.
 Digital calibration circuit (periodic counter correction): 0.95 ppm accuracy, obtained in a calibration
window of several seconds
 Time-stamp function for event saving
 Tamper detection event with configurable filter and internal pull-up
 Maskable interrupts/events:
─ Alarm A
─ Wakeup interrupt
─ Tamper detection

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24.3. RTC functional description

24.3.1. RTC block diagram

RTC_TAMP2
RTC tamper control
TAMPxF
registers
RTC_TAMP1

RTC_TS Time stamp


registers TSF

RTC_REFIN

LSE(32.768 Hz)
HSE/32
LSI
RTCCLK

RTC_CALR RTC_PRER ck_apre RTC_PRER ck_spre


(default 256 Hz) (default 1 Hz)
Asynchronous Synchronous
Smooth
7-bit prescaler 15-bit prescaler
calibration Calendar
(default = 128) (default = 256)

Shadow registers
Shadow register
RTC_TR,
RTC_SSR
RTC_DR

RTC_CALIB
Output
RTC_OUT
Control
RTC_ALARM

Alarm A
= ALRAF
RTC_ALRMAR
RTC_ALRMASSR

Figure 24-1 RTC block diagram

The RTC includes:


 One alarm
 2 I/O Tamper detection
 1 I/O Time-stamp
 A Tamper detection can generate a Time-stamp
 Alternate function outputs: RTC_OUT which selects one of the following two outputs:
─ RTC_CALIB: 512 Hz or 1Hz clock output (with an LSE frequency of 32.768 kHz). This output is
enabled by setting the COE bit in the RTC_CR register.
─ RTC_ALARM: Alarm A. This output is selected by configuring the OSEL[1:0] bits in the RTC_CR
register.

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 Alternate function inputs:


─ RTC_TS: timestamp event
─ RTC_TAMP1: tamper1 event detection
─ RTC_TAMP2: tamper2 event detection
─ RTC_REFIN: 50 or 60 Hz reference clock input

24.3.2. GPIOs controlled by the RTC

RTC_OUT, RTC_TS and RTC_TAMP1 are mapped on the same pin (PC13).
The selection of the RTC_ALARM output is performed through the RTC_TAFCR register as follows: the
PC13VALUE bit is used to select whether the RTC_ALARM output is configured in push-pull or open drain
mode.
When PC13 is not used as RTC alternate function, it can be forced in output push-pull mode by setting the
PC13MODE bit in the RTC_TAFCR. The output data value is then given by the PC13VALUE bit. In this case,
PC13 output push-pull state and data are preserved in Standby mode.
The output mechanism follows the priority order shown in Table 24-1
When PC14 and PC15 are not used as LSE oscillator, they can be forced in output push-pull mode by setting
the PC14MODE and PC15MODE bits in the RTC_TAFCR register respectively. The output data values are
then given by PC14VALUE and PC15VALUE. In this case, the PC14 and PC15 output push-pull states and
data values are preserved in Standby mode.
The output mechanism follows the priority order shown in Table 24-2 and Table 24-3
(1)
Table 24-1 RTC pin PC13 configuration
Pin RTC_TAMP1 RTC_TS RTC_ALARM RTC_CALIB
configuration output input output output PC13MODE PC13VALUE
and function enabled enabled enabled enabled
RTC_TAMP1
1 0 Don’t care Don’t care Don’t care Don’t care
input floating
RTC_TS and
RTC_TAMP1 1 1 Don’t care Don’t care Don’t care Don’t care
input floating
RTC_TS
0 1 Don’t care Don’t care Don’t care Don’t care
input floating
RTC_ALARM
0 0 1 Don’t care Don’t care 0
output OD
RTC_ALARM
0 0 1 Don’t care Don’t care 1
output PP
RTC_CALIB
0 0 0 1 Don’t care Don’t care
output PP
Output PP PC13 output
0 0 0 0 1
forced data value
Wakeup pin or
0 0 0 0 0 Don’t care
Standard GPIO

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1. OD: open drain; PP: push-pull.


(1)
Table 24-2 LSE pin PC14 configuration
Pin configuration LSEON bit in LSEBYP bit in PC14MODE PC14VALUE
and function RCC_BDCR register RCC_BDCR register bit bit
LSE oscillator 1 0 Don’t care Don’t care
LSE bypass 1 1 Don’t care Don’t care
PC14 output
Output PP forced 0 Don’t care 1
data value
Standard GPIO 0 Don’t care 0 Don’t care
1. OD: open drain; PP: push-pull.
(1)
Table 24-3 LSE pin PC15 configuration
Pin configuration LSEON bit in LSEBYP bit in PC15MODE PC15VALUE
and function RCC_BDCR register RCC_BDCR register bit bit
LSE oscillator 1 0 Don’t care Don’t care
1 1 PC15 output
Output PP forced 1
0 Don’t care data value
Standard GPIO 0 Don’t care 0 Don’t care
1. OD: open drain; PP: push-pull.

24.3.3. Clock and prescalers

The RTC clock source (RTCCLK) is selected through the clock controller among the LSE clock, the LSI
oscillator clock, and the HSE clock. For more information on the RTC clock source configuration, refer to
section 7 RCC
A programmable prescaler stage generates a 1 Hz clock which is used to update the calendar. To minimize
power consumption, the prescaler is split into 2 programmable prescalers (see Figure 24-1 RTC block
diagram):
 A 7-bit asynchronous prescaler configured through the PREDIV_A bits of the RTC_PRER register.
 A 15-bit synchronous prescaler configured through the PREDIV_S bits of the RTC_PRER register.
Note: When both prescalers are used, it is recommended to configure the asynchronous prescaler to a high
value to minimize consumption.
The asynchronous prescaler division factor is set to 128, and the synchronous division factor to 256, to
obtain an internal clock frequency of 1 Hz (ck_spre) with an LSE frequency of 32.768 kHz.
The minimum division factor is 1 and the maximum division factor is 2 22. This corresponds to a maximum
input frequency of around 4 MHz.
fCK_APRE is given by the following formula:

f RTCCLK
f CK_APRE 
PREDIV_A 1

he ck_apre clock is used to clock the binary RTC_SSR subseconds downcounter. When it reaches 0,
RTC_SSR is reloaded with the content of PREDIV_S.
fck_apre is given by the following formula:

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f RTCCLK
f CK_SPRE 
(PREDIV_S  1)  (PREDIV_A  1)

The ck_spre clock can be used either to update the calendar

24.3.4. Real-time clock and calendar

The RTC calendar time and date registers are accessed through shadow registers which are synchronized
with PCLK (APB clock). They can also be accessed directly in order to avoid waiting for the synchronization
duration.
 RTC_SSR for the subseconds
 RTC_TR for the time
 RTC_DR for the date
Every two RTCCLK periods, the current calendar value is copied into the shadow registers, and the RSF bit
of RTC_ISR register is set (see section 24.7.4: RTC initialization and status register). The copy is not
performed in Stop and Standby mode. When exiting these modes, the shadow registers are updated after up
to 2 RTCCLK periods.
When the application reads the calendar registers, it accesses the content of the shadow registers. It is
possible to make a direct access to the calendar registers by setting the BYPSHAD control bit in the
RTC_CR register. By default, this bit is cleared, and the user accesses the shadow registers.
When reading the RTC_SSR, RTC_TR or RTC_DR registers in BYPSHAD=0 mode, the frequency of the
APB clock (fAPB) must be at least 7 times the frequency of the RTC clock (fRTCCLK).
The shadow registers are reset by system reset.

24.3.5. Programmable alarm

The RTC unit provides programmable alarm: Alarm A.


The programmable alarm function is enabled through the ALRAE bit in the RTC_CR register. The ALRAF is
set to 1 if the calendar subseconds, seconds, minutes, hours, date or day match the values programmed in
the alarm registers RTC_ALRMASSR and RTC_ALRMAR. Each calendar field can be independently
selected through the MSKx bits of the RTC_ALRMAR register, and through the MASKSSx bits of the
RTC_ALRMASSR register. The alarm interrupt is enabled through the ALRAIE bit in the RTC_CR register.
Note: If the seconds field is selected (MSK1 bit reset in RTC_ALRMAR), the synchronous prescaler division
factor set in the RTC_PRER register must be at least 3 to ensure correct behavior.
Alarm A (if enabled by bits OSEL[1:0] in RTC_CR register) can be routed to the RTC_ALARM output.
RTC_ALARM output polarity can be configured through bit POL the RTC_CR register.

24.3.6. RTC initialization and configuration

RTC register access


The RTC registers are 32-bit registers. The APB interface introduces 2 wait-states in RTC register accesses

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except on read accesses to calendar shadow registers when BYPSHAD=0.

RTC register write protection


After system reset, the RTC registers are protected against parasitic write access by clearing the DBP bit in
the PWR_CR register (refer to the power control section). DBP bit must be set in order to enable RTC
registers write access.
After RTC ___domain reset, all the RTC registers are write-protected. Writing to the RTC registers is enabled by
writing a key into the Write Protection register, RTC_WPR.
The following steps are required to unlock the write protection on all the RTC registers except for
RTC_TAFCR, RTC_BKPxR and RTC_ISR[13:8]:
1. Write ‘0xCA’ into the RTC_WPR register.
2. Write ‘0x53’ into the RTC_WPR register.
Writing a wrong key reactivates the write protection.
The protection mechanism is not affected by system reset.

Calendar initialization and configuration


To program the initial time and date calendar values, including the time format and the prescaler
configuration, the following sequence is required:
1. Set INIT bit to 1 in the RTC_ISR register to enter initialization mode. In this mode, the calendar counter
is stopped and its value can be updated.
2. Poll INITF bit of in the RTC_ISR register. The initialization phase mode is entered when INITF is set to 1.
It takes around 2 RTCCLK clock cycles (due to clock synchronization).
3. To generate a 1 Hz clock for the calendar counter, program both the prescaler factors in RTC_PRER
register.
4. Load the initial time and date values in the shadow registers (RTC_TR and RTC_DR), and configure the
time format (12 or 24 hours) through the FMT bit in the RTC_CR register.
5. Exit the initialization mode by clearing the INIT bit. The actual calendar counter value is then
automatically loaded and the counting restarts after 4 RTCCLK clock cycles.
When the initialization sequence is complete, the calendar starts counting.
Note: After a system reset, the application can read the INITS flag in the RTC_ISR register to check if the
calendar has been initialized or not. If this flag equals 0, the calendar has not been initialized since the year
field is set at its RTC ___domain reset default value (0x00).
Note: To read the calendar after initialization, the software must first check that the RSF flag is set in the
RTC_ISR register.

Daylight saving time


The daylight saving time management is performed through bits SUB1H, ADD1H, and BKP of the RTC_CR
register.
Using SUB1H or ADD1H, the software can subtract or add one hour to the calendar in one single operation
without going through the initialization procedure.
In addition, the software can use the BKP bit to memorize this operation.

Programming the alarm

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A similar procedure must be followed to program or update the programmable alarms.


1. Clear ALRAE in RTC_CR to disable Alarm A.
2. Program the Alarm A registers (RTC_ALRMASSR/RTC_ALRMAR);
3. Set ALRAE in the RTC_CR register to enable Alarm A again.
Note: Each change of the RTC_CR register is taken into account after around 2 RTCCLK clock cycles due to
clock synchronization.

24.3.7. Reading the calendar

When BYPSHAD control bit is cleared in the RTC_CR register


To read the RTC calendar registers (RTC_SSR, RTC_TR and RTC_DR) properly, the APB clock frequency
(fPCLK) must be equal to or greater than seven times the RTC clock frequency (fRTCCLK). This ensures a
secure behavior of the synchronization mechanism.
If the APB clock frequency is less than seven times the RTC clock frequency, the software must read the
calendar time and date registers twice. If the second read of the RTC_TR gives the same result as the first
read, this ensures that the data is correct. Otherwise a third read access must be done. In any case the APB
clock frequency must never be lower than the RTC clock frequency.
The RSF bit is set in RTC_ISR register each time the calendar registers are copied into the RTC_SSR,
RTC_TR and RTC_DR shadow registers. The copy is performed every two RTCCLK cycles. To ensure
consistency between the 3 values, reading either RTC_SSR or RTC_TR locks the values in the higher-order
calendar shadow registers until RTC_DR is read. In case the software makes read accesses to the calendar
in a time interval smaller than 2 RTCCLK periods: RSF must be cleared by software after the first calendar
read, and then the software must wait until RSF is set before reading again the RTC_SSR, RTC_TR and
RTC_DR registers.
After waking up from low-power mode (Stop or Standby), RSF must be cleared by software. The software
must then wait until it is set again before reading the RTC_SSR, RTC_TR and RTC_DR registers.
The RSF bit must be cleared after wakeup and not before entering low-power mode.
After a system reset, the software must wait until RSF is set before reading the RTC_SSR, RTC_TR and
RTC_DR registers. Indeed, a system reset resets the shadow registers to their default values.
After an initialization (refer to Calendar initialization and configuration): the software must wait until RSF is
set before reading the RTC_SSR, RTC_TR and RTC_DR registers.
After synchronization (refer to 24.3.9 the software must wait until RSF is set before reading the RTC_SSR,
RTC_TR and RTC_DR registers.)

When the BYPSHAD control bit is set in the RTC_CR register (bypass shadow registers)
Reading the calendar registers gives the values from the calendar counters directly, thus eliminating the
need to wait for the RSF bit to be set. This is especially useful after exiting from low-power modes (STOP or
Standby), since the shadow registers are not updated during these modes.
When the BYPSHAD bit is set to 1, the results of the different registers might not be coherent with each
other if an RTCCLK edge occurs between two read accesses to the registers. Additionally, the value of one
of the registers may be incorrect if an RTCCLK edge occurs during the read operation. The software must
read all the registers twice, and then compare the results to confirm that the data is coherent and correct.
Alternatively, the software can just compare the two results of the least-significant calendar register.

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Note: While BYPSHAD=1, instructions which read the calendar registers require one extra APB cycle to
complete.

24.3.8. Resetting the RTC

The calendar shadow registers (RTC_SSR, RTC_TR and RTC_DR) and some bits of the RTC status
register (RTC_ISR) are reset to their default values by all available system reset sources.
On the contrary, the following registers are reset to their default values by a RTC ___domain reset and are not
affected by a system reset: the RTC current calendar registers, the RTC control register (RTC_CR), the
prescaler register (RTC_PRER), the RTC calibration register (RTC_CALR), the RTC shift register
(RTC_SHIFTR), the RTC timestamp registers (RTC_TSSSR, RTC_TSTR and RTC_TSDR), the RTC
tamper and alternate function configuration register (RTC_TAFCR), the RTC backup registers (RTC_BKPxR),
the wakeup timer register (RTC_WUTR), the Alarm A registers (RTC_ALRMASSR/RTC_ALRMAR).
In addition, the RTC keeps on running under system reset if the reset source is different from the RTC
___domain reset one. When a RTC ___domain reset occurs, the RTC is stopped and all the RTC registers are set to
their reset values.

24.3.9. RTC synchronization

The RTC can be synchronized to a remote clock with a high degree of precision. After reading the
sub-second field (RTC_SSR or RTC_TSSSR), a calculation can be made of the precise offset between the
times being maintained by the remote clock and the RTC. The RTC can then be adjusted to eliminate this
offset by “shifting” its clock by a fraction of a second using RTC_SHIFTR.
RTC_SSR contains the value of the synchronous prescaler counter. This allows one to calculate the exact
time being maintained by the RTC down to a resolution of 1 / (PREDIV_S + 1) seconds. As a consequence,
the resolution can be improved by increasing the synchronous prescaler value (PREDIV_S[14:0]. The
maximum resolution allowed (30.52 μs with a 32768 Hz clock) is obtained with PREDIV_S set to 0x7FFF.
However, increasing PREDIV_S means that PREDIV_A must be decreased in order to maintain the
synchronous prescaler output at 1 Hz. In this way, the frequency of the asynchronous prescaler output
increases, which may increase the RTC dynamic consumption.
The RTC can be finely adjusted using the RTC shift control register (RTC_SHIFTR). Writing to
RTC_SHIFTR can shift (either delay or advance) the clock by up to a second with a resolution of 1 /
(PREDIV_S + 1) seconds. The shift operation consists of adding the SUBFS[14:0] value to the synchronous
prescaler counter SS[15:0]: this will delay the clock. If at the same time the ADD1S bit is set, this results in
adding one second and at the same time subtracting a fraction of second, so this will advance the clock.
As soon as a shift operation is initiated by a write to the RTC_SHIFTR register, the SHPF flag is set by
hardware to indicate that a shift operation is pending. This bit is cleared by hardware as soon as the shift
operation has completed.
Note: This synchronization feature is not compatible with the reference clock detection feature: firmware
must not write to RTC_SHIFTR when REFCKON=1.

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24.3.10. RTC reference clock detection

The update of the RTC calendar can be synchronized to a reference clock, RTC_REFIN, which is usually
the mains frequency (50 or 60 Hz). The precision of the RTC_REFIN reference clock should be higher than
the 32.768 kHz LSE clock. When the RTC_REFIN detection is enabled (REFCKON bit of RTC_CR set to 1),
the calendar is still clocked by the LSE, and RTC_REFIN is used to compensate for the imprecision of the
calendar update frequency (1 Hz).
Each 1 Hz clock edge is compared to the nearest RTC_REFIN clock edge (if one is found within a given time
window). In most cases, the two clock edges are properly aligned. When the 1 Hz clock becomes misaligned
due to the imprecision of the LSE clock, the RTC shifts the 1 Hz clock a bit so that future 1 Hz clock edges
are aligned. Thanks to this mechanism, the calendar becomes as precise as the reference clock.
The RTC detects if the reference clock source is present by using the 256 Hz clock (ck_apre) generated
from the 32.768 kHz quartz. The detection is performed during a time window around each of the calendar
updates (every 1 s). The window equals 7 ck_apre periods when detecting the first reference clock edge. A
smaller window of 3 ck_apre periods is used for subsequent calendar updates.
Each time the reference clock is detected in the window, the asynchronous prescaler which outputs the
ck_apre clock is forced to reload. This has no effect when the reference clock and the 1 Hz clock are aligned
because the prescaler is being reloaded at the same moment. When the clocks are not aligned, the reload
shifts future 1 Hz clock edges a little for them to be aligned with the reference clock.
If the reference clock halts (no reference clock edge occurred during the 3 ck_apre window), the calendar is
updated continuously based solely on the LSE clock. The RTC then waits for the reference clock using a
large 7 ck_apre period detection window centered on the ck_spre edge.
When the RTC_REFIN detection is enabled, PREDIV_A and PREDIV_S must be set to their default values:
 PREDIV_A = 0x007F
 PREDIV_S = 0x00FF
Note: RTC_REFIN clock detection is not available in Standby mode.

24.3.11. RTC smooth digital calibration

The RTC frequency can be digitally calibrated with a resolution of about 0.954 ppm with a range from -487.1
ppm to +488.5 ppm. The correction of the frequency is performed using series of small adjustments (adding
and/or subtracting individual RTCCLK pulses). These adjustments are fairly well distributed so that the RTC
is well calibrated even when observed over short durations of time.
The smooth digital calibration is performed during a cycle of about 220 RTCCLK pulses, or 32 seconds when
the input frequency is 32768 Hz. This cycle is maintained by a 20-bit counter, cal_cnt[19:0], clocked by
RTCCLK.
The smooth calibration register (RTC_CALR) specifies the number of RTCCLK clock cycles to be masked
during the 32-second cycle:
 Setting the bit CALM[0] to 1 causes exactly one pulse to be masked during the 32- second cycle.
 Setting CALM[1] to 1 causes two additional cycles to be masked
 Setting CALM[2] to 1 causes four additional cycles to be masked
 and so on up to CALM[8] set to 1 which causes 256 clocks to be masked.

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Note: CALM[8:0] (RTC_CALR) specifies the number of RTCCLK pulses to be masked during the 32-second
cycle. Setting the bit CALM[0] to ‘1’ causes exactly one pulse to be masked during the 32-second cycle at
the moment when cal_cnt[19:0] is 0x80000; CALM[1]=1 causes two other cycles to be masked (when
cal_cnt is 0x40000 and 0xC0000); CALM[2]=1 causes four other cycles to be masked (cal_cnt =
0x20000/0x60000/0xA0000/ 0xE0000); and so on up to CALM[8]=1 which causes 256 clocks to be masked
(cal_cnt = 0xXX800).
While CALM allows the RTC frequency to be reduced by up to 487.1 ppm with fine resolution, the bit CALP
can be used to increase the frequency by 488.5 ppm. Setting CALP to ‘1’ effectively inserts an extra
RTCCLK pulse every 211 RTCCLK cycles, which means that 512 clocks are added during every 32-second
cycle.
Using CALM together with CALP, an offset ranging from -511 to +512 RTCCLK cycles can be added during
the 32-second cycle, which translates to a calibration range of -487.1 ppm to +488.5 ppm with a resolution of
about 0.954 ppm.
The formula to calculate the effective calibrated frequency (F CAL) given the input frequency (FRTCCLK) is as
follows:
20
F CAL  F RTCCLK  [1  (CALP  512  CALM) / (2  CALM  CALP  512) ]

Calibration when PREDIV_A<3


The CALP bit can not be set to 1 when the asynchronous prescaler value (PREDIV_A bits in RTC_PRER
register) is less than 3. If CALP was already set to 1 and PREDIV_A bits are set to a value less than 3, CALP
is ignored and the calibration operates as if CALP was equal to 0.
To perform a calibration with PREDIV_A less than 3, the synchronous prescaler value (PREDIV_S) should
be reduced so that each second is accelerated by 8 RTCCLK clock cycles, which is equivalent to adding 256
clock cycles every 32 seconds. As a result, between 255 and 256 clock pulses (corresponding to a
calibration range from 243.3 to 244.1 ppm) can effectively be added during each 32-second cycle using only
the CALM bits.
With a nominal RTCCLK frequency of 32768 Hz, when PREDIV_A equals 1 (division factor of 2), PREDIV_S
should be set to 16379 rather than 16383 (4 less). The only other interesting case is when PREDIV_A
equals 0, PREDIV_S should be set to 32759 rather than 32767 (8 less).
If PREDIV_S is reduced in this way, the formula given the effective frequency of the calibrated input clock is
as follows:
20
F CAL  F RTCCLK  [1  (256  CALM) / (2  CALM  256) ]
In this case, CALM[7:0] equals 0x100 (the midpoint of the CALM range) is the correct setting if RTCCLK is
exactly 32768.00 Hz.

Verifying the RTC calibration


RTC precision is ensured by measuring the precise frequency of RTCCLK and calculating the correct CALM
value and CALP values. An optional 1 Hz output is provided to allow applications to measure and verify the
RTC precision.
Measuring the precise frequency of the RTC over a limited interval can result in a measurement error of up
to 2 RTCCLK clock cycles over the measurement period, depending on how the digital calibration cycle is
aligned with the measurement period.
However, this measurement error can be eliminated if the measurement period is the same length as the

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Fremont Micro Devices FT32F0xxx8 RM

calibration cycle period. In this case, the only error observed is the error due to the resolution of the digital
calibration.
 By default, the calibration cycle period is 32 seconds.
Using this mode and measuring the accuracy of the 1 Hz output over exactly 32 seconds guarantees that the
measure is within 0.477 ppm (0.5 RTCCLK cycles over 32 seconds, due to the limitation of the calibration
resolution).
 CALW16 bit of the RTC_CALR register can be set to 1 to force a 16- second calibration cycle period.
In this case, the RTC precision can be measured during 16 seconds with a maximum error of 0.954 ppm
(0.5 RTCCLK cycles over 16 seconds). However, since the calibration resolution is reduced, the long term
RTC precision is also reduced to 0.954 ppm: CALM[0] bit is stuck at 0 when CALW16 is set to 1.
 CALW8 bit of the RTC_CALR register can be set to 1 to force a 8- second calibration cycle period.
In this case, the RTC precision can be measured during 8 seconds with a maximum error of 1.907 ppm (0.5
RTCCLK cycles over 8s). The long term RTC precision is also reduced to 1.907 ppm: CALM[1:0] bits are
stuck at 00 when CALW8 is set to 1.

Re-calibration on-the-fly
The calibration register (RTC_CALR) can be updated on-the-fly while RTC_ISR/INITF=0, by using the follow
process:
1. Poll the RTC_ISR/RECALPF (re-calibration pending flag).
2. If it is set to 0, write a new value to RTC_CALR, if necessary. RECALPF is then automatically set to 1
3. Within three ck_apre cycles after the write operation to RTC_CALR, the new calibration settings take
effect.

24.3.12. Time-stamp function

Time-stamp is enabled by setting the TSE bit of RTC_CR register to 1.


The calendar is saved in the time-stamp registers (RTC_TSSSR, RTC_TSTR, RTC_TSDR) when a
time-stamp event is detected on the RTC_TS pin.
When a time-stamp event occurs, the time-stamp flag bit (TSF) in RTC_ISR register is set.
By setting the TSIE bit in the RTC_CR register, an interrupt is generated when a time-stamp event occurs.
If a new time-stamp event is detected while the time-stamp flag (TSF) is already set, the time-stamp
overflow flag (TSOVF) flag is set and the time-stamp registers (RTC_TSTR and RTC_TSDR) maintain the
results of the previous event.
Note: TSF is set 2 ck_apre cycles after the time-stamp event occurs due to synchronization process.
There is no delay in the setting of TSOVF. This means that if two time-stamp events are close together,
TSOVF can be seen as ‘1’ while TSF is still ‘0’. As a consequence, it is recommended to poll TSOVF only
after TSF has been set.
Note: If a time-stamp event occurs immediately after the TSF bit is supposed to be cleared, then both TSF
and TSOVF bits are set.To avoid masking a time-stamp event occurring at the same moment, the application
must not write ‘0’ into TSF bit unless it has already read it to ‘1’.
Optionally, a tamper event can cause a time-stamp to be recorded. See the description of the TAMPTS
control bit in RTC_TAFCR

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24.3.13. Tamper detection

The RTC_TAMPx input events can be configured either for edge detection, or for level detection with
filtering.
The tamper detection can be configured for the following purposes:
 Generate an interrupt
 Capable to wakeup from Stop and Standby modes

Tamper detection initialization


Each input can be enabled by setting the corresponding TAMPxE bits to 1 in the RTC_TAFCR register.
Each RTC_TAMPx tamper detection input is associated with a flag TAMPxF in the RTC_ISR register.
The TAMPxF flag is asserted after the tamper event on the pin, with the latency provided below:
 3 ck_apre cycles when TAMPFLT differs from 0x0 (Level detection with filtering)
 3 ck_apre cycles when TAMPTS=1 (Timestamp on tamper event)
 No latency when TAMPFLT=0x0 (Edge detection) and TAMPTS=0
A new tamper occurring on the same pin during this period and as long as TAMPxF is set cannot be
detected.
By setting the TAMPIE bit in the RTC_TAFCR register, an interrupt is generated when a tamper detection
event occurs.

Timestamp on tamper event


With TAMPTS set to ‘1’, any tamper event causes a timestamp to occur. In this case, either the TSF bit or
the TSOVF bit are set in RTC_ISR, in the same manner as if a normal timestamp event occurs. The affected
tamper flag register TAMPxF is set at the same time that TSF or TSOVF is set.

Edge detection on tamper inputs


If the TAMPFLT bits are “00”, the RTC_TAMPx pins generate tamper detection events when either a rising
edge or a falling edge is observed depending on the corresponding TAMPxTRG bit. The internal pull-up
resistors on the RTC_TAMPx inputs are deactivated when edge detection is selected.
Note: To avoid losing tamper detection events, the signal used for edge detection is logically ANDed with the
corresponding TAMPxE bit in order to detect a tamper detection event in case it occurs before the
RTC_TAMPx pin is enabled.
 When TAMPxTRG = 0: if the RTC_TAMPx alternate function is already high before tamper detection is
enabled (TAMPxE bit set to 1), a tamper event is detected as soon as the RTC_TAMPx input is enabled,
even if there was no rising edge on the RTC_TAMPx input after TAMPxE was set.
 When TAMPxTRG = 1: if the RTC_TAMPx alternate function is already low before tamper detection is
enabled, a tamper event is detected as soon as the RTC_TAMPx input is enabled even if there was no
falling edge on the RTC_TAMPx input after TAMPxE was set.

Level detection with filtering on RTC_TAMPx inputs


Level detection with filtering is performed by setting TAMPFLT to a non-zero value. A tamper detection event
is generated when either 2, 4, or 8 (depending on TAMPFLT) consecutive samples are observed at the level

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designated by the TAMPxTRG bits.


The RTC_TAMPx inputs are precharged through the I/O internal pull-up resistance before its state is
sampled, unless disabled by setting TAMPPUDIS to 1,The duration of the precharge is determined by the
TAMPPRCH bits, allowing for larger capacitances on the RTC_TAMPx inputs.
The trade-off between tamper detection latency and power consumption through the pull-up can be
optimized by using TAMPFREQ to determine the frequency of the sampling for level detection.
Note: Refer to the datasheets for the electrical characteristics of the pull-up resistors.

24.3.14. Calibration clock output

When the COE bit is set to 1 in the RTC_CR register, a reference clock is provided on the RTC_CALIB
device output.
If the COSEL bit in the RTC_CR register is reset and PREDIV_A = 0x7F, the RTC_CALIB frequency is
fRTCCLK/64. This corresponds to a calibration output at 512 Hz for an RTCCLK frequency at 32.768 kHz. The
RTC_CALIB duty cycle is irregular: there is a light jitter on falling edges. It is therefore recommended to use
rising edges.
When COSEL is set and “PREDIV_S+1” is a non-zero multiple of 256 (i.e: PREDIV_S[7:0] = 0xFF), the
RTC_CALIB frequency is fRTCCLK/(256 * (PREDIV_A+1)). This corresponds to a calibration output at 1 Hz
for prescaler default values (PREDIV_A = 0x7F, PREDIV_S = 0xFF), with an RTCCLK frequency at 32.768
kHz.
Note: When the RTC_CALIB or RTC_ALARM output is selected, the RTC_OUT pin is automatically
configured in output alternate function.
When COSEL is cleared, RTC_CALIB output is level 6 of asynchronous prescaler.
When COSEL is set, RTC_CALIB output is level 8 of synchronous prescaler.

24.3.15. Alarm output

The OSEL[1:0] control bits in the RTC_CR register are used to activate the alarm alternate function output
RTC_ALARM, and to select the function which is output. These functions reflect the contents of the
corresponding flags in the RTC_ISR register.
The polarity of the output is determined by the POL control bit in RTC_CR so that the opposite of the
selected flag bit is output when POL is set to 1.
Alarm alternate function output
The RTC_ALARM pin can be configured in output open drain or output push-pull using the control bit
PC13VALUE in the RTC_TAFCR register.
Note: Once the RTC_ALARM output is enabled, it has priority over RTC_CALIB (COE bit is don’t care and
must be kept cleared).
When the RTC_CALIB or RTC_ALARM output is selected, the RTC_OUT pin is automatically configured in
output alternate function.

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24.4. RTC low-power modes

Table 24-4 Effect of low-power modes on RTC


Mode Description
Sleep No effect
RTC interrupts cause the device to exit the Sleep mode.
Stop The RTC remains active when the RTC clock source is LSE or LSI. RTC alarm, RTC tamper
event, RTC timestamp event, and RTC Wakeup cause the device to exit the Stop mode.
Standby The RTC remains active when the RTC clock source is LSE or LSI. RTC alarm, RTC tamper
event, RTC timestamp event, and RTC Wakeup cause the device to exit the Standby mode.

24.5. RTC interrupts

All RTC interrupts are connected to the EXTI controller


To enable RTC interrupt(s), the following sequence is required:
1. Configure and enable the EXTI line(s) corresponding to the RTC event(s) in interrupt mode and select
the rising edge sensitivity.
2. Configure and enable the RTC IRQ channel in the NVIC.
3. Configure the RTC to generate RTC interrupt(s).
Table 24-5 Interrupt control bits
Event Enable Exit the Sleep Exit the Stop Exit the Standby
Interrupt event
flag control bit mode mode mode
(1) (1)
Alarm A ALRAF ALRAIE yes yes yes
RTC_TS input (1) (1)
TSF TSIE yes yes yes
(timestamp)
RTC_TAMP1 input (1) (1)
TAMP1F TAMPIE yes yes yes
detection
RTC_TAMP2 input (1) (1)
TAMP2F TAMPIE yes yes yes
detection
1. Wakeup from STOP and Standby modes is possible only when the RTC clock source is LSE or LSI.

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24.6. RTC register map

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17
16

15

14

13

12

11

10
Offset Register

8
7

0
HT

PM
RTC_TR HU[3:0] MNT[2:0] MNU[3:0] ST[2:0] SU[3:0]
–

–
0x00 [1:0]
Reset x x x x x x x x x 0 0 0 0 0 0 0 x 0 0 0 0 0 0 0 x 0 0 0 0 0 0 0
DT

MT
RTC_DR YT[3:0] YU[3:0] WDU[2:0] MU[3:0] DU[3:0]
–

–
0x04 [1:0]
Reset x x x x x x x x 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 x x 0 0 0 0 0 1

REFCKON
BYPSHAD

TSEDGE
ALRAIE
COSEL

SUB1H
ADD1H

ALRAE
OSEL

TSIE

FMT
COE

POL

BKP

TSE
–

–
RTC_CR
0x08

Reset x x x x x x x x 0 x 0 0 0 0 0 0 0 x x 0 0 x x 0 x 0 0 0 0 x x x

RECALPF

ALRAWF
TAMP2F

TAMP1F
TSOVF

ALRAF

INITF

SHPF
INITS
INIT
TSF

RSF
RTC_ISR
–

–
0x0C

Reset x x x x x x x x x x x x x x x 0 x 0 0 0 0 x x 0 0 0 0 0 0 x x 1
RTC_PRER PREDIV_A[6:0] PREDIV_S[14:0]
–

–
0x10
Reset x x x x x x x x x 1 1 1 1 1 1 1 x 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
WDSEL
MSK4

MSK3

MSK2

MSK1
DT HT
PM

RTC_ALRMAR DU[3:0] HU[3:0] MNT[2:0] MNU[3:0] ST[2:0] SU[3:0]


0x1C [1:0] [1:0]

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RTC_WPR KEY[7:0]
–

–
–

–
–

–
0x24
Reset x x x x x x x x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0
RTC_SSR SS[15:0]
–

–
–

–
–

0x28
Reset x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ADD1S

SUBFS[14:0]
–

–
–

RTC_SHIFTR
0x2C

Reset 0 x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HT
PM

HU[3:0] MNT[2:0] MNU[3:0] ST[2:0] SU[3:0]


–

–
RTC_TSTR
0x30 [1:0]
Reset x x x x x x x x x 0 0 0 0 0 0 0 x 0 0 0 0 0 0 0 x 0 0 0 0 0 0 0
DT
MT

WDU[2:0] MU[3:0] DU[3:0]


–

–
–

–
RTC_TSDR
0x34 [1:0]
Reset x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 x x 0 0 0 0 0 0
RTC_TSSSR SS[15:0]
–

–
–

0x38
Reset x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CALW16
CALW8
CALP

RTC_CALR CALM[8:0]
–

–
–

–
–

0x3C

Reset x x x x x x x x x x x x x x x x 0 0 0 x x x x 0 0 0 0 0 0 0 0 0
TAMPPUDIS
PC15VALUE

PC14VALUE

PC13VALUE

TAMPPRCH

TAMPFREQ

TAMP2TRG

TAMP1TRG
PC15MODE

PC14MODE

PC13MODE

TAMPFLT

TAMPTS

TAMP2E

TAMP1E
TAMPIE
[1:0]
[1:0]

[2:0]

RTC_TAFCR
–

–
–

0x40

Reset x x x x x x x x 0 0 0 0 0 0 x x 0 0 0 0 0 0 0 0 0 x x 0 0 0 0 0
MASKSS
SS[14:0]
–

–
–

–
–

RTC_ALRMASSR
0x44 [3:0]
Reset x x x x 0 0 0 0 x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

24.6.1. RTC_TR

The RTC_TR is the calendar time shadow register. This register must be written in initialization mode only.
Refer to Calendar initialization and configuration and Reading the calendar
This register is write protected. The write access procedure is described in “RTC register write protection”
Address offset: 0x00
RTC ___domain reset value: 0x0000 0000

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System reset: 0x0000 0000 when BYPSHAD = 0. Not affected when BYPSHAD = 1.

Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0


31:24 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 — PM HT[1:0] HU[3:0]
Type RO-0 RW RW RW RW RW RW RW
15:8 — MNT[2:0] MNU[3:0]
Type RO-0 RW RW RW RW RW RW RW
7:0 — ST[2:0] SU[3:0]
Type RO-0 RW RW RW RW RW RW RW

Bit Name Function


31:23 NA Reserved
22 PM AM/PM notation
0: AM or 24-hour format
1: PM
21:20 HT[1:0] Hour tens in BCD format
19:16 HU[3:0] Hour units in BCD format
15 NA Reserved
14:12 MNT[2:0] Minute tens in BCD format
11:8 MNU[3:0] Minute units in BCD format
7 NA Reserved
6:4 ST[2:0] Second tens in BCD format
3:0 SU[3:0] Second units in BCD format

24.6.2. RTC_DR

The RTC_DR is the calendar date shadow register. This register must be written in initialization mode only.
Refer to Calendar initialization and configuration and Reading the calendar
This register is write protected. The write access procedure is described in “RTC register write protection”
Address offset: 0x04
RTC ___domain reset value: 0x0000 2101
System reset: 0x0000 2101 when BYPSHAD = 0. Not affected when BYPSHAD = 1.

Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0


31:24 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 YT[3:0] YU[3:0]
Type RW RW RW RW RW RW RW RW
15:8 WDU[2:0] MT MU[3:0]
Type RW RW RW RW RW RW RW RW

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7:0 — DT[1:0] DU[3:0]


Type RO-0 RO-0 RW RW RW RW RW RW

Bit Name Function


31:24 NA Reserved
23:20 YT[3:0] Year tens in BCD format
19:16 YU[3:0] Year units in BCD format
15:13 WDU[2:0] Week day units
000: forbidden
001: Monday
...
111: Sunday
12 MT Month tens in BCD format
11:8 MU[3:0] Month units in BCD format
7:6 NA Reserved
5:4 DT[1:0] Date tens in BCD format
3:0 DU[3:0] Date units in BCD format

24.6.3. RTC_CR

Address offset: 0x08


RTC ___domain reset value: 0x0000 0000
System reset: not affected

Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0


31:24 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 COE — OSEL POL COSEL BKP SUB1H ADD1H
Type RW RO-0 RW RW RW RW WO WO
15:8 TSIE — ALRAIE TSE — ALRAE
Type RW RO RO RW RW RO-0 RO-0 RW
7:0 — FMT BYPSHAD REFCKON TSEDGE —
Type RO-0 RW RW RW RW RO-0 RO-0 RO-0

Bit Name Function


31:24 NA Reserved
23 COE Calibration output enable
This bit enables the RTC_CALIB output
0: Calibration output disabled
1: Calibration output enabled
22 NA Reserved
21 OSEL Output selection

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Fremont Micro Devices FT32F0xxx8 RM

These bits are used to select the flag to be routed to RTC_ALARM output
0: Output disabled
1: Alarm A output enabled
20 POL Output polarity
This bit is used to configure the polarity of RTC_ALARM output
0: The pin is high when ALRAF is asserted
1: The pin is low when ALRAF is asserted
19 COSEL Calibration output selection
When COE=1, this bit selects which signal is output on RTC_CALIB
0: Calibration output is 512 Hz
1: Calibration output is 1 Hz
These frequencies are valid for RTCCLK at 32.768 kHz and prescalers at
their default values (PREDIV_A=127 and PREDIV_S=255). Refer to section
24.3.14: calibration clock output
18 BKP Backup
This bit can be written by the user to memorize whether the daylight saving
time change has been performed or not.
17 SUB1H Subtract 1 hour (winter time change)
When this bit is set outside initialization mode, 1 hour is subtracted to the
calendar time if the current hour is not 0. This bit is always read as 0.
Setting this bit has no effect when current hour is 0.
0: No effect
1: Subtracts 1 hour to the current time. This can be used for winter time
change
16 ADD1H Add 1 hour (summer time change)
When this bit is set outside initialization mode, 1 hour is added to the
calendar time. This bit is always read as 0.
0: No effect
1: Adds 1 hour to the current time. This can be used for summer time change
15 TSIE Time-stamp interrupt enable
0: Time-stamp Interrupt disable
1: Time-stamp Interrupt enable
14:13 NA Reserved
12 ALRAIE Alarm A interrupt enable
0: Alarm A interrupt disabled
1: Alarm A interrupt enabled
11 TSE timestamp enable
0: timestamp disable
1 Alarm A enable: timestamp enable
10:9 NA Reserved
8 ALRAE Alarm A enable
0: Alarm A disabled
1: Alarm A enabled

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7 NA Reserved
6 FMT Hour format
0: 24 hour/day format
1: AM/PM hour format
5 BYPSHAD Bypass the shadow registers
0: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR)
are taken from the shadow registers, which are updated once every two
RTCCLK cycles.
1: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR)
are taken directly from the calendar counters.
Note: If the frequency of the APB clock is less than seven times the
frequency of RTCCLK, BYPSHAD must be set to ‘1’
4 REFCKON RTC_REFIN reference clock detection enable (50 or 60 Hz)R
0: RTC_REFIN detection disabled
1: RTC_REFIN detection enabled
Note: PREDIV_S must be 0x00FF.
3 TSEDGE Time-stamp event active edge
0: RTC_TS input rising edge generates a time-stamp event
1: RTC_TS input falling edge generates a time-stamp event
TSE must be reset when TSEDGE is changed to avoid unwanted TSF
setting.
2:0 NA Reserved
Note: Bits 7, 6 and 4 of this register can be written in initialization mode only (RTC_ISR/INITF = 1).
It is recommended not to change the hour during the calendar hour increment as it could mask the
incrementation of the calendar hour.
ADD1H and SUB1H changes are effective in the next second.
This register is write protected. The write access procedure is described in “RTC register write protection”

24.6.4. RTC_ISR

This register is write protected (except for RTC_ISR[13:8] bits). The write access procedure is described in
“RTC register write protection”
Address offset: 0x0C
RTC ___domain reset value: 0x0000 0007
System reset: not affected except INIT, INITF, and RSF bits which are cleared to ‘0’

Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0


31:24 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 — RECALPF
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO
15:8 — TAMP2F TAMP1F TSOVF TSF — ALRAF

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Type RO-0 RC_W0 RC_W0 RC_W0 RC_W0 RO-0 RO-0 RC_W0


7:0 INIT INITF RSF INITS SHPF — ALRAWF
Type RW RO RC_W0 RO RO RO-0 RO-0 RO

Bit Name Function


31:17 NA Reserved
16 RECALPF Recalibration pending Flag
The RECALPF status flag is automatically set to ‘1’ when software writes to
the RTC_CALR register, indicating that the RTC_CALR register is blocked.
When the new calibration settings are taken into account, this bit returns to
‘0’. Refer to “Re-calibration on-the-fly”
15 NA Reserved
14 TAMP2F RTC_TAMP2 detection flag
This flag is set by hardware when a tamper detection event is detected on
the RTC_TAMP2 input.
It is cleared by software writing 0
13 TAMP1F RTC_TAMP1 detection flag
This flag is set by hardware when a tamper detection event is detected on
the RTC_TAMP1 input.
It is cleared by software writing 0
12 TSOVF Time-stamp overflow flag
This flag is set by hardware when a time-stamp event occurs while TSF is
already set.
This flag is cleared by software by writing 0. It is recommended to check and
then clear. TSOVF only after clearing the TSF bit. Otherwise, an overflow
might not be noticed if a time- stamp event occurs immediately before the
TSF bit is cleared.
11 TSF Time-stamp flag
This flag is set by hardware when a time-stamp event occurs.
This flag is cleared by software by writing 0.
10:9 NA Reserved
8 ALRAF Alarm A flag
This flag is set by hardware when the time/date registers (RTC_TR and
RTC_DR) match the Alarm A register (RTC_ALRMAR).
This flag is cleared by software by writing 0.
7 INIT Initialization mode
0: Free running mode
1: Initialization mode used to program time and date register (RTC_TR and
RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and
start counting from the new value when INIT is reset
6 INITF Initialization flag
When this bit is set to 1, the RTC is in initialization state, and the time, date
and prescaler registers can be updated.

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0: Calendar registers update is not allowed


1: Calendar registers update is allowed
5 RSF Registers synchronization flag
This bit is set by hardware each time the calendar registers are copied into
the shadow registers (RTC_SSRx, RTC_TRx and RTC_DRx). This bit is
cleared by hardware in initialization mode, while a shift operation is pending
(SHPF=1), or when in bypass shadow register mode (BYPSHAD=1). This bit
can also be cleared by software.
It is cleared either by software or by hardware in initialization mode.
0: Calendar shadow registers not yet synchronized
1: Calendar shadow registers synchronized
4 INITS Initialization status flag
This bit is set by hardware when the calendar year field is different from 0
(RTC ___domain reset state)
0: Calendar has not been initialized
1: Calendar has been initialized
3 SHPF Shift operation pending
0: No shift operation is pending
1: A shift operation is pending
2:1 NA Reserved
0 ALRAWF Alarm A write flag
This bit is set by hardware when Alarm A values can be changed, after the
ALRAE bit has been set to 0 in RTC_CR.
It is cleared by hardware in initialization mode
0: Alarm A update not allowed
1: Alarm A update allowed
Note: The bits ALRAF, WUTF and TSF are cleared 2 APB clock cycles after programming them to 0.

24.6.5. RTC_PRER

This register must be written in initialization mode only. The initialization must be performed in two separate
write accesses. Refer to Calendar initialization and configuration
This register is write protected. The write access procedure is described in “RTC register write protection”
Address offset: 0x10
RTC ___domain reset value: 0x007F 00FF
System reset: not affected

Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0


31:24 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 — PREDIV_A[6:0]
Type RO-0 RW RW RW RW RW RW RW

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15:8 — PREDIV_S[14:8]
Type RO-0 RW RW RW RW RW RW RW
7:0 PREDIV_S[7:0]
Type RW RW RW RW RW RW RW RW

Bit Name Function


31:23 NA Reserved
22:16 PREDIV_A[6:0] Asynchronous prescaler factor
ck_apre frequency =RTCCLK frequency /(PREDIV_A+1)
15 NA Reserved
14:0 PREDIV_S[14:0] Synchronous prescaler factor
ck_spre frequency =ck_apre frequency /(PREDIV_S+1)

24.6.6. RTC_ALRMAR

This register can be written only when ALRAWF is set to 1 in RTC_ISR, or in initialization mode.
This register is write protected. The write access procedure is described in “RTC register write protection”
Address offset: 0x1C
RTC ___domain reset value: 0x0000 0000
System reset: not affected

Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0


31:24 MSK4 WDSEL DT[1:0] DU[3:0]
Type RW RW RW RW RW RW RW RW
23:16 MSK3 PM HT[1:0] HU[3:0]
Type RW RW RW RW RW RW RW RW
15:8 MSK2 MNT[2:0] MNU[3:0]
Type RW RW RW RW RW RW RW RW
7:0 MSK1 ST[2:0] SU[3:0]
Type RW RW RW RW RW RW RW RW

Bit Name Function


31 MSK4 Alarm A date mask
0: Alarm A set if the date/day match
1: Date/day don’t care in Alarm A comparison
30 WDSEL Week day selection
0: DU[3:0] represents the date units
1: DU[3:0] represents the week day. DT[1:0] is don’t care.
29:28 DT[1:0] Date tens in BCD format.
27:24 DU[3:0] Date units or day in BCD format.
23 MSK3 Alarm A hours mask

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0: Alarm A set if the hours match


1: Hours don’t care in Alarm A comparison
22 PM AM/PM notation
0: AM or 24-hour format
1: PM
21:20 HT[1:0] Hour tens in BCD format.
19:16 HU[3:0] Hour units in BCD format.
15 MSK2 Alarm A minutes mask
0: Alarm A set if the minutes match
1: Minutes don’t care in Alarm A comparison
14:12 MNT[2:0] Minute tens in BCD format.
11:8 MNU[3:0] Minute units in BCD format.
7 MSK1 Alarm A seconds mask
0: Alarm A set if the seconds match
1: Seconds don’t care in Alarm A comparison
6:4 ST[2:0] Second tens in BCD format.
3:0 SU[2:0] Second units in BCD format.

24.6.7. RTC_WPR

Address offset: 0x24


Reset value0x0000 0000

Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0


31:24 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
7:0 KEY[7:0]
Type WO WO WO WO WO WO WO WO

Bit Name Function


31:8 NA Reserved
7:0 KEY[7:0] Write protection key
This byte is written by software.
Reading this byte always returns 0x00.
Refer to “RTC register write protection” a description of how to unlock RTC
register write protection

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Fremont Micro Devices FT32F0xxx8 RM

24.6.8. RTC_SSR

Address offset; 0x28


RTC ___domain reset value: 0x0000 0000
System reset: 0x0000 0000 when BYPSHAD = 0. Not affected when BYPSHAD = 1.

Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0


31:24 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 SS[15:8]
Type RO RO RO RO RO RO RO RO
7:0 SS[7:0]
Type RO RO RO RO RO RO RO RO

Bit Name Function


31:16 NA Reserved
15:0 SS[15:0] Sub second value
SS[15:0] is the value in the synchronous prescaler counter. The fraction of a
second is given by the formula below:
Second fraction = (PREDIV_S – SS) / (PREDIV_S + 1)
Note: SS can be larger than PREDIV_S only after a shift operation. In that
case, the correct time/date is one second less than as indicated by
RTC_TR/RTC_DR.

24.6.9. RTC_SHIFTR

This register is write protected. The write access procedure is described in “RTC register write protection”
Address offset: 0x2C
RTC ___domain reset value: 0x0000 0000
System reset: not affected

Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0


31:24 ADD1S —
Type WO RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 — SUBFS[14:8]
Type RO-0 WO WO WO WO WO WO WO
7:0 SUBFS[7:0]
Type WO WO WO WO WO WO WO WO

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Bit Name Function


31 ADD1S Add one second
0: No effect
1: Add one second to the clock/calendar
This bit is write only and is always read as zero. Writing to this bit has no
effect when a shift operation is pending (when SHPF=1, in RTC_ISR).
This function is intended to be used with SUBFS (see description below) in
order to effectively add a fraction of a second to the clock in an atomic
operation.
30:15 NA Reserved
14:0 SUBFS[14:0] Subtract a fraction of a second
These bits are write only and is always read as zero. Writing to this bit has
no effect when a shift operation is pending (when SHPF=1, in RTC_ISR).
The value which is written to SUBFS is added to the synchronous prescaler
counter. Since this counter counts down, this operation effectively subtracts
from (delays) the clock by:
Delay (seconds) = SUBFS / (PREDIV_S + 1)
A fraction of a second can effectively be added to the clock (advancing the
clock) when the ADD1S function is used in conjunction with SUBFS,
effectively advancing the clock by:
Advance (seconds) = (1 – (SUBFS / (PREDIV_S + 1)))
Note: Writing to SUBFS causes RSF to be cleared. Software can then wait
until RSF=1 to be sure that the shadow registers have been updated with the
shifted time.

24.6.10. RTC_TSTR

The content of this register is valid only when TSF is set to 1 in RTC_ISR. It is cleared when TSF bit is reset.
Address offset: 0x30
RTC ___domain reset value: 0x0000 0000
System reset: not affected

Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0


31:24 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 — PM HT[1:0] HU[3:0]
Type RO-0 RO RO RO RO RO RO RO
15:8 — MNT[2:0] MNU[3:0]
Type RO-0 RO RO RO RO RO RO RO
7:0 — ST[2:0] SU[3:0]
Type RO-0 RO RO RO RO RO RO RO

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Bit Name Function


31:23 NA Reserved
22 PM AM/PM notation
0: AM or 24-hour format
1: PM
21:20 HT[1:0] Hour tens in BCD format
19:16 HU[3:0] Hour units in BCD format.
15 NA Reserved
14:12 MNT[2:0] Minute tens in BCD format.
11:8 MNU[3:0] Minute units in BCD format.
7 NA Reserved
6:4 ST[2:0] Second tens in BCD format.
3:0 SU[3:0] Second units in BCD format

24.6.11. RTC_TSDR

The content of this register is valid only when TSF is set to 1 in RTC_ISR. It is cleared when TSF bit is reset.
Address offset: 0x34
RTC ___domain reset value: 0x0000 0000
System reset: not affected

Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0


31:24 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 WDU[2:0] MT MU[3:0]
Type RO RO RO RO RO RO RO RO
7:0 — DT[1:0] DU[3:0]
Type RO-0 RO-0 RO RO RO RO RO RO

Bit Name Function


31:16 NA Reserved
15:13 WDU[2:0] Week day units
12 MT Month tens in BCD format
11:8 MU[3:0] Month units in BCD format
7:6 NA Reserved
5:4 DT[1:0] Date tens in BCD format
3:0 DU[3:0] Date units in BCD format

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Fremont Micro Devices FT32F0xxx8 RM

24.6.12. RTC_TSSSR

The content of this register is valid only when RTC_ISR/TSF is set. It is cleared when the RTC_ISR/TSF bit
is reset.
Address offset: 0x38
RTC ___domain reset value: 0x0000 0000
System reset: not affected

Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0


31:24 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 SS[15:8]
Type RO RO RO RO RO RO RO RO
7:0 SS[7:0]
Type RO RO RO RO RO RO RO RO

Bit Name Function


31:16 NA Reserved
15:0 SS[15:0] Sub second value
SS[15:0] is the value of the synchronous prescaler counter when the
timestamp event occurred.

24.6.13. RTC_CALR

This register is write protected. The write access procedure is described in “RTC register write protection”
Address offset: 0x3C
RTC ___domain reset value: 0x0000 0000
System reset: not affected

Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0


31:24 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 CALP CALW8 CALW16 — CALM[8]
Type RW RW RW RO-0 RO-0 RO-0 RO-0 RW
7:0 CALM[7:0]
Type RW RW RW RW RW RW RW RW

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Fremont Micro Devices FT32F0xxx8 RM

Bit Name Function


31:16 NA Reserved
15 CALP Increase frequency of RTC by 488.5 ppm
0: No RTCCLK pulses are added.
1: One RTCCLK pulse is effectively inserted every 2 11 pulses (frequency
increased by 488.5 ppm).
This feature is intended to be used in conjunction with CALM, which lowers
the frequency of the calendar with a fine resolution. If the input frequency is
32768 Hz, the number of RTCCLK pulses added during a 32-second window
is calculated as follows: (512 * CALP) – CALM.
Refer to section 24.3.11: RTC smooth digital calibration
14 CALW8 Use an 8-second calibration cycle period
When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected.
Note: CALM[1:0] are stuck at “00” when CALW8=’1’. Refer to section
24.3.11: RTC smooth digital calibration
13 CALW16 Use a 16-second calibration cycle period
When CALW16 is set to ‘1’, the 16-second calibration cycle period is
selected.This bit must not be set to ‘1’ if CALW8=1.
Note: CALM[0] is stuck at ‘0’ when CALW16=’1’. Refer to section 24.3.11:
RTC smooth digital calibration
12:9 NA Reserved
8:0 CALM[8:0] Calibration minus
The frequency of the calendar is reduced by masking CALM out of 2 20
RTCCLK pulses (32 seconds if the input frequency is 32768 Hz). This
decreases the frequency of the calendar with a resolution of 0.9537 ppm.
To increase the frequency of the calendar, this feature should be used in
conjunction with CALP. See section 24.3.11 RTC smooth digital calibration

24.6.14. RTC_TAFCR

Address offset: 0x40


RTC ___domain reset value: 0x0000 0000
System reset: not affected

Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0


31:24 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 PC15MODE PC15VALUE PC14MODE PC14VALUE PC13MODE PC13VALUE —
Type RW RW RW RW RW RW RO-0 RO-0
15:8 TAMPPUDIS TAMPPRCH[1:0] TAMPFLT[1:0] TAMPFREQ[2:0]
Type RW RW RW RW RW RW RW RW
7:0 TAMPTS — TAMP2TRG TAMP2E TAMPIE TAMP1TRG TAMP1E
Type RW RO-0 RO-0 RW RW RW RW RW

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Fremont Micro Devices FT32F0xxx8 RM

Bit Name Function


31:24 NA Reserved
23 PC15MODE PC15 mode
0: PC15 is controlled by the GPIO configuration registers. Consequently
PC15 is floating in Standby mode.
1: PC15 is forced to push-pull output if LSE is disabled.
22 PC15VALUE PC15 value
If the LSE is disabled and PC15MODE = 1, PC15VALUE configures the
PC15 output data.
21 PC14MODE PC14 mode
0: PC14 is controlled by the GPIO configuration registers. Consequently
PC14 is floating in Standby mode.
1: PC14 is forced to push-pull output if LSE is disabled.
20 PC14VALUE PC14 value
If the LSE is disabled and PC14MODE = 1, PC14VALUE configures the
PC14 output data.
19 PC13MODE PC13 mode
0: PC13 is controlled by the GPIO configuration registers. Consequently
PC13 is floating in Standby mode.
1: PC13 is forced to push-pull output if all RTC alternate functions are
disabled.
18 PC13VALUE RTC_ALARM output type/PC13 value
If PC13 is used to output RTC_ALARM, PC13VALUE configures the output
configuration:
0: RTC_ALARM is an open-drain output
1: RTC_ALARM is a push-pull output
If all RTC alternate functions are disabled and PC13MODE = 1,
PC13VALUE configures the PC13 output data.
17:16 NA Reserved
15 TAMPPUDIS RTC_TAMPx pull-up disable
This bit determines if each of the RTC_TAMPx pins are pre-charged before
each sample.
0: Precharge RTC_TAMPx pins before sampling (enable internal pull-up)
1: Disable precharge of RTC_TAMPx pins.
14:13 TAMPPRCH[1:0 RTC_TAMPx precharge duration
] These bit determines the duration of time during which the pull-up/is
activated before each sample. TAMPPRCH is valid for each of the
RTC_TAMPx inputs.
0x0: 1 RTCCLK cycle
0x1: 2 RTCCLK cycles
0x2: 4 RTCCLK cycles
0x3: 8 RTCCLK cycles
12:11 TAMPFLT[1:0] RTC_TAMPx filter count

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Fremont Micro Devices FT32F0xxx8 RM

These bits determines the number of consecutive samples at the specified


level (TAMP*TRG) needed to activate a Tamper event. TAMPFLT is valid for
each of the RTC_TAMPx inputs.
0x0: Tamper event is activated on edge of RTC_TAMPx input transitions to
the active level (no internal pull-up on RTC_TAMPx input).
0x1: Tamper event is activated after 2 consecutive samples at the active
level.
0x2: Tamper event is activated after 4 consecutive samples at the active
level.
0x3: Tamper event is activated after 8 consecutive samples at the active
level.
10:8 TAMPFREQ[2:0] Tamper sampling frequency
Determines the frequency at which each of the RTC_TAMPx inputs are
sampled.
0x0:RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz)
0x1:RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz)
0x2:RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz)
0x3:RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz)
0x4:RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz)
0x5:RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz)
0x6:RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz)
0x7:RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz)
7 TAMPTS Activate timestamp on tamper detection event
0: Tamper detection event does not cause a timestamp to be saved
1: Save timestamp on tamper detection event
6:5 NA Reserved
4 TAMP2TRG Active level for RTC_TAMP2 input
if TAMPFLT != 00:
0: RTC_TAMP2 input staying low triggers a tamper detection event.
1: RTC_TAMP2 input staying high triggers a tamper detection event.
If TAMPFLT = 00:
0: RTC_TAMP2 input rising edge triggers a tamper detection event.
1: RTC_TAMP2 input falling edge triggers a tamper detection event.
3 TAMP2E RTC_TAMP2 input detection enable
0: RTC_TAMP2 detection disabled
1: RTC_TAMP2 detection enabled
2 TAMPIE Tamper interrupt enable
0: Tamper interrupt disabled
1: Tamper interrupt enabled.
1 TAMP1TRG Active level for RTC_TAMP1 input
If TAMPFLT != 00
0: RTC_TAMP1 input staying low triggers a tamper detection event.
1: RTC_TAMP1 input staying high triggers a tamper detection event.

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Fremont Micro Devices FT32F0xxx8 RM

If TAMPFLT = 00:
0: RTC_TAMP1 input rising edge triggers a tamper detection event.
1: RTC_TAMP1 input falling edge triggers a tamper detection event.
0 TAMP1E RTC_TAMP1 input detection enable
0: RTC_TAMP1 detection disabled
1: RTC_TAMP1 detection enabled
Note: When TAMPFLT = 0, TAMP1E must be reset when TAMP1TRG is changed to avoid spuriously setting
TAMP1F.

24.6.15. RTC_ALRMASSR

This register can be written only when ALRAE is reset in RTC_CR register, or in initialization mode.
This register is write protected. The write access procedure is described in “RTC register write protection”
Address offset: 0x44
RTC ___domain reset value: 0x0000 0000
System reset: not affected

Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0


31:24 — MASKSS[3:0]
Type RO-0 RO-0 RO-0 RO-0 RW RW RW RW
23:16 —
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 — SS[14:8]
Type RO-0 RW RW RW RW RW RW RW
7:0 SS[7:0]
Type RW RW RW RW RW RW RW RW

Bit Name Function


31:28 NA Reserved
27:24 MASKSS[3:0] Mask the most-significant bits starting at this bit
0: No comparison on sub seconds for Alarm A. The alarm is set when the
seconds unit is incremented (assuming that the rest of the fields match).
1: SS[14:1] are don’t care in Alarm A comparison. Only SS[0] is compared.
2: SS[14:2] are don’t care in Alarm A comparison. Only SS[1:0] are
compared.
3: SS[14:3] are don’t care in Alarm A comparison. Only SS[2:0] are
compared.
...
12: SS[14:12] are don’t care in Alarm A comparison. SS[11:0] are compared.
13: SS[14:13] are don’t care in Alarm A comparison. SS[12:0] are compared.
14: SS[14] is don’t care in Alarm A comparison. SS[13:0] are compared.
15: All 15 SS bits are compared and must match to activate alarm.

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Fremont Micro Devices FT32F0xxx8 RM

The overflow bits of the synchronous counter (bits 15) is never compared.
This bit can be different from 0 only after a shift operation.
23:15 NA Reserved
14:0 SS[14:0] Sub seconds value
This value is compared with the contents of the synchronous prescaler
counter to determine if Alarm A is to be activated. Only bits 0 up MASKSS-1
are compared.

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25. Inter-integrated circuit (I2C) interface

25.1. main features

 Slave and master modes


 Multimaster capability
 Standard-mode (up to 100 kHz)
 Fast-mode (up to 400 kHz)
 Fast-mode Plus (up to 1 MHz)
 7-bit and 10-bit addressing mode
 Multiple 7-bit slave addresses (2 addresses, 1 with configurable mask)
 General call
 Programmable setup and hold times
 Optional clock stretching
 Software reset
 Single data 491ffecti with DMA capability
 Programmable analog and digital noise filters
 SMBus specification rev 2.0 compatibility
—Hardware PEC generation and verification
—Command and data ACK control
—Address resolution protocol (ARP) support
—Host and Device support
—SMBus alert
—Timeouts and idle condition detection
—PMBus rev 1.1 standard compatibility
—Support multi-clock ___domain, I2C clock is independent from PCLK

25.2. functional description

In addition to receiving and transmitting data, this interface converts it from serial to parallel format and vice
versa. The interrupts are enabled or disabled by software. The interface is connected to the I2C bus by a
data pin (SDA) and by a clock pin (SCL). It can be connected with a standard (up to 100 kHz), Fast-mode
(up to 400 kHz) or Fast-mode Plus (up to 1 MHz) I2C bus.
This interface can also be connected to a SMBus with the data pin (SDA) and clock pin (SCL). If SMBus
feature is supported: the additional optional SMBus Alert pin (SMBA) is also available.

25.2.1. I2C implementation

This manual describes the full set of features implemented in I2C1. I2C2 supports a smaller set of features,
but is otherwise identical to I2C1. The differences are listed below.

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Table 25-1 I2C implementation


features I2C1 I2C2
7-bit addressing mode √ √
10-bit addressing mode √ √
Standard mode √ √
Fast mode √ √
Multi-clock ___domain √ —
SMBus √ —
20 mA output drive for Fm+ mode √ —

25.2.2. block diagram

APB
APB bus
bus

PCLK Register
Register

SMBus
SMBus Alert
Alert control
control &
& status
status I2C_SMBA

Clock
Clock generation
generation Digital
Digital Analog
Analog
noise
noise noise
noise
filter
filter filter
filter GPIO
GPIO I2C_SCL
Clock
Clock stretching
stretching

Timeout
Timeout

Clock control

I2C1SW
Data control

SYSCLK Digital
Digital Analog
Analog
Shift
Shift register
register noise noise
0 noise noise
PCLK filter
filter filter
filter GPIO
GPIO I2C_SDA
1
HSI
PEC
PEC generation/check
generation/check

Figure 25-1 I2Cblock diagram


The I2C is clocked by an independent clock source which allows to the I2C to operate independently from
the PCLK frequency.
This independent clock source can be selected for either of the following two clock sources:
HSI: high speed internal oscillator
SYSCLK: system clock

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I2C I/Os support 20 mA output current drive for Fast-mode Plus operation. This is enabled by setting the
driving capability control bits for SCL and SDA, refer to SYSCFG_CFGR1.

25.2.3. clock requirements

The I2C kernel is clocked by I2CCLK.

The I2CCLK period TI2CCLK must respect the following conditions:


TI2CCLK<(TLOW-Tfilters)/4 and TI2CCLK<THIGH
with:
TLOW:SCL low time and THIGH:SCL high time
Tfilters: when enabled, sum of the delays brought by the analog filter and by the digital filter.
Analog filter delay is maximum 200ns. Digital filter delay isDNF * T I2CCLK.

The PCLK clock period TPCLK must respect the following condition:
TPCLK<4/3TSCL
with TSCL:SCL period
Caution: When the I2C kernel is clocked by PCLK. PCLK must respect the conditions for T I2CCLK.

25.2.4. Mode selection

The interface can operate in one of the four following modes:


 Slave transmitter
 Slave receiver
 Master transmitter
 Master receiver
By default, it operates in slave mode. The interface automatically switches from slave to
master when it generates a START condition, and from master to slave if an arbitration loss or a STOP
generation occurs, allowing multimaster capability.

Communication flow
In Master mode, the I2C interface initiates a data transfer and generates the clock signal. A
serial data transfer always begins with a START condition and ends with a STOP condition. Both START
and STOP conditions are generated in master mode by software.

In Slave mode, the interface is capable of recognizing its own addresses (7 or 10-bit), and
the General Call address. The General Call address detection can be enabled or disabled by software. The
reserved SMBus addresses can also be enabled by software.

Data and addresses are transferred as 8-bit bytes, MSB first. The first byte(s) following the START condition
contain the address (one in 7-bit mode, two in 10-bit mode). The address is always transmitted in Master

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mode.

th
A9 clock pulse follows the 8 clock cycles of a byte transfer, during which the receiver must send an
acknowledge bit (ACK) to the transmitter. Refer to the following Figure 25-2 I2C bus protocol.

SDA MSB ACK

SCL 1 8 9
2
START
STOP

Figure 25-2 I2C bus protocol


Acknowledge can be enabled or disabled by software. The I2C interface addresses (7bit, 10bit, and General
Call address)can be selected by software.

25.2.5. I2C initialization

Enabling and disabling the peripheral


The I2C peripheral clock must be configured and enabled in the clock controller. Then the I2C can be
enabled by setting the PE bit in the I2C_CR1 register. When the I2C is disabled (PE=0), the I2C performs a
software reset. I2C lines(SCL and SDA)are released. Internal states machines are reset and communication
control bits, as well as status bits come back to their reset value.

Noise filters
Before you enable the I2C peripheral by setting the PE bit in I2C_CR1 register, you must configure the noise
filters, if needed. By default, an analog noise filter is present on the SDA and SCL inputs. This analog filter is
compliant with the I2C specification which requires the suppression of spikes with a pulse width up to 50 ns
in Fast-mode and Fast-mode Plus. You can disable this analog filter by setting the ANFOFF bit, and/or
select a digital filter by configuring the DNF[3:0] bit in the I2C_CR1 register.

When the digital filter is enabled, the level of the SCL or the SDA line is internally changed only if it remains
stable for more than DNF*I2CCLK periods. This allows to suppress spikes with a programmable length of 1
to 15 I2CCLK periods.
Table 25-2 Comparison of analog vs. digital filters
Analog filter Digital filter
Pulse width of suppressed spikes Programmable length from 1 to 15
I2C peripheral clocks
Benefits Available in Stop mode Programmable length:
Drawbacks Variation vs. temperature, voltage, —
process
Caution: Changing the filter configuration is not allowed when the I2C is enabled.

I2C timings

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The timings must be configured in order to guarantee a correct data hold and setup time, used in master and
slave modes. This is done by programming the PRESC[3:0], SCLDEL[3:0] and SDADEL[3:0] bits in the
I2C_TIMINGR register.

DATA HOLD TIME

synchronization time
SDADEL

SCL

SDA

data hold time

DATA SETUP TIME

SCLDEL
SCL

SDA

data setup
time

Figure 25-3 Setup and hold timings


● When the SCL falling edge is internally detected, a delay is inserted before sendingSDA output. This
delay is TSDADEL=SDADEL*TPRESC where TPRESC=(PRESC+1)*TI2C_CLK .
TSDADEL impacts the hold time.
The total SDA output delay is: T sync1+[SDADEL*(PRESC+1)*TI2C_CLK]
Tsync1duration depends on these parameters:
－SCL falling slope
－When enabled, input delay brought by the analog filter: at least 50ns, maximum is 200ns
－When enabled, input delay brought by the digital filterTDNF=DNF*TI2C_CLK
－Delay due to SCL synchronization to I2CCLK clock (2 to 3 I2CCLK periods)
In order to bridge the undefined region of the SCL falling edge, you must program SDADEL
in such a way that:
{Tfmax+THD,DATA(min)-50ns-[(DNF+3)*TI2C_CLK]}/{(PRESC+1)*TI2C_CLK}<=SDADEL
SDADEL<={THD,DATA(max)-200ns-[(DNF+4)*TI2C_CLK]}/{(PRESC+1)*TI2C_CLK}
Note: -50ns/-200nsare part of the equation only when the analog filter is enabled.
● After sending SDA output, SCL line is kept at low level during the setup time. This setup time is
TSCLDEL=(SCLDEL+1)*TPRESC TPRESC=(PRESC+1)*TI2C_CLK

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TSCLDEL impacts the setup time


In order to bridge the undefined region of the SDA transition (rising edge usually worst case), you must
program SCLDEL in such a way that:
{[TR(max)+TSU, DAT(min)]/[(PRESC+1)]*TI2C_CLK}}-1<=SCLDEL
Table 25-3 I2C-SMBUS specification data setup and hold times
Standard-mode Fast-mode Fast-modePlus SMBUS
Symbol Parameter Unit
Min Max Min Max Min Max Min Max
Data hold
THD:DAT 0 - 0 - 0 - 0.3 - μs
time
Data valid
TVD:DAT - 3.45 - 0.9 - 0.45 - - μs
time
Data setup
TSU:DAT 250 - 100 - 50 - 250 - ns
time
Rise time of
TR both SDA and - 1000 - 300 - 120 - 1000 ns
SCL signals
Fall time of
both SDA and
TF - 300 - 300 - 120 - 300 ns
SCL
signals
Additionally, in master mode, the SCL clock high and low levels must be configured by programming the
PRESC[3:0], SCLH[7:0] and SCLL[7:0] bits in the I2C_TIMINGR register.
● When the SCL falling edge is internally detected, a delay is inserted before releasing the SCL output.
This delay is TSCLL=(SCLL+1)*TPRESC where TPRESC=(PRESC+1)*TI2C_CLK.TSCLL impacts the SCL low time
TLOW.
● When the SCL rising edge is internally detected, a delay is inserted before forcing the SCL output to low
level. This delay is TSCLH=(SCLH+1)*TPRESC whereTPRESC=(PRESC+1)*TI2C_CLK.TSCLH impacts the SCL
high time THIGH.

Caution: Changing the timing configuration is not allowed when the I2C is enabled.

I2C configuration
The I2C slave NOSTRETCH mode must also be configured before enabling the peripheral.

Changing the NOSTRETCH configuration is not allowed when the I2C is enabled

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Initial settings

Clear PE bit

Configure
PRESC,SDADEL,SCLDEL,SCLH,
SCLL

Configure NOSTRETCH bit

Set PE bit

End

Figure 25-4 I2C initialization flowchart

25.2.6. Software reset

A software reset can be performed by clearing the PE bit in the I2C_CR1 register. In that case I2C lines SCL
and SDA are released. Internal states machines are reset and communication control bits, as well as status
bits come back to their reset value. The configuration registers are not impacted.
Here is the list of impacted register bits:
1. I2Cx_CR2 register: START,STOP,NACK
2. I2Cx_ISR register: BSY,TXE,TXIS,RXNE,ADDR,NACKF,TCR,TC,STOPF,BERR,ARLO,OVR

and in addition when the SMBus feature is supported:


1. I2Cx_CR2 register: PECBYTE
2. I2Cx_ISR register: PECERR,TIMEOUT,ALERT

PE must be kept low during at least 3 APB clock cycles in order to perform the software reset. This is
ensured by writing the following software sequence: - Write PE=0 – Check PE=0 – Write PE=1.

25.2.7. Data transfer

The data transfer is managed through transmit and receive data registers and a shift register.
Reception
th
The SDA input fills the shift register. After the 8 SCL pulse (when the complete data byte is received), the
shift register is copied into I2C_RXDR register if it is empty (RXNE=0). If RXNE=1, meaning that the
previous received data byte has not yet been read, the SCL line is stretched low until I2C_RXDR is read.
th th
The stretch is inserted between the 8 and 9 SCL pulse (before the Acknowledge pulse).

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ACK ACK
pulse pulse
SCL SCLstretch

Shift
xx data1 xx data2
register

RXNE
read data0
read data1

RXDR data0 data1 data2

Figure 25-5 Data reception

Transmission
th
If the I2C_TXDR register is not empty (TXE=0), its content is copied into the shift register after the 9 SCL
pulse (the Acknowledge pulse). Then the shift register content is shifted out on SDA line. If TXE=1, meaning
that no data is written yet in I2C_TXDR, SCL line is stretched low until I2C_TXDR is written. The stretch is
th
done after the 9 SCL pulse.

ACK ACK
pulse pulse
SCL SCLstretch

Shift
xx xx xx
d1

d2

register

TXE
write data1
write data2

TXDR data0 data1 data2

Figure 25-6 Data transmission


Hardware transfer management
The I2C has a byte counter embedded in hardware in order to manage byte transfer and to
close the communication in various modes such as:
－NACK, STOP and ReSTART generation in master mode
－ACK control in slave receiver mode
－PEC generation/checking when SMBus feature is supported

The byte counter is always used in master mode. By default it is disabled in slave mode, but it can be
enabled by software by setting the SBC (Slave Byte Control) bit in the I2Cx_CR2 register.

The number of bytes to be transferred is programmed in the NBYTES[7:0] bit field in the I2C_CR2 register. If

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the number of bytes to be transferred (NBYTES) is greater than 255, or if a receiver wants to control the
acknowledge value of a received data byte, the reload mode must be selected by setting the RELOAD bit in
the I2C_CR2 register. In this mode, TCR flag is set when the number of bytes programmed in NBYTES has
been transferred, and an interrupt is generated if TCIE is set. SCL is stretched as long as TCR flag is set.
TCR is cleared by software when NBYTES is written to a non-zero value.
When the NBYTES counter is reloaded with the last number of bytes, RELOAD bit must be cleared.

When RELOAD=0 in master mode, the counter can be used in 2 modes:


● Automatic end mode(AUTOEND=1 in the I2Cx_CR2 register). In this mode, the master automatically
sends a STOP condition once the number of bytes programmed in the NBYTES[7:0] bit field has been
transferred.
● Software end mode(AUTOEND=0 in the I2Cx_CR2 register). In this mode, software action is expected
once the number of bytes programmed in the NBYTES[7:0] bit field has been transferred; the TC flag is
set and an interrupt is generated if the TCIE bit is set. The SCL signal is stretched as long as the TC flag
is set. The TC flag is cleared by software when the START or STOP bit is set in the I2C_CR2 register.
This mode must be used when the master wants to send a RESTART condition.

Caution: The AUTOEND bit has no effect when the RELOAD bit is set.
Table 25-4 I2C configuration table
Function SBC bit RELOAD bit AUTOEND bit
Master Tx/Rx NBYTES + STOP x 0 1
Master Tx/Rx + NBYTES + RESTART x 0 0
Slave Tx/Rx+ ACK 0 x x
Slave Rx + ACK 1 1 x

25.2.8. I2C slave mode

I2C slave initialization


In order to work in slave mode, you must enable at least one slave address. Two registers I2Cx_OAR1 and
I2Cx_OAR2 are available in order to program the slave own addresses OA1 and OA2.
● OA1 can be configured either in 7-bit mode (by default) or in 10-bit addressing mode by setting the
OA1MODE bit in the I2Cx_OAR1 register. OA1 is enabled by setting the OA1EN bit in the I2Cx_OAR1
register.
nd
● If additional slave addresses are required, you can configure the 2 slave address OA2. Up to 7 OA2
LSB can be masked by configuring the OA2MSK[2:0] bits in the I2Cx_OAR2 register. Therefore for
OA2MSK configured from 1 to 6, only OA2[7:2], OA2[7:3], OA2[7:4], OA2[7:5], OA2[7:6] or OA2[7] are
compared with the received address. As soon as OA2MSK is not equal to 0, the address comparator for
OA2 excludes the I2C reserved addresses (0000 XXX and 1111 XXX), which are not acknowledged. If
OA2MSK=7, all received 7-bit addresses are acknowledged (except reserved addresses). OA2 is
always a 7-bit address, but not a 10-bit address. These reserved addresses can be acknowledged if
they are enabled by the specific enable bit, if they are programmed in the I2Cx_OAR1 or I2Cx_OAR2
register with OA2MSK=0. OA2 is enabled by setting the OA2EN bit in the I2Cx_OAR2 register.
● The General Call address is enabled by setting the GCEN bit in the I2Cx_CR1 register.

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When the I2C is selected by one of its enabled addresses, the ADDR interrupt status flag is set, and an
interrupt is generated if the ADDRIE bit is set.

By default, the slave uses its clock stretching capability, which means that it stretches the SCL signal at low
level when needed, in order to perform software actions. If the master does not support clock stretching, the
I2C must be configured with NOSTRETCH=1 in the I2Cx_CR1 register.

After receiving an ADDR interrupt, if several addresses are enabled you must read the ADDCODE[6:0] bits
in the I2Cx_ISR register in order to check which address matched. DIR flag must also be checked in order to
know the transfer direction.

Slave clock stretching(NOSTRETCH=0)


In default mode, the I2C slave stretches the SCL clock in the following situations:
● When the ADDR flag is set: the received address matches with one of the enabled slave addresses.
This stretch is released when the ADDR flag is cleared by software setting the ADDRCF bit.
● In transmission, if the previous data transmission is completed and no new data is written in I2Cx_TXDR
register, or if the first data byte is not written when the ADDR flag is cleared (TXE=1). This stretch is
released when the data is written to the I2Cx_TXDR register.
● In reception when the I2Cx_RXDR register is not read yet and a new data reception is completed. This
stretch is released when I2Cx_RXDR is read.
● When TCR = 1 in Slave Byte Control mode, reload mode (SBC=1 and RELOAD=1), meaning that the
last data byte has been transferred. This stretch is released when then TCR is cleared by writing a
non-zero value in the NBYTES[7:0] field.

Slave without clock stretching (NOSTRETCH = 1)


When NOSTRETCH = 1 in the I2Cx_CR1 register, the I2C slave does not stretch the SCL signal.
● The SCL clock is not stretched while the ADDR flag is set.
● In transmission, the data must be written in the I2Cx_TXDR register before the first SCL pulse
corresponding to its transfer occurs. If not, an underrun occurs, the OVR flag is set in the I2Cx_ISR
register and an interrupt is generated if the ERRIE bit is set in the I2Cx_CR1 register. The OVR flag is
also set when the first data transmission starts and the STOPF bit is still set (has not been cleared).
Therefore, if you clear the STOPF flag of the previous transfer only after writing the first data to be
transmitted in the next transfer, you ensure that the OVR status is provided, even for the first data to be
transmitted.
th
● In reception, the data must be read from the I2Cx_RXDR register before the 9 SCL pulse (ACK pulse)
of the next data byte occurs. If not an overrun occurs, the OVR flag is set in the I2Cx_ISR register and
an interrupt is generated if the ERRIE bit is set in the I2Cx_CR1 register.

Slave Byte Control Mode


In order to allow byte ACK control in slave reception mode, Slave Byte Control mode must be enabled by
setting the SBC bit in the I2Cx_CR1 register. This is required to be compliant with SMBus standards.

Reload mode must be selected in order to allow byte ACK control in slave reception mode (RELOAD=1). To

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get control of each byte, NBYTES must be initialized to 0x1 in the ADDR interrupt subroutine, and reloaded
to 0x1 after each received byte. When the byte is received, the TCR bit is set, stretching the SCL signal low
th th
between the 8 and 9 SCL pulses. You can read the data from the I2Cx_RXDR register, and then decide to
acknowledge it or not by configuring the ACK bit in the I2Cx_CR2 register. The SCL stretch is released by
programming NBYTES to a non-zero value: the acknowledge or not-acknowledge is sent and next byte can
be received.

NBYTES can be loaded with a value greater than 0x1, and in this case, the reception flow is continuous
during NBYTES data reception.

Note1: The SBC bit must be configured when the I2C is disabled, or when the slave is not addressed, or
when ADDR=1.
Note2. The RELOAD bit value can be changed when ADDR=1, or when TCR=1.
Note3. Slave Byte Control mode is not compatible with NOSTRETCH mode. Setting SBC when
NOSTRETCH=1 is not allowed.

Slave initialization

Initial setting

Clear OA1EN，OA2EN

Configure OA1，OA1MODE，OA1EN，
OA2，OA2MSK，OA2EN，GCEN

Configure SBC

Enable interrupts and/or


DMA

End

Figure 25-7 Slave initialization flowchart

Slave transmitter
A transmit interrupt status (TXIS) is generated when the I2Cx_TXDR register becomes empty. An interrupt is
generated if the TXIE bit is set in the I2Cx_CR1 register.

The TXIS bit is cleared when the I2C_TXDR register is written with the next data byte to be transmitted.

When a NACK is received, the NACKF bit is set in the I2Cx_ISR register and an interrupt is generated if the

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NACKIE bit is set in the I2Cx_CR1 register. The slave automatically releases the SCL and SDA lines in order
to let the master perform a STOP or a RESTART condition. The TXIS bit is not set when a NACK is
received.

When a STOP is received and the STOPIE bit is set in the I2C_CR1 register, the STOPF flag is set in the
I2Cx_ISR register and an interrupt is generated. In most applications, the SBC bit is usually programmed to
‘0’. In this case, If TXE = 0 when the slave address is received (ADDR=1), you can choose either to send the
content of the I2Cx_TXDR register as the first data byte, or to flush the I2Cx_TXDR register by setting the
TXE bit in order to program a new data byte.

In Slave Byte Control mode (SBC=1), the number of bytes to be transmitted must be programmed in
NBYTES in the address match interrupt subroutine (ADDR=1). In this case, the number of TXIS events
during the transfer corresponds to the value programmed in NBYTES.

Caution: When NOSTRETCH=1, the SCL clock is not stretched while the ADDR flag is set, so you cannot
flush the I2Cx_TXDR register content in the ADDR subroutine, in order to program the first data byte. The
first data byte to be sent must be previously programmed in the I2Cx_TXDR register:
● This data can be the data written in the last TXIS event of the previous transmission message.
● If this data byte is not the one to be sent, the I2Cx_TXDR register can be flushed by setting the TXE bit
in order to program a new data byte. The STOPF bit must be cleared only after these actions, in order to
guarantee that they are executed before the first data transmission starts, following the address
acknowledge. If STOPF is still set when the first data transmission starts, an underrun error will be
generated (the OVR flag is set). If you need a TXIS event, (Transmit Interrupt or Transmit DMA request),
you must set the TXIS bit in addition to the TXE bit, in order to generate a TXIS event.

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Slave
transmission

Slave initialization

NO

ADDR=1？

YES SCL
read ADDCODE and DIR, stretched
set ADDRCF(optional set
TXE)

NO
TXIS=1？

YES

Write TXDATA register

Figure 25-8 Transfer sequence flowchart for I2C slave transmitter(NOSTRETCH=0)

Slave
transmission

Slave initialization

NO

NO STOPF=1？
TXIS=1？

YES
YES
Optional set TXE and
Write TXDATA register TXIS

Set STOPCF

Figure 25-9 Transfer sequence flowchart for I2C slave transmitter(NOSTRETCH=1)

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I2C slave transmitter 3 bytes with 1st data flushed (NOSTRETCH=0)

ADDR TXIS TXIS TXIS

S ADDR A DATA1 A DATA2 A DATA3 NA P

EV1 EV2 EV3 EV4 EV5

TXE

transmission
EV1：ADDR ISR, read ADDCODE，DIR，set ADDRCF
S reception
EV2：TXIS ISR, write DATA1

EV3：TXIS ISR, write DATA2 SCL stretch

EV4：TXIS ISR, write DATA3

EV5：TXIS ISR, write DATA4(not sent)

I2C slave transmitter 3 bytes without 1st data flushed (NOSTRETCH=0)

ADDR TXIS TXIS TXIS

S ADDR A DATA1 A DATA2 A DATA3 NA P

EV1 EV2 EV3 EV4

TXE

transmission
EV1：ADDR ISR, read ADDCODE，DIR， set ADDRCF
S reception
EV2：TXIS ISR, write DATA2
SCL stretch
EV3：TXIS ISR, ,write DATA3

EV3：TXIS ISR, write DATA4(not sent)

I2C slave transmitter 3 bytes（(NOSTRETCH=1)


TXIS TXIS STOP
TXIS
F

S ADDR A DATA1 A DATA2 A DATA3 NA P

EV2 EV3 EV4 EV5


EV1

TXE

EV1：write DATA1 transmission

EV2：TXIS ISR write DATA2


S reception
EV3：TXIS ISR, write DATA3

SCL stretch
EV4：TXIS ISR, write DATA4(not sent)

EV5：STOPF ISR, optional set TXE and TXIS, set STOPCF

Figure 25-10 Transfer bus diagrams for I2C slave transmitter


Slave receiver

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RXNE is set in I2Cx_ISR when the I2C_RXDR is full, and generates an interrupt if RXIE is set in I2Cx_CR1.
RXNE is cleared when I2Cx_RXDR is read.
When a STOP is received and STOPIE is set in I2Cx_CR1, STOPF is set in I2Cx_ISR and an interrupt is
generated.

Slave reception

Slave initialization

NO

ADDR=1？

YES SCL
Read ADDCODE and DIR, stretched
set ADDRCF(optional set
TXE)

NO
RXNE=1？

YES

Read RXDATA register

Figure 25-11 Transfer sequence flowchart for slave receiver(NOSTRETCH=0)

Slave reception

Slave initialization

NO

NO STOPF=1？
RXNE=1？

YES
YES
optional set TXE and TXIS
Read RXDATA register

Set STOPCF

Figure 25-12 Transfer sequence flowchart for slave receiver(NOSTRETCH=1)

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I2C slave receiver 3 bytes(NOSTRETCH=0)

ADDR RXNE RXNE RXNE

S ADDR A DATA1 A DATA2 A DATA3 A P

EV2 EV3 EV4


EV1

RXNE

transmission
EV1：ADDR ISR, read ADDCODE，DIR， set ADDRCF
S reception
EV2：RXNE ISR, read DATA1

EV3：RXNEISR, read DATA2 SCL stretch

EV4：RXNE ISR, read DATA3

I2C slave receiver 3 bytes（(NOSTRETCH=1)


RXNE RXNE RXNE

S ADDR A DATA1 A DATA2 A DATA3 A P

EV1 EV2 EV3 EV4

TXE

EV1：RXNE ISR, read DATA1 transmission

EV2：RXNE ISR, read DATA2


S reception

EV3：RXNE ISR, read DATA3


SCL stretch
EV4：STOPF ISR, set TXE and TXIS, set STOPCF

Figure 25-13 Transfer bus diagrams for I2C slave receiver

25.2.9. I2C master mode

I2C master initialization


Before enabling the peripheral, the I2C master clock must be configured by setting the SCLH and SCLL bits
in the I2C_TIMINGR register.

A clock synchronization mechanism is implemented in order to support multi-master environment and slave
clock stretching.

In order to allow clock synchronization:


● The low level of the clock is counted using the SCLL counter, starting from the SCL low level internal

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detection.
● The high level of the clock is counted using the SCLH counter, starting from the SCL high level internal
detection.

The I2C detects its own SCL low level after a T sync1 delay depending on the SCL falling edge, SCL input
noise filters (analog + digital) and SCL synchronization to the I2CxCLK clock. The I2C releases SCL to high
level once the SCLL counter reaches the value programmed in the SCLL[7:0] bits in the I2Cx_TIMINGR
register.

The I2C detects its own SCL high level after a T sync2 delay depending on the SCL rising edge, SCL input
noise filters (analog + digital) and SCL synchronization to I2CxCLK clock. The I2C ties SCL to low level once
the SCLH counter is reached reaches the value programmed in the SCLH[7:0] bits in the I2C_TIMINGR
register.

Consequently the master clock period is:


TSCL = Tsync1 + Tsync2 + { [(SCLH+1) + (SCLL+1)] x (PRESC+1) *TI2C_CLK }.
The duration of Tsync1 depends on these parameters:
－SCL falling slope
－When enabled, input delay induced by the analog filter.
－When enabled, input delay induced by the digital filter: DNF *T I2C_CLK
－Delay due to SCL synchronization with I2CCLK clock (2 to 3 I2CCLK periods)
The duration of Tsync2 depends on these parameters:
－SCL rising slope
－When enabled, input delay induced by the analog filter
－When enabled, input delay induced by the digital filter:DNF *T I2C_CLK
－Delay due to SCL synchronization with I2CCLK clock (2 to 3 I2CCLK periods)

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SCL high level SCL low level


SCL master clock generation detected SCLH detected SCLL
counter starts counter starts

Tsync2 Tsync1
SCLH

SCL

SCLL
SCL released SCL drive low

SCL master clock synchronization

SCL high level SCL low level


detected SCLH detected SCLL
counter starts counter starts

SCLH SCLH
SCLL SCLL

SCL released
SCL driven low by SCL driven low by
another device another device

Figure 25-14 Master clock generation


Caution: In order to be I2C or SMBus compliant, the master clock must respect the timings given below:
Table 25-5 I2C SMBUS specification clock timings
Standard-mode Fast-mode Fast-mode Plus SMBUS
Symbol Parameter Unit
Min Max Min Max Min Max Min Max
FSCL SCL clock - 100 - 400 - 1000 - 100 kHz
frequency
THD:STA START Hold time 4.0 - 0.6 - 0.26 - 4.0 - μs
TSU:STA RESTART Set-up 4.7 - 0.6 - 0.26 - 4.7 - μs
time
TSU:STO STOP Set-up time 4.0 - 0.6 - 0.26 - 4.0 - μs
TBUF Bus free time 4.7 - 1.3 - 0.5 - 4.7 - μs
between a STOP
and
STARTcondition
TLOW Low period of the 4.7 - 1.3 - 0.5 - 4.7 - μs
SCL clock
THIGH High period of the 4.0 - 0.6 - 0.26 - 4.0 50 μs
SCL clock
TR Rise time of both - 1000 - 300 - 120 - 1000 ns
SDA and SCL

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signals
TF Fall time of both - 300 - 300 - 120 - 300 ns
SDA and SCL
signals
SCLL is also used to generate the T BUF and TSU:STA timings.
SCLH is also used to generate the T HD:STA and TSU:STO timings.

Master communication initialization (address phase)


In order to initiate the communication, you must program the following parameters for the
addressed slave in the I2Cx_CR2 register:
● Addressing mode (7-bit or 10-bit): ADD10
● Slave address to be sent: SADD[9:0]
● Transfer direction: RD_WRN
● In case of 10-bit address read: HEAD10R bit. HEAD10R must be configure to indicate if the complete
address sequence must be sent, or only the header in case of a direction change.
● The number of bytes to be transferred: NBYTES[7:0]. If the number of bytes is equal to or greater than
255 bytes, NBYTES[7:0] must initially be filled with 0xFF.

You must then set the START bit in I2C_CR2 register. Changing all the above bits is not allowed when
START bit is set.

Then the master automatically sends the START condition followed by the slave address as soon as it
detects that the bus is free (BSY = 0) and after a delay of tBUF.

In case of an arbitration loss, the master automatically switches back to slave mode and can acknowledge
its own address if it is addressed as a slave.

Note: The START bit is reset by hardware when the slave address has been sent on the bus, whatever the
received acknowledge value. The START bit is also reset by hardware if an arbitration loss occurs. If the I2C
is addressed as a slave (ADDR=1) while the START bit is set, the I2C switches to slave mode and the
START bit is cleared when the ADDRCF bit is set.

Note:The same procedure is applied for a Repeated Start condition. In this case BSY=1.

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Master
initialization

Initial setting

Enable interrupts and/or DMA

End

Figure 25-15 Master initialization flowchart


Initialization of a master receiver addressing a 10-bit address slave
If the slave address is in 10-bit format, you can choose to send the complete read sequence by clearing the
HEAD10R bit in the I2C_CR2 register. In this case the master automatically sends the following complete
sequence after the START bit is set:
nd
(Re)Start + Slave address 10-bit header Write + Slave address 2 byte + REStart + Slave address 10-bit
header Read
11110x 11110x
x 0 1
x
Slave address R Slave address S Slave address R
S A A A DATA A
1st 7 bits W 2nd byte R 1st 7 bits W

DATA NA P

Figure 25-16 10-bit address read access with HEAD10R=0


● If the master addresses a 10-bit address slave, transmits data to this slave and then reads data from the
same slave, a master transmission flow must be done first. Then a repeated start is set with the 10 bit
slave address configured with HEAD10R=1. In this case the master sends this sequence: ReStart +
Slave address 10-bit header Read
11110x
x 0
Slave address R Slave address
S A A DATA A DATA A/NA
1st 7 bits W 2nd byte

11110x
1
x
Slave address R
S A DATA A DATA NA P
1st 7 bits W

Figure 25-17 10-bit address read access with HEAD10R=1


Master transmitter
th
In the case of a write transfer, the TXIS flag is set after each byte transmission, after the 9 SCL pulse when
an ACK is received.

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A TXIS event generates an interrupt if the TXIE bit is set in the I2Cx_CR1 register. The flag is cleared when
the I2Cx_TXDR register is written with the next data byte to be transmitted.
The number of TXIS events during the transfer corresponds to the value programmed in NBYTES[7:0]. If the
total number of data bytes to be sent is greater than 255, reload mode must be selected by setting the
RELOAD bit in the I2C_CR2 register. In this case, when NBYTES data have been transferred, the TCR flag
is set and the SCL line is stretched low until NBYTES[7:0] is written to a non-zero value.

The TXIS flag is not set when a NACK is received.


● When RELOAD=0 and NBYTES data have been transferred:
－In automatic end mode (AUTOEND=1), a STOP is automatically sent.
－In software end mode (AUTOEND=0), the TC flag is set and the SCL line is stretched low in order to
perform software actions: A RESTART condition can be requested by setting the START bit in the
I2Cx_CR2 register with the proper slave address configuration, and number of bytes to be transferred.
Setting the START bit clears the TC flag and the START condition is sent on the bus. A STOP condition
can be requested by setting the STOP bit in the I2Cx_CR2 register. Setting the STOP bit clears the TC
flag and the STOP condition is sent on the bus.
● If a NACK is received: the TXIS flag is not set, and a STOP condition is automatically sent after the
NACK reception. The NACKF flag is set in the I2C_ISR register, and an interrupt is generated if the
NACKIE bit is set.

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Master
transmission

Master initialization

NBYTES=N，AUTOEND=0(for
RESTART),AUTOEND=1(for STOP)

No
No
NACKF=1? TXIS=1?

Yes Yes

End Write TXDR

No
NBYTES
transmitted？

Yes
TC=1？

No

End Set START bit

Figure 25-18 Transfer sequence flowchart for I2C master transmitter for N≤255 bytes

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Master
transmission

Master initialization

NBYTES=0xFF，N=N-255，
RELOAD=1， set START

No
No
NACKF=1? TXIS=1?

Yes Yes

End Write TXDR

No
NBYTES
transmitted？

Yes

Yes
TC=1？

No

Set START bit

TCR=1？

IF
N<256;NBYTES=N;RELOAD=
0;AUTOEND=0 FOR
RESTART;
AUTOEND=1 FOR STOP
ELSE
NBYTES=0xff;N=N-255;
RELOAD=1

Figure 25-19 Transfer sequence flowchart for I2C master transmitter for N>255 bytes

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I2C master transmitter 2 bytes, automatic end mode

TXIS TXIS

S ADDR A DATA1 A DATA2 A P

INIT EV1 EV2

TXE

NBYTES
xx 2

INIT：program Slave address, NBYTES=2，AUTOEND=1 reception

EV1：TXIS ISR , write DATA1


S transmission
EV2：TXIS ISR, write DATA2
SCL stretch

I2C master transmitter 2 bytes, software end mode (RESTART)

TXIS TXIS TC

S ADDR A DATA1 A DATA2 A SR ADDR

INIT EV1 EV2 EV3

TXE

NBYTES

xx 2

INIT：program Slave address, NBYTES=2，AUTOEND=0 reception

EV1：TXIS ISR, Write DATA1


S transmission
EV2：TXIS ISR, Write DATA2
SCL stretch
EV3：TC ISR, program NBYTES, set START

Figure 25-20 Transfer bus diagrams for I2C master transmitter

Master receiver
th
In the case of a read transfer, the RXNE flag is set after each byte reception, after the 8 SCL pulse. An
RXNE event generates an interrupt if the RXIE bit is set in the I2Cx_CR1 register. The flag is cleared when
I2C_RXDR is read.

If the total number of data bytes to be received is greater than 255, reload mode must be selected by setting
the RELOAD bit in the I2Cx_CR2 register. In this case, when NBYTES[7:0] data have been transferred, the
TCR flag is set and the SCL line is stretched low until NBYTES[7:0] is written to a non-zero value.

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●When RELOAD=0 and NBYTES[7:0] data have been transferred:


－In automatic end mode (AUTOEND=1), a NACK and a STOP are automatically sent after the last
received byte.
－In software end mode (AUTOEND=0), a NACK is automatically sent after the last received byte, the
TC flag is set and the SCL line is stretched low in order to allow software actions: A RESTART condition
can be requested by setting the START bit in the I2Cx_CR2 register with the proper slave address
configuration, and number of bytes to be transferred. Setting the START bit clears the TC flag and the
START condition, followed by slave address, are sent on the bus. A STOP condition can be requested
by setting the STOP bit in the I2Cx_CR2 register. Setting the STOP bit clears the TC flag and the STOP
condition is sent on the bus.

Master reception

Master initialization

NBYTES=N，AUTOEND=0 （FOR
RESTART）;AUTOEND=1（FOR
STOP），configure slave address,
set START bit

No
RXNE=1？

Yes

Read RXDR

No
NBYTES
received？

Yes

Yes
TC=1？

set START bit


No

Master reception

Figure 25-21 Transfer sequence flowchart for I2C master receiver for N≤255 bytes

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Master reception

Master initialization

NBYTES=0xFF，N=N-255；
RELOAD=1，configure slave
address，set START bit

No
RXNE=1？

Yes

Read RXDR

No
NBYTES
received？

Yes

Yes
TC=1？

Set START bit No

No
TCR=1？

Yes

IF N<256
NBYTES=N;N=0;RELOAD=0;
AUTOEND=0 for RESTART;
AUTOEND=1 for STOP
ELSE
NBYTES=0XFF;N=N-255
RELOAD=1

End

Figure 25-22 Transfer sequence flowchart for I2C master receiver for N >255 bytes

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I2C master receiver 2 bytes, automatic end mode(STOP)

RXNE RXNE

S ADDR A DATA1 A DATA2 NA P

INIT EV1 EV2


NBYTES
xx 2

INIT：program Slave address，NBYTES=2，AUTOEND=1 reception

EV1：RXNE ISR, read DATA1


S transmission
EV2：RXNE ISR, read DATA2

NBYTES SCL stretch

I2C master receiver 2 bytes, software end mode(RESTART)

RXNE RXNE TC

S ADDR A DATA1 A DATA2 NA SR ADDR

INIT
EV1 EV2

NBYTES

xx 2

INIT：program Slave address，NBYTES=2，AUTOEND=0 reception

EV1：RXNE ISR, read DATA1


S transmission
EV2：RXNE ISR, read DATA2
SCL stretch
EV3：TC ISR， program Slave address, NBYTES，set START

Figure 25-23 Transfer bus diagrams for I2C master receiver

25.2.10. I2Cx_TIMINGR register configuration examples

The tables below provide examples of how to program the I2C_TIMINGR to obtain timings compliant with
the I2C specification. There is an error between configuration values and the actual synchronous values.
Table 25-6 Examples of timings settings forFI2CCLK=8M
Parameter Standard-mode Fast-mode Fast-mode Plus
10kHz 100kHz 400kHz 500kHz
PRESC 1 1 0 0
SCLL 0xC7 0x13 0x9 0x6

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TSCLL 200*250ns=50μs 20*250ns=5μs 10*125ns=1250ns 7*125ns=875ns


SCLH 0xC3 0xF 0x3 0x3
TSCLH 196*250ns=49μs 16*250ns=4μs 4*125ns=500ns 4*125ns=500ns
TSCL ~100μs ~10μs ~2500ns ~2000ns
SDADEL 0x2 0x2 0x1 0x0
TSDADEL 2*250ns=500ns 2*250ns=500ns 1*125ns=125ns 0ns
SCLDEL 0x4 0x4 0x3 0x1
TSCLDEL 5*250ns=1250ns 5*250ns=1250ns 4*125ns=500ns 2*125ns=250ns
Table 25-7 Examples of timings settings forFI2CCLK=16M
Parameter Standard-mode Fast-mode Fast-mode Plus
10kHz 100kHz 400kHz 1000kHz
PRESC 3 3 1 0
SCLL 0xC7 0x13 0x9 0x4
TSCLL 200*250ns=50μs 20*250ns=5μs 10*125ns=1250ns 5*62.5ns=312.5ns
SCLH 0xC3 0xF 0x3 0x2
TSCLH 196*250ns=49μs 16*250ns=4μs 4*125ns=500ns 3*62.5ns=187.5ns
TSCL ~100μs ~10μs ~2500ns ~1000ns
SDADEL 0x2 0x2 0x2 0x0
TSDADEL 2*250ns=500ns 2*250ns=500ns 2*125ns=125ns 0ns
SCLDEL 0x4 0x4 0x3 0x2
TSCLDEL 5*250ns=1250ns 5*250ns=1250ns 4*125ns=500ns 3*62.5ns=187.5ns
Table 25-8 Examples of timings settings for FI2CCLK=48M
Parameter Standard-mode Fast-mode Fast-mode Plus
10kHz 100kHz 400kHz 1000kHz
PRESC 0xB 0xB 5 5
SCLL 0xC7 0x13 0x9 0x3
TSCLL 200*250ns=50μs 20*250ns=5μs 10*125ns=1250ns 4*125ns=500ns
SCLH 0xC3 0xF 0x3 0x1
TSCLH 196*250ns=49μs 16*250ns=4μs 4*125ns=500ns 2*125ns=250ns
TSCL ~100μs ~10μs ~2500ns ~875ns
SDADEL 0x2 0x2 0x3 0x0
TSDADEL 2*250ns=500ns 2*250ns=500ns 3*125ns=375ns 0ns
SCLDEL 0x4 0x4 0x3 0x1
TSCLDEL 5*250ns=1250ns 5*250ns=1250ns 4*125ns=500ns 2*125ns=250ns

25.2.11. SMBus specific features

The System Management Bus (SMBus) is a two-wire interface through which various devices can
communicate with each other and with the rest of the system. It is based on I2C principles of operation.
SMBus provides a control bus for system and power management related tasks.

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This peripheral is compatible with the SMBUS specification rev 2.0(http://smbus.org/specs/).

The System Management Bus Specification refers to three types of devices.


● A slave is a device that receives or responds to a command.
● A master is a device that issues commands, generates the clocks and terminates the transfer.
● A host is a specialized master that provides the main interface to the system’s CPU. A host must be a
master-slave and must support the SMBus host notify protocol. Only one host is allowed in a system.

This peripheral can be configured as master or slave device, and also as a host.

Bus protocols
There are eleven possible command protocols for any given device. A device may use any or all of the
eleven protocols to communicate. The protocols are Quick Command, Send Byte, Receive Byte, Write Byte,
Write Word, Read Byte, Read Word, Process Call, Block Read, Block Write and Block Write-Block Read
Process Call. These protocols should be implemented by the user software.

For more details of these protocols, refer to SMBus specification version 2.0 (http://smbus.org/specs/).

Address resolution protocol (ARP)


SMBus slave address conflicts can be resolved by dynamically assigning a new unique address to each
slave device. In order to provide a mechanism to isolate each device for the purpose of address assignment
each device must implement a unique device identifier (UDID). This 128-bit number is implemented by
software.

This peripheral supports the Address Resolution Protocol (ARP). The SMBus Device Default Address
(0b1100 001) is enabled by setting SMBDEN bit in I2Cx_CR1 register. The ARP commands should be
implemented by the user software.

Arbitration is also performed in slave mode for ARP support.

For more details of the SMBus Address Resolution Protocol, refer to SMBus specification version 2.0
(http://smbus.org/specs/).

Received Command and Data acknowledge control


A SMBus receiver must be able to NACK each received command or data. In order to allow the ACK control
in slave mode, the Slave Byte Control mode must be enabled by setting SBC bit in I2Cx_CR1 register.

Host Notify protocol


This peripheral supports the Host Notify protocol by setting the SMBHEN bit in the I2C_CR1 register. In this
case the host will acknowledge the SMBus Host address (0b0001 000).

When this protocol is used, the device acts as a master and the host as a slave.

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SMBus alert
The SMBus ALERT optional signal is supported. A slave-only device can signal the host through the
SMBALERT# pin that it wants to talk. The host processes the interrupt and simultaneously accesses all
SMBALERT# devices through the Alert Response Address (0b0001 100). Only the device(s) which pulled
SMBALERT# low will acknowledge the Alert Response Address.

When configured as a slave device(SMBHEN=0), the SMBA pin is pulled low by setting the ALERTEN bit in
the I2Cx_CR1 register. The Alert Response Address is enabled at the same time.

When configured as a host (SMBHEN=1), the ALERT flag is set in the I2Cx_ISR register when a falling edge
is detected on the SMBA pin and ALERTEN=1. An interrupt is generated if the ERRIE bit is set in the
I2Cx_CR1 register. When ALERTEN=0, the ALERT line is considered high even if the external SMBA pin is
low.

If the SMBus ALERT pin is not needed, the SMBA pin can be used as a standard GPIO if ALERTEN=0.

Packet error checking


A packet error checking mechanism has been introduced in the SMBus specification to improve reliability
and communication robustness. Packet Error Checking is implemented by appending a Packet Error Code
8 2
(PEC) at the end of each message transfer. The PEC is calculated by using the C(x)=x +x +x+1
CRC8polynomial on all the message bytes (including addresses and read/write bits).

The peripheral embeds a hardware PEC calculator and allows to send a Not Acknowledge automatically
when the received byte does not match with the hardware calculated PEC.

Timeouts
This peripheral embeds hardware timers in order to be compliant with the 3 timeouts defined in SMBus
specification version 2.0.
Table 25-9 SMBus timeout specifications
Limits
Symbol Parameter Unit
Min Max
TTIMOUT Detect clock low timeout 25 35 ms
TLOW:SEXT Cumulative clock low extend time (slave device) - 25 ms
TLOW:MEXT Cumulative clock low extend time (master device) - 10 ms
TLOW:SEXTis the cumulative time a given slave device is allowed to extend the clock cycles in one message
from the initial START to the STOP. It is possible that, another slave device or the master will also extend the
clock causing the combined clock low extend time to be greater than T LOW:SEXTis. Therefore, this parameter
is measured with the slave device as the sole target of a full-speed master.

TLOW:MEXT is the cumulative time a master device is allowed to extend its clock cycles within each byte of a
message as defined from START-to-ACK, ACK-to-ACK, or ACK-to-STOP. It is possible that a slave device
or another master will also extend the clock causing the combined clock low time to be greater than
TLOW:MEXT on a given byte. Therefore, this parameter is measured with a full speed slave device as the sole

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target of the master.

Bus idle detection


A master can assume that the bus is free if it detects that the clock and data signals have been high for T IDLE
greater than THIGH,MAX.

This timing parameter covers the condition where a master has been dynamically added to the bus and may
not have detected a state transition on the SMBCLK or SMBDAT lines. In this case, the master must wait
long enough to ensure that a transfer is not currently in progress. The peripheral supports a hardware bus
idle detection.

Start Stop

TLOW:SEXT

TLOW:MEXT TLOW:MEXT TLOW:MEXT

SMBCLK

SMBCLK

ACK ACK

Figure 25-24 Timeout intervals for TLOW:MEXT, TLOW:SEXT

25.2.12. SMBus initialization

This section is relevant only when SMBus feature is supported. In addition to I2C initialization, some other
specific initialization must be done in order to perform SMBus communication:

Received Command and Data Acknowledge control


A SMBus receiver must be able to NACK each received command or data. In order to allow ACK control in
slave mode, the Slave Byte Control mode must be enabled by setting the SBC bit in the I2Cx_CR1 register.

Specific address (Slave mode)


The specific SMBus addresses should be enabled if needed.
● The SMBus Device Default address (0b1100 001) is enabled by setting the SMBDEN bit in the
I2Cx_CR1 register.
● The SMBus Host address (0b0001 000) is enabled by setting the SMBHEN bit in the I2Cx_CR1 register.
● The Alert Response Address (0b0001100) is enabled by setting the ALERTEN bit in the I2C_CR1
register.

Packet error checking

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PEC calculation is enabled by setting the PECEN bit in the I2Cx_CR1 register. Then the PEC transfer is
managed with the help of a hardware byte counter: NBYTES[7:0] in the I2Cx_CR2 register. The PECEN bit
must be configured before enabling the I2C.

The PEC transfer is managed with the hardware byte counter, so the SBC bit must be set when interfacing
the SMBus in slave mode. The PEC is transferred after NBYTES-1 data have been transferred when the
PECBYTE bit is set and the RELOAD bit is cleared. If RELOAD is set, PECBYTE has no effect.

Caution: Changing the PECEN configuration is not allowed when the I2C is enabled.
Table 25-10 SMBus with PEC configuration
Mode SBC RELOAD AUTOEND PECBYTE
Master Tx/Rx NBYTES+PEC+STOP x 0 1 1
Master Tx/Rx NBYTES+PEC+RESTART x 0 0 1
Slave Tx/Rx with +PEC 1 0 x 1

Timeout detection
The timeout detection is enabled by setting the TIMOUTEN and TEXTEN bits in the I2C_TIMEOUTR
register. The timers must be programmed in such a way that the
● TTIMEOUT check
In order to enable theTTIMEOUT check, the 12-bit TIMEOUTA[11:0] bits must be programmed with the timer
reload value in order to check the tTIMEOUT parameter. The TIDLE bit must be configured to ‘0’ in order to
detect the SCL low level timeout. Then the timer is enabled by setting the TIMOUTEN in the
I2Cx_TIMEOUTR register. If SCL is tied low for a time greater than(TIMEOUTA+1)*2048*T I2C_CLK, the
TIMEOUT flag is set in the I2Cx_ISR register.

Caution: Changing the TIMEOUTA[11:0] bits and TIDLE bit configuration is not allowed when the
TIMEOUTEN bit is set.
● TLOW:SEXT and TLOW:MEXT check
Depending on if the peripheral is configured as a master or as a slave, The 12-bit TIMEOUTB timer must be
configured in order to check TLOW:SEXT for a slave and TLOW:MEXT for a master. As the standard specifies only a
maximum, you can choose the same value for the both. Then the timer is enabled by setting the TEXTEN bit
in the I2Cx_TIMEOUTR register. If the SMBus peripheral performs a cumulative SCL stretch for a time
greater than (TIMEOUTB+1)*2048*TI2C_CLK, and in the timeout interval described in Bus idle the
TIMEOUT flag is set in the I2Cx_ISR register.

Caution: Changing the TIMEOUTB configuration is not allowed when the TEXTEN bit is set.

Bus Idle detection


In order to enable the TIDLE check, the 12-bit TIMEOUTA[11:0] field must be programmed with the timer
reload value in order to obtain the tIDLE parameter. The TIDLE bit must be configured to ‘1 in order to detect
both SCL and SDA high level timeout. Then the timer is enabled by setting the TIMOUTEN bit in the
I2Cx_TIMEOUTR register. If both the SCL and SDA lines remain high for a time greater than
(TIMEOUTA+1)*4*TI2C_CLK , the TIMEOUT flag is set in the I2Cx_ISR register.

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25.2.13. I2C_TIMEOUTR register configuration examples

This section is relevant only when SMBus feature is supported.


 Configuring the maximum duration of TIMEOUT to 25 ms
Table 25-11 Examples of TIMEOUTA settings for various I2CCLK frequencies
FI2CCLK TIMEOUTA TIDLE TIMEOUTEN TTIMEOUT
8MHz 0x61 0 1 98*2048*125ns=25ms
16MHz 0xC3 0 1 196*2048*62.5ns=25ms
48MHz 0x249 0 1 586*2048*20.08ns=25ms
 Configuring the maximum duration of TLOW:SEXT and TLOW:MEXTto 8 ms
Table 25-12 Examples of TIMEOUTB settings for various I2CCLK frequencies
FI2CCLK TIMEOUTB TEXTEN TLOW:EXT
8MHz 0x1F 1 32*2048*125ns=8ms
16MHz 0x3F 1 64*2048*62.5ns=8ms
48MHz 0xBB 1 188*2048*20.08ns=8ms
 Configuring the maximum duration of TIDLE to 50μs
Table 25-13 Examples of TIMEOUTA settings for various I2CCLK frequencies(T IDLE)
FI2CCLK TIMEOUTA TIDLE TIMEOUTEN TIDLE
8MHz 0x63 1 1 100*4*125ns=50μs
16MHz 0xC7 1 1 200*4*62.5ns=50μs
48MHz 0x257 1 1 600*4*20.08ns=50μs

25.2.14. SMBus slave mode

This section is relevant only when SMBus feature is supported.

In addition to 2C slave transfer management some additional software flowcharts are provided to support
SMBus.

SMBus Slave transmitter


When the IP is used in SMBus, SBC must be programmed to ‘1’ in order to allow the PEC transmission at
the end of the programmed number of data bytes. When the PECBYTE bit is set, the number of bytes
programmed in NBYTES[7:0] includes the PEC transmission. In that case the total number of TXIS
interrupts will be NBYTES-1 and the content of the I2C_PECR register is automatically transmitted if the
master requests an extra byte after the NBYTES-1 data transfer.

Caution: The PECBYTE bit has no effect when the RELOAD bit is set.

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Fremont Micro Devices FT32F0xxx8 RM

SMBus slave
transmission

Slave transmission

No

ADDR=1？

Yes
SCL
Read ADDRCODE and set DIR stretched
bit , NBYTES=N+1, set ADDRCF

TXIS=1？
No
Yes
Write TXDATA
register

Figure 25-25 Transfer sequence flowchart for SMBus slave transmitter N bytes + PEC

ADDR TXIS TXIS

S ADDR A DATA1 A DATA2 A PEC NA P

EV1 EV2 EV3


NBYTES
xx 3

EV1：ADDR ISR, read ADDCODR, program


NBYTES=3，set PECBYTTE and ADDRCF transmission

EV2：TXIS ISR , write DATA1


S reception

EV3：TXIS ISR, write DATA2


SCL stretch

Figure 25-26 Transfer bus diagrams for SMBus slave transmitter (SBC=1)

SMBus Slave receiver


When the I2C is used in SMBus mode, SBC must be programmed to ‘1’ in order to allow the PEC checking
at the end of the programmed number of data bytes. In order to allow the ACK control of each byte, the
reload mode must be selected (RELOAD=1).

In order to check the PEC byte, the RELOAD bit must be cleared and the PECBYTE bit must be set. In this

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Fremont Micro Devices FT32F0xxx8 RM

case, after NBYTES-1 data have been received, the next received byte is compared with the internal
I2Cx_PECR register content. A NACK is automatically generated if the comparison does not match, and an
ACK is automatically generated if the comparison matches, whatever the ACK bit value. Once the PEC byte
is received, it is copied into the I2Cx_RXDR register like any other data, and the RXNE flag is set.

In the case of a PEC mismatch, the PECERR flag is set and an interrupt is generated if the ERRIE bit is set
in the I2C_CR1 register.

If no ACK software control is needed, you can program PECBYTE=1 and, in the same write operation,
program NBYTES with the number of bytes to be received in a continuous flow. After NBYTES-1 are
received, the next received byte is checked as being the PEC.

Caution: The PECBYTE bit has no effect when the RELOAD bit is set.

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Fremont Micro Devices FT32F0xxx8 RM

SMBus slave
reception

Slave initialization

No

ADDR=1？

Yes SCL stetch

Read ADDRCODE and DIR bit，


NBYTES=N+1，set ADDRCF

RXNE=1？ No
TCR=1？

Yes

Read RXDATA，program
NACK=0，NBYTES=1,N=N-1

No
N=1?

Yes

Read RXDATA，program
RELOAD=0,NACK=0,NBYTES=1

No
RXNE=1?

Yes

Read RXDATA

End

Figure 25-27 Transfer sequence flowchart for SMBus slave receiver

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Fremont Micro Devices FT32F0xxx8 RM

ADDR RXNE RXNE RXNE

S ADDR A DATA1 A DATA2 A PEC A P

EV1 EV2 EV3 EV4


NBYTES
xx 3

EV1：ADDR ISR，read ADDCODR， program


NBYTES=3，RELOAD=0， set PECBYTTE and
ADDRCF transmission

EV2：RXNE ISR, read DATA1


S reception

EV3：RXNE ISR, read DATA2


SCL stretch
EV4：RXNE ISR, read PEC

ADDR RXNE,TCR RXNE,TCR RXNE

S ADDR A DATA1 A DATA2 A PEC A P

EV1 EV2 EV3 EV4


NBYTES
xx 1

EV1：ADDR ISR, read ADDCODR, program transmissio


NBYTES=3，RELOAD=1, set PECBYTTE and ADDRCF n

EV2：RXNE,TCR ISR, read DATA1, write NACK=0， S reception


NBYTES=1

EV3：RXNE,TCR ISR, read DATA2, write NACK=0，


SCL stretch
NBYTES=1，RELOAD=0

EV4：RXNE,TCR ISR, read PEC

Figure 25-28 Bus transfer diagrams for SMBus slave receiver (SBC=1)
This section is relevant only when SMBus feature is supported. In addition to I2C master transfer
management some additional software flowcharts are provided to support SMBus.

SMBus Master transmitter


When the SMBus master wants to transmit the PEC, the PECBYTE bit must be set and the number of bytes
must be programmed in the NBYTES[7:0] field, before setting the START bit. In this case the total number of
TXIS interrupts will be NBYTES-1. So if the PECBYTE bit is set when NBYTES=0x1, the content of the
I2Cx_PECR register is automatically transmitted.

If the SMBus master wants to send a STOP condition after the PEC, automatic end mode should be
selected (AUTOEND=1). In this case, the STOP condition automatically follows the PEC transmission.

When the SMBus master wants to send a RESTART condition after the PEC, software mode must be
selected (AUTOEND=0). In this case, once NBYTES-1 have been transmitted, the I2C_PECR register

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Fremont Micro Devices FT32F0xxx8 RM

content is transmitted and the TC flag is set after the PEC transmission, stretching the SCL line low. The
RESTART condition must be programmed in the TC interrupt subroutine.
Caution: The PECBYTE bit has no effect when the RELOAD bit is set.

TXIS TXIS

S ADDR A DATA1 A DATA2 A PEC A P

INIT EV1 EV2

TXE

NBYTES
xx 3

INIT：program slave address, write NBYTES=3，


AUTOEND=1, set PECBYTE and START reception

EV1：TXIS ISR, write DATA1


S transmission

EV2：TXIS ISR, write DATA2


TXIS TXIS SCL stretch

S ADDR A DATA1 A DATA2 A PEC A SR ADDR

INIT EV1 EV2 EV3

TXE

NBYTES
xx 3 N

INIT：program slave address, write NBYTES=3， reception


AUTOEND=0， set PECBYTE and START
S transmission
EV1：TXIS ISR, write DATA1

EV2：TXIS ISR, write DATA2 SCL stretch

EV3：TC ISR, program slave address, NBYTES, set


START

Figure 25-29 Bus transfer diagrams for SMBus master transmitter


SMBus Master receiver
When the SMBus master wants to receive the PEC followed by a STOP at the end of the transfer, automatic
end mode can be selected (AUTOEND=1). The PECBYTE bit must be set and the slave address must be
programmed, before setting the START bit. In this case, after NBYTES-1 data have been received, the next
received byte is automatically checked versus the I2C_PECR register content. A NACK response is given to
the PEC byte, followed by a STOP condition.

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Fremont Micro Devices FT32F0xxx8 RM

When the SMBus master receiver wants to receive the PEC byte followed by a RESTART condition at the
end of the transfer, software mode must be selected (AUTOEND=0). The PECBYTE bit must be set and the
slave address must be programmed, before setting the START bit. In this case, after NBYTES-1 data have
been received, the next received byte is automatically checked versus the I2C_PECR register content. The
TC flag is set after the PEC byte reception, stretching the SCL line low. The RESTART condition can be
programmed in the TC interrupt subroutine.
Caution: The PECBYTE bit has no effect when the RELOAD bit is set.

ADDR RXNE RXNE RXNE

S ADDR A DATA1 A DATA2 A PEC NA P

INIT EV1 EV2 EV3


NBYTES
xx 3

INIT：program slave address, NBYTES=3，


AUTOEND=1，set PECBYTE and START
reception
EV1：RXNE ISR, read DATA1

S transmission
EV2：RXNE ISR, read DATA2

EV3：RXNE ISR, read PEC SCL stretch

RXNE RXNE RXNE TC

S ADDR A DATA1 A DATA2 A PEC NA SR ADDR

EV1 EV2 EV3 EV4


NBYTES
xx 3 N

INIT：program slave address, NBYTES=3，


reception
AUTOEND=0，set PECBYTE and START

EV1：RXNE ISR, read DATA1 S transmission

EV2：RXNE ISR, read DATA2 SCL stretch

EV3：RXNE ISR, read PEC

EV4：TC ISR, program slave address, NBYTES=N，set


START

Figure 25-30 Bus transfer diagrams for SMBus master receiver

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Fremont Micro Devices FT32F0xxx8 RM

25.2.15. Error conditions

The following are the error conditions which may cause communication to fail.

Bus error (BERR)


A bus error is detected when a START or a STOP condition is detected and is not located after a multiple of
9 SCL clock pulses. A START or a STOP condition is detected when a SDA edge occurs while SCL is high.

The bus error flag is set only if the I2C is involved in the transfer as master or addressed slave (i.e not during
the address phase in slave mode).

In case of a misplaced START or RESTART detection in slave mode, the I2C enters address recognition
state like for a correct START condition.

When a bus error is detected, the BERR flag is set in the I2Cx_ISR register, and an interrupt is generated if
the ERRIE bit is set in the I2Cx_CR1 register.

Arbitration lost(ARLO)
An arbitration loss is detected when a high level is sent on the SDA line, but a low level is sampled on the
SCL rising edge.
● In master mode, arbitration loss is detected during the address phase, data phase and data
acknowledge phase. In this case, the SDA and SCL lines are released, the START control bit is cleared
by hardware and the master switches automatically to slave mode.
● In slave mode, arbitration loss is detected during data phase and data acknowledge phase. In this case,
the transfer is stopped, and the SCL and SDA lines are released.

When an arbitration loss is detected, the ARLO flag is set in the I2Cx_ISR register, and an interrupt is
generated if the ERRIE bit is set in the I2Cx_CR1 register.

Overrun/underrun error (OVR)


An overrun or underrun error is detected in slave mode when NOSTRETCH=1 and:
● In reception when a new byte is received and the RXDR register has not been read yet. The new
received byte is lost, and a NACK is automatically sent as a response to the new byte.
● In transmission:
—When STOPF=1 and the first data byte should be sent. The content of the I2Cx_TXDR register is sent
if TXE=0, 0xFF if not.
—When a new byte should be sent and the I2Cx_TXDR register has not been written yet, 0xFF is sent.

When an overrun or underrun error is detected, the OVR flag is set in the I2Cx_ISR register, and an interrupt
is generated if the ERRIE bit is set in the I2Cx_CR1 register.

Packet Error Checking Error (PECERR)


This section is relevant only when the SMBus feature is supported.

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Fremont Micro Devices FT32F0xxx8 RM

A PEC error is detected when the received PEC byte does not match with the I2Cx_PECR register content.
A NACK is automatically sent after the wrong PEC reception.

When a PEC error is detected, the PECERR flag is set in the I2Cx_ISR register, and an interrupt is
generated if the ERRIE bit is set in the I2Cx_CR1 register.

Timeout Error (TIMEOUT)


This section is relevant only when the SMBus feature is supported.

A timeout error occurs for any of these conditions:


● TIDLE=0 and SCL remained low for the time defined in the TIMEOUTA[11:0] bits: this is used to detect a
SMBus timeout.
● TIDLE=1 and both SDA and SCL remained high for the time defined in the TIMEOUTA [11:0] bits: this is
used to detect a bus idle condition.
● Master cumulative clock low extend time reached the time defined in the TIMEOUTB[11:0] bits (SMBus
TLOW:MEXT parameter)
● Slave cumulative clock low extend time reached the time defined in TIMEOUTB[11:0] bits (SMBus
TLOW:SEXT parameter)

When a timeout violation is detected in master mode, a STOP condition is automatically sent.

When a timeout violation is detected in slave mode, SDA and SCL lines are automatically released.

When a timeout error is detected, the TIMEOUT flag is set in the I2Cx_ISR register, and an interrupt is
generated if the ERRIE bit is set in the I2Cx_CR1 register.

Alert (ALERT)
This section is relevant only when the SMBus feature is supported.

The ALERT flag is set when the I2C interface is configured as a Host (SMBHEN=1), the alert pin detection is
enabled (ALERTEN=1) and a falling edge is detected on the SMBA pin. An interrupt is generated if the
ERRIE bit is set in the I2Cx_CR1 register.

25.2.16. DMA requests

Transmission using DMA


DMA (Direct Memory Access) can be enabled for transmission by setting the TXDMAEN bit in the I2C_CR1
register. Data is loaded from an SRAM area configured using the DMA peripheral to the I2Cx_TXDR register
whenever the TXIS bit is set.

Only the data are transferred with DMA.

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Fremont Micro Devices FT32F0xxx8 RM

● In master mode: the initialization, the slave address, direction, number of bytes and START bit are
programmed by software (the transmitted slave address cannot be transferred with DMA). When all data
are transferred using DMA, the DMA must be initialized before setting the START bit. The end of transfer
is managed with the NBYTES counter.
● In slave mode:
－With NOSTRETCH=0, when all data are transferred using DMA, the DMA must be initialized before
the address match event, or in ADDR interrupt subroutine, before clearing ADDR.
－With NOSTRETCH=1, the DMA must be initialized before the address match event.
● For instances supporting SMBus: the PEC transfer is managed with NBYTES counter.

Note: If DMA is used for transmission, the TXIE bit does not need to be enabled.

Reception using DMA


DMA (Direct Memory Access) can be enabled for reception by setting the RXDMAEN bit in the I2Cx_CR1
register. Data is loaded from the I2Cx_RXDR register to an SRAM area configured using the DMA peripheral
whenever the RXNE bit is set. Only the data (including PEC) are transferred with DMA.
● In master mode, the initialization, the slave address, direction, number of bytes and START bit are
programmed by software. When all data are transferred using DMA, the DMA must be initialized before
setting the START bit. The end of transfer is managed with the NBYTES counter.
● In slave mode with NOSTRETCH=0, when all data are transferred using DMA, the DMA must be
initialized before the address match event, or in the ADDR interrupt subroutine, before clearing the
ADDR flag.
● If SMBus is supported: the PEC transfer is managed with the NBYTES counter.

Note: If DMA is used for reception, the RXIE bit does not need to be enabled.

25.2.17. Debug mode

When the microcontroller enters debug mode (core halted), the SMBus timeout either continues to work
normally or stops, depending on the DBG_I2Cx_SMBUS_TIMEOUT configuration bits in the DBG module.

25.2.18. Low-power modes

Table 25-14 low-power modes


Mode Description
Sleep No effect I2C interrupts cause the device to exit the Sleep mode.
Stop The I2C is disabled but its registers content is kept.
Standby The I2C peripheral is powered down and must be reinitialized after exiting Standby.

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Fremont Micro Devices FT32F0xxx8 RM

25.2.19. Interrupts

Table 25-15 Interrupt requests


Interrupt event Event flag Interrupt clearing Interrupt enable control bit
Receive buffer not empty RXNE Read 2C_RXDR register RXIE
Transmit buffer interrupt TXIS Write I2C_TXDR register TXIE
status
Stop detection STOPF Write STOPCF=1 STOPIE
Transfer Complete Reload TCR Write NBYTES!=0
TCIE
Transfer complete TC Write START=1 or STOP=1
Address matched ADDR Write ADDRCF=1 ADDRIE
NACK reception NACKF Write NACKCF=1 NACKIE
Bus error BERR Write BERRCF=1
Overrun/Underrun OVR Write OVRCF=1
PEC error PECERR Write PECERRCF=1 ERRIE
Timeout error TIMEOUT Write TIMEOUTCF=1
SMBus Alert ALERT Write ALERTCF=1

Depending on the product implementation, all these interrupts events can either share the same interrupt
vector (I2C global interrupt), or be grouped into 2 interrupt vectors (I2C event interrupt and I2C error
interrupt).
In order to enable the I2C interrupts, the following sequence is required:
1. Configure and enable the I2C IRQ channel in the NVIC.
2. Configure the I2C to generate interrupts.

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Fremont Micro Devices FT32F0xxx8 RM

TCR
TC
TCIE

TXIS
TXIE

RXNE
RXNEIE I2C interrupt
glonal interrupt

STOPF
STOPIE

ADDR
ADDRIE erro interrupt

ERRIE
NACKF
NACKIE

BERR
OVR
ARLO
TIMEOUT PECERR
ALERT

Figure 25-31 I2C interrupt mapping diagram

Rev1.3 534 2024-03-22


0x28
0x24
0x20
0x18
0x14
0x10
0x08
0x04
0x00

0x1C
0x0C

Rev1.3
Address offset

Reset
Reset
Reset
Reset
Reset
Reset
Reset
Reset
Reset
Reset
Reset
Name

I2C_CR2
I2C_CR1

I2Cx_ICR
I2Cx_ISR
I2C_OAR1

I2Cx_OAR2

I2Cx_TXDR
I2Cx_RXDR
I2Cx_PECR
I2Cx_TIMINGR

I2Cx_TIMEOUTR
Fremont Micro Devices

x
x
x
x
x
x
x
x
x
– – – – – TEXTEN – – – – 31

x
x
x
x
x
0x
x
x
x
x
– – – – – – – – – – 30

0
PRESC[3:0]

x
x
x
x
x
x
x
x
x
– – – – – – – – – x – 29

x
x
x
x
x
x
x
x
x
x

– – – – – – – – – – 28

x
x
x
x
x
0x
x
x
x
x

– – – – – – – – – – 27

x
x
x
x
x
x
x
x
x

– – – – – – – – PECBYTE – 26

0
0
25.3. I2C register map

x
x
x
x
x
x
x
x
x

– – – – – – – – AUTOEND – 25

0
0

x
x
x
x
x
x
x
x
x

– – – – – – – – RELOAD – 24

0
0

x
x
x
x
x
x
– – – – – – PECEN 23

0
0
0
0
0

x
x
x
x
x
x
– – – – – – ALERTEBN 22

0
0
0
0
0

TIMEOUTB[11:0] SCLDEL[3:0]

x
x
x
x
x
– – – – – x – SMBDEN 21

0
0
0
0
0

x
x
x
x
x
x
– – – – ADDCODE[6:0] – – SMBHEN 20

0
0
0
0
0

NBYTE[7:0]

x
x
x
x
x
x

– – – – – – GCEN 19

535
0
0
0
0

x
x
x
x
x
x
0x

– – – – – – – 18

0
0
0
0

SDADEL[3:0]

x
x
x
x
x
x

– – – – – – NOSTRETCH 17

0
0
0
0

x
x
x
x
x
x
0x

– – – – DIR – – SBC 16

0
0
0
0

x
x
x
x
– – – – BUSY TIMOUTEN OA2EN OA1EN NACK RXDMAEN 15

0
0
0

x
x
x
x
0x
0x
0x
0x

– – – – – – – – STOP TXDMAEN 14

0
0

x
x
x
x
x
x
0x

– – – ALERTCF ALERT – – – START – 13

0
0
0
0

x
x
x
x
x

– – – TIMEOUTCF TIMEOUT TIDLE – – HEAD10R ANOFF 12

0
0
0
0
0
0

SCLH[7:0]

x
x
x
x
x

– – – PECCF PECERR – – ADD10 11

0
0
0
0
0
0

x
x
x
– – – OVRCF OVR OA1MODE RD_WRN 10

0
0
0
0
0
0
0
0

DNF[3:0]

x
x
x
– – – ARLOCF ARLO OA2MSK[2:0] 9

0
0
0
0
0
0
0
0

x
x
x
– – – BERRCF BERR 8

0
0
0
0
0
0
0
0

– TCR ERRIE 7

0
0
0
0
0
0
0
0
0
0
0

– TC TCIE 6

0
0
0
0
0
0
0
0
0
0
0

TIMEOUTA[11:0]
STOPCF STOPF STOPIE 5

0
0
0
0
0
0
0
0
0
0
0

OA1[9:0] SADD[9:0]
NACKCF NACKF OA2[7:1] NACKIE 4

0
0
0
0
0
0
0
0
0
0
0

TXDATA[7:0] RXDATA[7:0] PECR[7:0] SCLL[7:0]


ADDRCF ADDR ADDRIE 3

0
0
0
0
0
0
0
0
0
0

0x
– RXNE RXIE 2

0
0
0
0
0
0
0
0
0
0

x
– TXIS TXIE 1

0
0
0
0
0
0
0
0
0

x
0x

– TXE – PE 0

0
0
0
1
0
0
0
0
0
FT32F0xxx8 RM

2024-03-22
Fremont Micro Devices FT32F0xxx8 RM

25.3.1. Control register 1 (I2Cx_CR1)

bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0


31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 PECEN ALERTEN SMBDEN SMBHEN GCEN — NOSTRE SBC
TCH
type RW RW RW RW RW RO-0 RW RW
15:8 RXDMAEN TXDMAEN — ANFOFF DNF[3:0]
type RW RW RO-0 RW RW RW RW RW
7:0 ERRIE TCIE STOPIE NACKIE ADDRIE RXIE TXIE PE
type RW RW RW RW RW RW RW RW

Bit Name Function


31:24 NA Reserved, undefined
23 PECEN 0: PEC calculation disabled
1: PEC calculation enabled
22 ALERTEN SMBus alert enable
0: SMBus alert is disabled
1: SMBus alert is enabled
21 SMBDEN SMBus Device Default address enable
0: Device default address disabled. Address 0b1100001x is NACKed.
1: Device default address enabled. Address 0b1100001x is ACKed.
20 SMBHEN SMBus Host address enable
0: Host address disabled. Address 0b0001000x is NACKed.
1: Host address enabled. Address 0b0001000x is ACKed.
19 GCEN General call enable
0: General call disabled. Address 0b00000000 is NACKed.
1: General call enabled. Address 0b00000000 is ACKed.
18 NA Reserved, undefined
17 NOSTRETCH Clock stretching disable
0: Clock stretching enabled
1: Clock stretching disabled
16 SBC Slave byte control
This bit is used to enable hardware byte control in slave mode.
0: Slave byte control disabled
1: Slave byte control enabled
15 RXDMAEN DMA reception requests enable
0: DMA mode disabled for reception
1: DMA mode enabled for reception
14 TXDMAEN DMA transmission requests enable
0: DMA mode disabled for transmission

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Fremont Micro Devices FT32F0xxx8 RM

1: DMA mode enabled for transmission


13 NA Reserved, undefined
12 ANFOFF Analog noise filter OFF
0: Analog noise filter enabled
1: Analog noise filter disabled
Note: PF6(I2C2SCL), PF7(I2C2SDA) do not have Analog noise filter
11:8 DNF Digital noise filter,
0: Digital noise filter is disabled
x: Digital filter enabled and filtering capability up to x I2C clock
7 ERRIE Error interrupts enable
0: Error detection interrupts disabled
1: Error detection interrupts enabled
6 TCIE Transfer Complete interrupt enable
0: Transfer Complete interrupt disabled
1: Transfer Complete interrupt enabled
5 STOPIE STOP detection Interrupt enable
0: Stop detection (STOPF) interrupt disabled
1: Stop detection (STOPF) interrupt enabled
4 NACKIE Not acknowledge received Interrupt enable
0: Not acknowledge (NACKF) received interrupts disabled
1: Not acknowledge (NACKF) received interrupts enabled
3 ADDRIE Address match Interrupt enable (slave only)
0: Address match (ADDR) interrupts disabled
1: Address match (ADDR) interrupts enabled
2 RXIE RX Interrupt enable
0: Receive (RXNE) interrupt disabled
1: Receive (RXNE) interrupt enabled
1 TXIE TX Interrupt enable
0: Transmit (TXIS) interrupt disabled
1: Transmit (TXIS) interrupt enabled
0 PE Peripheral enable
0: Peripheral disable
1: Peripheral enable

25.3.2. Control register 2 (I2Cx_CR2)

bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0


31:24 — PECBYTE AUTOEND RELOAD
type RO-0 RO-0 RO-0 RO-0 RO-0 RW RW RW
23:16 NBYTES[7:0]
type RW RW RW RW RW RW RW RW

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Fremont Micro Devices FT32F0xxx8 RM

15:8 NACK STOP START HEAD10R ADD10 RD_WRN SADD[9:8]


type RW RW RW RW RW RW RW RW
7:0 SADD[7:0]
type RW RW RW RW RW RW RW RW

Bit Name Function


31:27 NA Reserved, undefined
26 PECBYTE Packet error checking byte, This bit is cleared by hardware when PE=0.
0: No PEC transfer
1: PEC transmission/reception is requested,cleared by hardware when the
PEC is transferred
25 AUTOEND Automatic end mode (master mode)
0: software end mode: TC flag is set when NBYTES data are transferred,
stretching SCL low.
1: Automatic end mode: a STOP condition is automatically sent when
NBYTES data are transferred.
24 RELOAD NBYTES reload mode
0: The transfer is completed after the NBYTES data transfer
1: The transfer is not completed after the NBYTES data transfer (NBYTES
will be reloaded). TCR flag is set when NBYTES data are transferred,
stretching SCL low.
23:16 NBYTES Number of bytes
The number of bytes to be transmitted/received is programmed there. This
field is don’t care in slave mode with SBC=0.
Note: Changing these bits when the START bit is set is not allowed.
15 NACK NACK generation (slave mode)
0: an ACK is sent after current received byte.
1: a NACK is sent after current received byte.
14 STOP Stop generation (master mode)
0: No Stop generation.
1: Stop generation after current byte transfer.
13 START Start generation
This bit is set by software, and cleared by hardware after the Start followed
by the address sequence is sent, by an arbitration loss, by a timeout error
detection, or when PE = 0.
0: No Start generation.
1: Restart/Start generation:
12 HEAD10R 10-bit address header only read direction (master receiver mode)
0: The master sends the complete 10 bit slave address read sequence: Start
+ 2 bytes 10bit
st
address in write direction + Restart + 1 7 bits of the 10 bit address in read
direction.

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st
1: The master only sends the 1 7 bits of the 10 bit address, followed by
Read direction.
11 ADD10 10-bit addressing mode (master mode)
0: The master operates in 7-bit addressing mode,
1: The master operates in 10-bit addressing mode
10 RD_WRN Transfer direction (master mode)
0: Master requests a write transfer.
1: Master requests a read transfer.
9:0 SADD Slave address,(master mode)
In 7-bit addressing mode (ADD10 = 0):
SADD[9:8] and SADD[0] bits are don’t care, SADD[7:1] should be written
with the 7-bit slave address to be sent
In 10-bit addressing mode (ADD10 = 1):
These bits should be written with bits 10 of the slave address to be sent.

25.3.3. Own address 1 register (I2Cx_OAR1)

bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0


31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 OA1EN — OA1MODE OA1[9:8]
type RW RO-0 RO-0 RO-0 RO-0 RW RW RW
7:0 OA1[7:0]
type RW

Bit Name Function


31:16 NA Reserved, undefined
15 OA1EN Own Address 1 enable
0: Own address 1 disabled.
1: Own address 1 enabled.
14:11 NA Reserved, undefined
10 OA1MODE Own Address 1 10-bit mode
0: Own address 1 is a 7-bit address.
1: Own address 1 is a 10-bit address.
9:0 OA1 Interface address
7-bit addressing mode:
OA1[9:8] and OA1[0] bits are don’t care, bits 7:1 of address
10-bit addressing mode:
bits 9:8 of address, bit 0 of address

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25.3.4. Own address 2 register(I2Cx_OAR2)

bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0


31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 OA2EN — OA2MSK[2:0]
type RW RO-0 RO-0 RO-0 RO-0 RW RW RW
7:0 OA1[7:1] —
type RW RW RW RW RW RW RW RO-0

Bit Name Function


31:16 NA Reserved, undefined
15 OA2EN Own Address 2 enable
0: Own address 2 disabled.
1: Own address 2 enabled.
14:11 NA Reserved, undefined
10:8 OA2MSK Own Address 2 masks
000: No mask
001: OA2[1] is masked and don’t care. Only OA2[7:2] are compared.
010: OA2[2:1] are masked and don’t care. Only OA2[7:3] are compared.
011: OA2[3:1] are masked and don’t care. Only OA2[7:4] are compared.
100: OA2[4:1] are masked and don’t care. Only OA2[7:5] are compared.
101: OA2[5:1] are masked and don’t care. Only OA2[7:6] are compared.
110: OA2[6:1] are masked and don’t care. Only OA2[7] is compared.
111: OA2[7:1] are masked and don’t care. No comparison is done, and all
(except reserved) 7-bit received addresses are acknowledged.
7:1 OA2 Interface address
bits 7:1 of address
0 NA Reserved, undefined

25.3.5. Timing register(I2Cx_TIMINGR)

bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0


31:24 PRESC[3:0] —
type RW RO-0 RO-0 RO-0 RO-0
23:16 SCLDEL[3:0] SDADEL[3:0]
type RW RW
15:8 SCLH[7:0]
type RW

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7:0 SCLL[7:0]
type RW

Bit Name Function


31:28 PRESC Timing prescaler
TPRESC=(PRESC+1)* TI2CCLK
27:24 NA Reserved, undefined
23:20 SCLDEL Data setup time
TSCLDEL=(SCLDEL+1)*TPRESC
19:16 SDADEL Data hold time
TSDADEL=SDADEL*TPRESC
15:8 SCLH SCL high period (master mode)
TSCLH=(SCLH+1)*TPRESC
7:0 SCLL SCL low period (master mode)
TSCLL=(SCLL+1)*TPRESC

25.3.6. Timeout register(I2Cx_TIMEOUTR)

bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0


31:24 TEXTEN — TIMOUTB[11:8]
type RW RO-0 RO-0 RO-0 RW
23:16 TIMOUTB[7:0]
type RW
15:8 TIMOUTEN — TIDLE TIDLE[11:8]
type RW RO-0 RO-0 RW RW
7:0 TIDLE[7:0]
type RW

Bit Name Function


31 TEXTEN Extended clock timeout enable
0: Extended clock timeout detection is disabled
1: Extended clock timeout detection is enabled. When a cumulative SCL
stretch for more than tLOW:EXT is done by the I2C interface, a timeout error
is detected (TIMEOUT=1).
30:28 NA Reserved, undefined
27:16 TIMEOUTB Bus timeout B
TLOW:EXT=(TIMEOUTB+1)*2048*TI2CCLK
15 TIMOUTEN Clock timeout enable
0: SCL timeout detection is disabled
1: SCL timeout detection is enabled: when SCL is low for more than T TIMEOUT
(TIDLE=0) or high for more than tIDLE (TIDLE=1), a timeout error is detected

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(TIMEOUT=1).
14:13 NA Reserved, undefined
12 TIDLE Idle clock timeout detection
0: TIMEOUTA is used to detect SCL low timeout
1: TIMEOUTA is used to detect both SCL and SDA high timeout (bus idle
condition)
11:0 TIMEOUTA Bus Timeout A
The SCL low timeout condition TTIMEOUT when TIDLE=0:
TTIMOUT=(TIMEOUTA+1)*2048*TI2CCLK
The bus idle condition (both SCL and SDA high) when TIDLE=1:
TIDLE=(TIMEOUTA+1)*4*TI2CCLK

25.3.7. Interrupt and status register(I2Cx_ISR)

bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0


31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 ADDCODE[6:0] DIR
type RO RO
15:8 BUSY — ALERT TIMEOUT PECERR OVR ARLO BERR
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
7:0 TCR TC STOPF NACKF ADDR RXNE TXIS TXE
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0

Bit Name Function


31:24 NA Reserved, undefined
23:17 ADDCODE Address match code (Slave mode)
These bits are updated with the received address when an address match
event occurs (ADDR = 1).
In the case of a 10-bit address, ADDCODE provides the 10-bit header followed
by the 2 MSBs of the address.
16 DIR Transfer direction (Slave mode)
0: Write transfer, slave enters receiver mode.
1: Read transfer, slave enters transmitter mode
15 BUSY Bus busy, It is cleared by hardware when PE=0.
0: This flag indicates that a communication is not in progress on the bus
1: This flag indicates that a communication is in progress on the bus
14 NA Reserved, undefined
13 ALERT SMBus alert
This bit is cleared by hardware when PE=0.
This flag is set by hardware when SMBHEN=1 (SMBus host configuration),

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ALERTEN=1 and a SMBALERT event (falling edge) is detected on SMBA pin. It


is cleared by software by setting the ALERTCF bit.
12 TIMEOUT Timeout or tLOW detection flag
This bit is cleared by hardware when PE=0. PE=0
This flag is set by hardware when a timeout or extended clock timeout
occurred. It is cleared by software by setting the TIMEOUTCF bit
11 PECERR PEC Error in reception
This bit is cleared by hardware when PE=0.
This flag is set by hardware when the received PEC does not match with the
PEC register content. A NACK is automatically sent after the wrong PEC
reception. It is cleared by software by setting the PECCF bit.
10 OVR Overrun/Underrun (slave mode)
This flag is set by hardware in slave mode with NOSTRETCH=1, when an
overrun/underrun error occurs. It is cleared by software by setting the OVRCF
bit.
Note: This bit is cleared by hardware when PE=0.
9 ARLO Arbitration lost
This flag is set by hardware in case of arbitration loss. It is cleared by software
by setting the ARLOCF bit.
Note: This bit is cleared by hardware when PE=0.
8 BERR Bus error
This flag is set by hardware when a misplaced Start or Stop condition is
detected whereas the peripheral is involved in the transfer. The flag is not set
during the address phase in slave mode. It is cleared by software by setting
BERRCF bit.
Note: This bit is cleared by hardware when PE=0.
7 TCR Transfer Complete Reload
This flag is set by hardware when RELOAD=1 and NBYTES data have been
transferred. It is cleared by software when NBYTES is written to a non-zero
value.
Note: This bit is cleared by hardware when PE=0.
6 TC Transfer Complete (master mode)
This flag is set by hardware when RELOAD=0, AUTOEND=0 and NBYTES
data have been transferred. It is cleared by software when START bit or STOP
bit is set.
Note: This bit is cleared by hardware when PE=0.
5 STOPF Stop detection flag
This flag is set by hardware when a Stop condition is detected on the bus and
the peripheral is involved in this transfer:
– either as a master, provided that the STOP condition is generated by the
peripheral.
– or as a slave, provided that the peripheral has been addressed previously
during this

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transfer.
It is cleared by software by setting the STOPCF bit.
Note: This bit is cleared by hardware when PE=0
4 NACKF This flag is set by hardware when a NACK is received after a byte transmission.
It is cleared by software by setting the NACKCF bit.
Note: This bit is cleared by hardware when PE=0.
3 ADDR Address matched (slave mode)
This bit is set by hardware as soon as the received slave address matched with
one of the enabled slave addresses. It is cleared by software by setting
ADDRCF bit.
Note: This bit is cleared by hardware when PE=0.
2 RXNE Receive data register not empty (receivers)
This bit is set by hardware when the received data is copied into the I2C_RXDR
register, and is ready to be read. It is cleared when I2C_RXDR is read.
Note: This bit is cleared by hardware when PE=0.
1 TXIS Transmit interrupt status (transmitters)
This bit is set by hardware when the I2C_TXDR register is empty and the data
to be transmitted must be written in the I2C_TXDR register. It is cleared when
the next data to be sent is written in the I2C_TXDR register.
This bit can be written to ‘1’ by software when NOSTRETCH=1 only, in order to
generate a TXIS event (interrupt if TXIE=1 or DMA request if TXDMAEN=1).
Note: This bit is cleared by hardware when PE=0.
0 TXE Transmit data register empty (transmitters)
This bit is set by hardware when the I2C_TXDR register is empty. It is cleared
when the next data to be sent is written in the I2C_TXDR register.
This bit can be written to ‘1’ by software in order to flush the transmit data
register I2C_TXDR.
Note: This bit is set by hardware when PE=0.

25.3.8. Interrupt clear register(I2Cx_ICR)

bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0


31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 — ALERTCF TIMEOUTCF PECCF OVRCF ARLOCF BERRCF
type RO-0 RO-0 WO WO WO WO WO WO
7:0 — STOPCF NACKCF ADDRCF —
type RO-0 RO-0 WO WO WO RO-0 RO-0 RO-0

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Bit Name Function


31:14 NA Reserved, undefined
13 ALERTCF Alert flag clear
Writing 1 to this bit clears the ALERT flag in the I2C_ISR register.
12 TIMOUTCF Timeout detection flag clear
Writing 1 to this bit clears the TIMEOUT flag in the I2C_ISR register
11 PECCF PEC Error flag clear
Writing 1 to this bit clears the PECERR flag in the I2C_ISR register
10 OVRCF Overrun/Underrun flag clear
Writing 1 to this bit clears the OVR flag in the I2C_ISR register.
9 ARLOCF Arbitration Lost flag clear
Writing 1 to this bit clears the ARLO flag in the I2C_ISR register.
8 BERRCF Bus error flag clear
Writing 1 to this bit clears the BERRF flag in the I2C_ISR register.
7:6 NA Reserved, undefined
5 STOPCF Stop detection flag clear
Writing 1 to this bit clears the STOPF flag in the I2C_ISR register.
4 NACKF Not Acknowledge flag clear
Writing 1 to this bit clears the ACKF flag in I2C_ISR register.
3 ADDRCF Address Matched flag clear
Writing 1 to this bit clears the ADDR flag in the I2C_ISR register. Writing 1 to
this bit also clears the START bit in the I2C_CR2 register.
2:0 NA Reserved, undefined

25.3.9. PEC register(I2Cx_PECR)

bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0


31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
7:0 PEC[7:0]
type RO

Bit Name Function


31:8 NA Reserved, undefined
7:0 PEC Packet error checking register
This field contains the internal CRC code when PECEN=1.

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25.3.10. Receive data register(I2Cx_RXDR)

bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0


31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
7:0 RXDATA[7:0]
type RO

Bit Name Function


31:8 NA Reserved, undefined
7:0 RXDATA 8-bit receive data
Data byte received from the I2C bus.

25.3.11. Transmit data register(I2Cx_TXDR)

bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0


31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
7:0 TXDATA[7:0]
type RW

Bit Name Function


31:8 NA Reserved, undefined
7:0 TXDATA 8-bit transmit data
Data byte to be transmitted to the I2C bus.

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26. Universal synchronous asynchronous


receiver transmitter(USART)

26.1. USART main features

 Full-duplex asynchronous communications


 NRZ standard format
 Configurable oversampling method by 16 or 8 to give flexibility between speed and clock tolerance
 A common programmable transmit and receive baud rate of up to 9 Mbit/s when the clock
frequency is 72 MHz and oversampling is by 8
 Convenient baud rate programming
 Auto baud rate detection
 Programmable data word length(8 or 9 bit)
 Programmable data order with MSB-first or LSB-first shifting
 Configurable stop bits (1 or 2 stop bits)
 Synchronous mode and clock output for synchronous communications
 Single-wire half-duplex communications
 Continuous communications using DMA
—Received/transmitted bytes are buffered in reserved SRAM using centralized DMA
 Separate enable bits for transmitter and receiver
 Separate signal polarity control for transmission and reception
 Swappable Tx/Rx pin configuration
 Hardware flow control for modem and RS-485 transceiver
 Communication control/error detection flags
 Parity control
—Transmits parity bit
—Checks parity of received data byte
 Fourteen interrupt sources with flags
 Multiprocessor communications The USART enters mute mode if the address does not match.
 Wakeup from mute mode (by idle line detection or address mark detection).

26.2. USART functional description

26.2.1. USART implementation

This manual describe the full set of features implemented in USART1, USART2supports a smaller set of
features, but is otherwise identical to USART1. The differences are listed below.

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Table 26-1 USART implementation


USART features USART1 USART2
Hardware flow control for modem √ √
Continuous communication using DMA √ √
Multiprocessor communication √ √
Synchronous mode √ √
half- duplex communication √ √
Receiver timeout interrupt √ -
Auto baud rate detection √ -
RS485 drive enable signal √ √

26.2.2. Functional description

The interface connect with external device by 3 pins as shown in Figure 26-1, any USART bidirectional
communication requires a minimum of two pins: Receive data In (RX) and Transmit data Out (TX):

RX: Receive data Input. This is the serial data input. Oversampling techniques are used for data recovery by
discriminating between valid incoming data and noise.

TX: Transmit data Output. When the transmitter is disabled, the output pin returns to its I/O port
configuration. When the transmitter is enabled and nothing is to be transmitted, the TX pin is at high level. In
single-wire half- duplex communication, this I/O is used to transmit and receive the data.

Serial data are transmitted and received through these pins in normal USART mode. The frames are
comprised of:
 An Idle Line prior to transmission or reception
 A start bit
 A data word(8 or 9 bit)least significant bit first
 1,1.5,2 stop bits indicating that the frame is complete
 The USART interface uses a baud rate generator (12-bit integer, 4-bit demicals)
 A status register(USART_ISR)
 Receive and transmit data registers(USART_RDR,USART_TDR)
 A baud rate register USART_BRR)

The following pin is required to interface in synchronous mode


 SCLK: Clock output. This pin outputs the transmitter data clock for synchronous transmission
corresponding to SPI master mode (no clock pulses on start bit and stop bit, and a software option to
send a clock pulse on the last data bit). In parallel, data can be received synchronously on RX. This can
be used to control peripherals that have shift registers (e.g. LCD drivers). The clock phase and polarity
are software programmable.

The following pin is required in Hardware control mode:

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 nCTS: Clear To Send blocks the data transmission at the end of the current transfer when high
 nRTS: Request to send indicates that the USART is ready to receive data (when low).

The following pin is required in RS485 Hardware control mode:


 DE: Driver Enable activates the transmission mode of the external transceiver

Note:DE and nRTS share the same pin.

APB BUS

CPU/DMA Write CPU/DMA Read

TDR RDR

Transmit shift Receive shift


register register

SCLK
TX SCL control
SIR/ENDEC
block
RX
GT PSC USART_CR2

USART_CR3
USART_CR1
nRTS/DE
Hardware flow
controller
nCTS

Transmit control Receiver control

USART_CR1 USART_ISR

Interrupt control

/8*（2-OVER8） /USART_DIV USART_BRR

Fclk

Figure 26-1 USART block diagram

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26.2.3. USART character description

The word length can be selected as being either 8 or 9 bits by programming the M0 bits in the USARTx_CR1
register
 8-bit character length: M0=0
 9-bit character length: M0=1

In default configuration, the signal (TX or RX) is in low state during the start bit. It is in high state during the
stop bit. These values can be inverted, separately for each signal, through polarity configuration control.

An Idle character is interpreted as an entire frame of “1”s. (The number of “1” ‘s will include
the number of stop bits).

A Break character is interpreted on receiving “0”s for a frame period. At the end of the break frame, the
transmitter inserts 2 stop bits.

Transmission and reception are driven by a common baud rate generator, the clock for each is generated
when the enable bit is set respectively for the transmitter and receiver.

The details of each block is given below.

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9 Bit word length 1stop bit


Possible
Parity
Data Frame bit Next Start Next Frame

Start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit8 Stop

Clock
*

Break Frame
Stop Start

Idle Frame

Start

* LBCL control this clock

8 Bit word length 1stop bit

Data Frame Next Start Next Frame

Start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 Stop

Clock *

Break Frame
Stop Start

Idle Frame

Start

*LBCL control this clock

Figure 26-2 Word length programming

26.2.4. Transmitter

The transmitter can send data words of either 8 or 9 bits depending on the M bits status. The Transmit
Enable bit (TE) must be set in order to activate the transmitter function. The data in the transmit shift register
is output on the TX pin and the corresponding clock pulses are output on the SCLK pin.

Character transmission
During an USART transmission, data shifts out least significant bit first (default configuration) on the TX pin.
In this mode, the USARTx_TDR register consists of a buffer (TDR) between the internal bus and the
transmit shift register. Every character is preceded by a start bit which is a logic level low for one bit period.
The character is terminated by a configurable number of stop bits. The following stop bits are supported by
USART: 1, 1.5 and 2 stop bits.

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Note1: The TE bit must be set before writing the data to be transmitted to the USARTx_TDR. The TE bit
should not be reset during transmission of data. Resetting the TE bit during the transmission will corrupt the
data on the TX pin.
Note2: An idle frame will be sent after the TE bit is enabled.
Configurable stop bits
The number of stop bits to be transmitted with every character can be programmed in Control register 2, bits
13,12
1. 1 stop bit: This is the default value of number of stop bits.
2. 2 stop bits: This will be supported by normal USART, single-wire and modem modes.

An idle frame transmission will include the stop bits.

A break transmission will be 10 low bits (when M= 0) or 11 low bits (when M= 1) or followed by 2 stop bits. It
is not possible to transmit long breaks (break of length greater than 10/11 low bits).

8 Bit data 1 Stop bit

Data Frame Next Start Next Frame

bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 1Stop

Clock
*

*LBCL bit controls this clock

8 Bit data 1.5 Stop bits


Data Frame Next Start Next Frame

bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 1.5Stop

8 Bit data 2 Stop bits


Data Frame Next Start Next Frame

bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 2Stop

Figure 26-3 Configurable stop bits


Character transmission procedure
1. Program the M0 bits in USARTx_CR1 to define the word length.
2. Select the desired baud rate using the USARTx_BRR register.
3. Program the number of stop bits in USARTx_CR2.
4. Enable the USART by writing the UE bit in USARTx_CR1 register to 1.
5. Select DMA enable (DMAT) in USARTx_CR3 if multibuffer communication is to take place. Configure
the DMA register as explained in multibuffer communication.
6. Set the TE bit in USARTx_CR1 to send an idle frame as first transmission.
7. Write the data to send in the USARTx_TDR register (this clears the TXE bit). Repeat this for each data
to be transmitted in case of single buffer. Wait for TXE set before repeat procedure 7;
8. After writing the last data into the USARTx_TDR register, wait until TC=1. This indicates that the

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transmission of the last frame is complete. This is required for instance when the USART is disabled or
enters the Halt mode to avoid corrupting the last transmission.

Single byte communication


Clearing the TXE bit is always performed by a write to the transmit data register. The TXE bit is set by
hardware and it indicates:
● The data has been moved from the USARTx_TDR register to the shift register and the data
transmission has started.
● The USARTx_TDR register is empty.
● The next data can be written in the USARTx_TDR register without overwriting the previous data.

This flag generates an interrupt if the TXEIE bit is set.

When a transmission is taking place, a write instruction to the USARTx_TDR register stores the data in the
TDR register; next, the data is copied in the shift register at the end of the currently ongoing transmission.

When no transmission is taking place, a write instruction to the USARTx_TDR register places the data in the
shift register, the data transmission starts, and the TXE bit is set.

If a frame is transmitted (after the stop bit) and the TXE bit is set, the TC bit goes high. An interrupt is
generated if the TCIE bit is set in the USARTx_CR1 register.

After writing the last data in the USARTx_TDR register, it is mandatory to wait for TC=1 before disabling the
USART(Figure 26-4).

IDLE

TX line

TXE flag

USART_TDR F1 F2 F3

TC flag

Wait untilTXE=1, TC is not set, TC is not set, TC is not set,


Set UE
and writes F2 to DR becasuse TXE=0 becasuse TXE=0 becasuse TXE=1

Figure 26-4 TC/TXE behavior when transmitting

Break characters
Setting the SBKRQ bit transmits a break character. The break frame length depends on the M0 bit(Figure
26-2).

If a ‘1’ is written to the SBKRQ bit, a break character is sent on the TX line after completing the current
character transmission. The SBKF bit is set by the write operation and it is reset by hardware when the

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break character is completed (during the stop bits after the break character). The USART inserts a logic 1
signal (STOP) for the duration of 2 bits at the end of the break frame to guarantee the recognition of the start
bit of the next frame.

Idle characters
Setting the TE bit drives the USART to send an idle frame before the first data frame.

26.2.5. Receiver

The USART can receive data words of either 8 or 9 bits depending on the M0 bits in the USARTx_CR1
register.

Start bit detection


The start bit detection sequence is the same when oversampling by 16 or by 8.

In the USART, the start bit is detected when a specific sequence of samples is recognized. This sequence is:
1110X0X0X 0X0X0X0.

IDLE
LOW_DET START

RX line

Sample clk

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

sampled
values
7/16 7/16

one-bit time

Sample Data 1 1 0 X 0 X 0 X 0 0 0 0 X X X X X X X
Falling edge
detection
Zero Zero

Sampled value is 0 if two of the three is 0

Figure 26-5 Start bit detection timing


Note: If the sequence is not complete, the start bit detection aborts and the receiver returns to the
idle state (no flag is set), where it waits for a falling edge.

Character reception
During an USART reception, data shifts in least significant bit first (default configuration) through the RX pin.
In this mode, the USARTx_RDR register consists of a buffer (RDR) between the internal bus and the receive
shift register.

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Procedure:
1. Program the M0 bits in USARTx_CR1 to define the word length.
2. Select the desired baud rate using the baud rate register USARTx_BRR
3. Program the number of stop bits in USARTx_CR2.
4. Enable the USART by writing the UE bit in USARTx_CR1 register to 1.
5. Select DMA enable (DMAR) in USARTx_CR3 if multibuffer communication is to take place. Configure
the DMA register as explained in multibuffer communication.
6. Set the RE bit USARTx_CR1. This enables the receiver which begins searching for a start bit.

When a character is received:


● The RXNE bit is set to indicate that the content of the shift register is transferred to the RDR. In other
words, data has been received and can be read (as well as its associated error flags).
● An interrupt is generated if the RXNEIE bit is set.
● The error flags can be set if a frame error, noise or an overrun error has been detected during reception.
PE flag can also be set with RXNE.
● In multibuffer, RXNE is set after every byte received and is cleared by the DMA read of the Receive data
Register.
● In single buffer mode, clearing the RXNE bit is performed by a software read to the USARTx_RDR
register. The RXNE flag can also be cleared by writing 1 to the RXFRQ in the USARTx_RQR register.
The RXNE bit must be cleared before the end of the reception of the next character to avoid an overrun
error.

Break character
When a break character is received, the USART handles it as a framing error.

Idle character
When an idle frame is detected, there is the same procedure as for a received data character plus an
interrupt if the IDLEIE bit is set.

Overrun error
An overrun error occurs when a character is received when RXNE has not been reset. Data can not be
transferred from the shift register to the RDR register until the RXNE bit is cleared.
The RXNE flag is set after every byte received. An overrun error occurs if RXNE flag is set when the next
data is received or the previous DMA request has not been serviced. When an overrun error occurs:
● The ORE bit is set.
● The RDR content will not be lost. The previous data is available when a read to USARTx_RDR is
performed.
● The shift register will be overwritten. After that point, any data received during overrun is lost.
● An interrupt is generated if either the RXNEIE bit is set or EIE bit is set.
● The ORE bit is reset by setting the ORECF bit in the ICR register.

Note: The ORE bit, when set, indicates that at least 1 data has been lost. There are two possibilities:
if RXNE=1, then the last valid data is stored in the receive register RDR and can be read.
If RXNE=0, then it means that the last valid data has already been read and thus there is nothing to be read

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in the RDR. This case can occur when the last valid data is read in the RDR at the same time as the new
(and lost) data is received.

Selecting the clock source and the proper oversampling method


The choice of the clock source is done through the Clock Control system (see Section 7: Reset and clock
control).
The clock source must be chosen before enabling the USART (by setting the UE bit).

The choice of the clock source must be done according to two criteria:
● Possible use of the USART in low-power mode
● Communication speed.

The clock source frequency is fCK.

The communication speed range (specially the maximum communication speed) is also determined by the
clock source.

The receiver implements different user-configurable oversampling techniques for data recovery by
discriminating between valid incoming data and noise. This allows a trade-off between the maximum
communication speed and noise/clock inaccuracy immunity.

The oversampling method can be selected by programming the OVER8 bit in the USARTx_CR1 register
and can be either 16 or 8 times the baud rate clock (Figure 26-6 and Figure 26-7).

Depending on the application:


● Select oversampling by 8 (OVER8=1) to achieve higher speed (up to fCK/8). In this case the maximum
receiver tolerance to clock deviation is reduced.
● Select oversampling by 16 (OVER8=0) to increase the tolerance of the receiver to clock deviations. In
this case, the maximum speed is limited to maximum fCK/16 where fCK is the clock source frequency.

Programming the ONEBIT bit in the USARTx_CR3 register selects the method used to evaluate the logic
level. There are two options:
● The majority vote of the three samples in the center of the received bit. In this case, when the 3 samples
used for the majority vote are not equal, the NF bit is set
● A single sample in the center of the received bit

Depending on the application:


－select the three samples’ majority vote method (ONEBIT=0) when operating in a noisy environment and
reject the data when a noise is detected because this indicates that a glitch occurred during the sampling.
－select the single sample method (ONEBIT=1) when the line is noise-free to increase the receiver’s
tolerance to clock deviations. In this case the NF bit will never be set.

When noise is detected in a frame: The NF bit is set. It will generate an interrupt if the EIE bit is set in the

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USARTx_CR3 register. The NF bit is reset by setting NFCF bit in ICR register.

RX line

Sample clk

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

sampled
values
7/16 7/16

one bit time

Figure 26-6 Data sampling when oversampling by 16

RX line

Sample clk

1 2 3 4 5 6 7 8

sampled values
3/8 3/8

one bit time

Figure 26-7 Data sampling when oversampling by 8


Table 26-2 Noise detection from sampled data
Sampled value NF status Received bit value
000 0 0
001 1 0
010 1 0
011 1 1
100 1 0
101 1 1
110 1 1
111 0 1

Framing error
A framing error is detected when:
The stop bit is not recognized on reception at the expected time, following either a de- synchronization or
excessive noise.

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When the framing error is detected: The FE bit is set by hardware; An interrupt will be issued if the EIE bit is
set in the USARTx_CR3 register. The FE bit is reset by writing 1 to the FECF in the USARTx_ICR register.

Configurable stop bits during reception


The number of stop bits to be received can be configured through the control bits of Control Register 2, it
can be either 1 or 2 in normal mode.
th th th
● 1 stop bit: Sampling for 1 stop Bit is done on the 8 , 9 and 10 samples.
th th th
● 2 stop bits: Sampling for 2 stop bits is done on the 8 , 9 and 10 samples of the first stop bit. If a
framing error is detected during the first stop bit the framing error flag will be set. The second stop bit is
not checked for framing error. The RXNE flag will be set at the end of the first stop bit.

26.2.6. Baud rate generation

The baud rate for the receiver and transmitter (Rx and Tx) are both set to the same value as programmed in
the USARTx_BRR register.

Baud rate for standard USART (SPI mode included):


𝑓ck
Tx or Rx Braud =
8 × (2 − OVER8) × USARTDIV
USARTDIV is an unsigned fixed point number that is coded on the USARTx_BRR register
● When OVER8=0, the demicals is configured in USART_BRR [3:0], USARTDIV=USART_BRR.
● When OVER8=1, the demicals is configured in USART_BRR [2:0], USART_BRR[3] must be 0,
USARTDIV[11:4]=USART_BRR[11:4],USART_BRR[2:0]=USARTDIV[3:1].

Note: The baud counters are updated to the new value in the baud registers after a write operation to
USARTx_BRR. Hence the baud rate register value should not be changed during communication. The value
of the USARTDIV configuration must be greater than or equal to 16.

How to derive USARTDIV from USARTx_BRR register values


Example 1: To obtain 9600 baud with fCK = 8 MHz.
● In case of oversampling by 16:
USARTDIV=8000000/9600
BRR=USARTDIV=800d=0341h
● In case of oversampling by 8:
USARTDIV=2*8000000/9600=1666.66(1667d=683h)
BRR[3:0]=3h>>1=1h
BRR=0x681
Example 2: To obtain 921.6 Kbaud with fCK = 48 MHz.
● In case of oversampling by 16:
USARTDIV=48000000/921600
BRR=USARTDIV=52d=34h
● In case of oversampling by 8:

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USARTDIV=2*48000000/921600=104(104d=68h)
BRR[3:0]= USARTDIV[3:0]>>1 = 8h>>1=4h
BRR=0x64

Table 26-3 Error calculation for programmed baud rates at f CK = 48MHz in both cases of
oversampling by 16 or by 8
Baud rate Oversampling by 16 Oversampling by 8
S.No Desired Actual BRR Error% Actual BRR Error%
1 2.4kBps 2.4kBps 0x4E20 0 2.4kBps 0x9C40 0
2 9.6kBps 9.6kBps 0x1388 0 9.6kBps 0x2710 0
3 19.2kBps 19.2kBps 0x9C4 0 19.2kBps 0x1384 0
4 38.4kBps 38.4kBps 0x4E2 0 38.4kBps 0x9C2 0
5 57.6kBps 57.62kBps 0x341 0.03 57.59kBps 0x681 0.02
6 115.2kBps 115.11kBps 0x1A1 0.08 115.25kBps 0x340 0.04
7 230.4kBps 230.76kBps 0xD0 0.16 230.21kBps 0x1A0 0.08
8 460.8kBps 461.54kBps 0x68 0.16 461.54kBps 0xD0 0.16
9 921.6kBps 923.07kBps 0x34 0.16 923.07kBps 0x64 0.16
10 2MBps 2MBps 0x18 0 2MBps 0x30 0
11 3MBps 3MBps 0x10 0 3MBps 0x20 0
12 4Mbps NA NA NA 4MBps 0x14 0
13 5MBps NA NA NA 5052.63kBps 0x11 1.05
14 6MBps NA NA NA 6MBps 0x10 0
Note: The lower the CPU clock the lower the accuracy for a particular baud rate.

26.2.7. Tolerance of the USART receiver to clock deviation

The asynchronous receiver of the USART works correctly only if the total clock system deviation is less than
the tolerance of the USART receiver. The causes which contribute to the total deviation are:
● DTRA: Deviation due to the transmitter error (which also includes the deviation of the transmitter’s local
oscillator)
● DQUANT: Error due to the baud rate quantization of the receiver
● DREC: Deviation of the receiver’s local oscillator
● DTCL: Deviation due to the transmission line (generally due to the transceivers which can introduce an
asymmetry between the low-to-high transition timing and the high-to- low transition timing).
Requirement: DTRA+DQUANT+DREC+DTCL<USART receiver’s tolerance.
The USART receiver can receive data correctly at up to the maximum tolerated deviation specified
depending on the following choices:
● 10- or 11-bit character length defined by the M bits in the USARTx_CR1 register
● Oversampling by 8 or 16 defined by the OVER8 bit in the USARTx_CR1 register
● Demicals baud rate utilization
● Use of 1 bit or 3 bits to sample the data, depending on the value of the ONEBIT bit in the USARTx_CR3
register.

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Table 26-4 Tolerance of the USART receiver when BRR [3:0] = 0000
OVER8=0 OVER8=1
M0 位
ONEBIT=0 ONEBIT=1 ONEBIT=0 ONEBIT=1
0 3.75% 4.375% 2.5% 3.75%
1 3.41% 3.97% 2.27% 3.41%

Table 26-5 Tolerance of the USART receiver when BRR[3:0] is different from 0000
OVER8=0 OVER8=1
M0 位
ONEBIT=0 ONEBIT=1 ONEBIT=0 ONEBIT=1
0 3.33% 3.88% 2% 3%
1 3.03% 3.53% 1.82% 2.73%
Note: The data specified in Table 26-4 and Table 26-5 may slightly differ in the special case when the
received frames contain some Idle frames of exactly 10-bit durations when M0 bits = 0 (11-bit durations
when M00 bits = 1)

26.2.8. Auto baud rate detection

The USART is able to detect and automatically set the USARTx_BRR register value based on the reception
of one character. Automatic baud rate detection is useful under two circumstances:
● The communication speed of the system is not known in advance
● The system is using a relatively low accuracy clock source and this mechanism allows the correct baud
rate to be obtained without measuring the clock deviation.

The clock source frequency must be compatible with the expected communication speed(oversampling by
16 must be selected and baudrate between fCK/65535 and fCK/16).

Before activating the auto baud rate detection, the character must be confirmed first .They can be chosen
through the ABRMOD[1:0] field in the USARTx_CR2 register:
● Any character starting with a bit at 1. In this case the USART measures the duration of the Start bit
(falling edge to rising edge).
● Any character starting with a 10xx bit pattern. In this case, the USART measures the duration of the
st
Start and of the 1 data bit. The measurement is done falling edge to falling edge, ensuring better
accuracy in the case of slow signal slopes.

Prior to activating auto baud rate detection, the USARTx_BRR register must be initialized by writing a
non-zero baud rate value.

If the line is noisy, the correct baud rate detection cannot be guaranteed. In this case the BRR value may be
corrupted and the ABRE error flag will be set. This also happens if the communication speed is not
compatible with the automatic baud rate detection range (bit duration not between

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8(OVER8=1)/16(0VER8=0) and 65536 clock periods).

The RXNE interrupt will signal the end of the operation

At any later time, the auto baud rate detection may be relaunched by resetting the ABRF flag (by writing a 0).

Note: If the USART is disabled (UE=0) during an auto baud rate operation, the BRR value may be corrupted.

26.2.9. Multiprocessor communication

It is possible to perform multiprocessor communication with the USART (with several USARTs connected in
a network). For instance one of the USARTs can be the master, its TX output connected to the RX inputs of
the other USARTs. The others are slaves, their respective TX outputs are logically ANDed together and
connected to the RX input of the master.

In multiprocessor configurations it is often desirable that only the intended message recipient should actively
receive the full message contents, thus reducing redundant USART service overhead for all non addressed
receivers.

The non addressed devices may be placed in mute mode by means of the muting function. In order to use
the mute mode feature, the MME bit must be set in the USARTx_CR1 register.

In mute mode:
● None of the reception status bits can be set.
● All the receive interrupts are inhibited.
● The RWU bit in USARTx_ISR register is set to 1. RWU can be controlled automatically by hardware or
by software, through the MMRQ bit in the USARTx_RQR register, under certain conditions.
The USART can enter or exit from mute mode using one of two methods, depending on the WAKE bit in the
USARTx_CR1 register:
● Idle Line detection if the WAKE bit is reset
● Address Mark detection if the WAKE bit is set

Idle line detection (WAKE=0)

The USART enters mute mode when the MMRQ bit is written to 1 and the RWU is automatically set. It
wakes up when an Idle frame is detected(Figure 26-8).

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RXNE RXNE

DATA1 DATA2 DATA3 DATA4 IDLE DATA5 DATA6

RWU

MMRQ Idle frame detected

Figure 26-8 Mute mode using Idle line detection

4-bit/7-bit address mark detection (WAKE=1)

In this mode, bytes are recognized as addresses if their MSB is a ‘1’ otherwise they are considered as data.
In an address byte, the address of the targeted receiver is put in the 4 or 7 LSBs. The choice of 7 or 4-bit
address detection is done using the ADDM7 bit. This 4- bit/7-bit word is compared by the receiver with its
own address which is programmed in the ADD bits in the USARTx_CR2 register.

Note: In 7-bit and 9-bit data modes, address detection is done on 6-bit and 8-bit addresses (ADD[5:0] and
ADD[7:0]) respectively.

The USART enters mute mode when an address character is received which does not match its
programmed address. In this case, the RWU bit is set by hardware. The RXNE flag is not set for this address
byte and no interrupt or DMA request is issued when the USART enters mute mode.

The USART exits from mute mode when an address character is received which matches the programmed
address. Then the RWU bit is cleared and subsequent bytes are received normally. The RXNE bit is set for
the address character since the RWU bit has been cleared(Figure 26-9).

RXNE RXNE

IDLE ADDR=0 IDLE DATA1 ADDR=1 DATA2 ADDR=3 DATA3

RWU

MMRQ Matching address No-matching address

Figure 26-9 Mute mode using address mark detection

26.2.10. Parity control

Parity control (generation of parity bit in transmission and parity checking in reception) can be enabled by
setting the PCE bit in the USARTx_CR1 register. Depending on the frame length defined by the M0 bit, the
possible USART frame formats are as listed in Table 26-6.

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Table 26-6 Frame formats


M0 bit PCE USAR frame
0 0 start bit + 8-bit data + stop bit
0 1 start bit + 7-bit data + parity bit + stop bit
1 0 start bit + 9-bit data + stop bit
1 1 start bit + 8-bit data + parity bit + stop bit

Even parity
The parity bit is calculated to obtain an even number of “1s” inside the frame of the 7 or 8 (depending on M0
bits values) and the parity bit. (PS =0)

Odd parity
The parity bit is calculated to obtain an odd number of “1s” inside the frame of the 7 or 8 (depending on M0
bits values) and the parity bit. (PS =1)

Parity checking in reception


If the parity check fails, the PE flag is set in the USARTx_ISR register and an interrupt is generated if PEIE is
set in the USARTx_CR1 register. The PE flag is cleared by software writing 1 to the PECF in the
USARTx_ICR register.

Parity generation in transmission


If the PCE bit is set in USARTx_CR1, then the MSB bit of the data written in the data register is transmitted
but is changed by the parity bit

26.2.11. USART synchronous mode

The synchronous mode is selected by writing the CLKEN bit in the USARTx_CR2 register to 1. In
synchronous mode, the following bit must be kept cleared:
● HDSEL bit in the USARTx_CR3 register

In this mode, the USART can be used to control bidirectional synchronous serial communications in master
mode. The SCLK pin is the output of the USART transmitter clock. No clock pulses are sent to the SCLK pin
during start bit and stop bit. Depending on the state of the LBCL bit in the USARTx_CR2 register, clock
pulses are, or are not, generated during the last valid data bit (address mark). The CPOL bit in the
USARTx_CR2 register is used to select the clock polarity, and the CPHA bit in the USARTx_CR2 register is
used to select the phase of the external clock(see Figure 26-10 and Figure 26-11).

During the Idle state, preamble and send break, the external SCLK clock is not activated. In synchronous
mode the USART transmitter works exactly like in asynchronous mode. But as SCLK is synchronized with
TX (according to CPOL and CPHA), the data on TX is synchronous.

In this mode the USART receiver works in a different manner compared to the asynchronous mode. If RE=1,

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the data is sampled on SCLK (rising or falling edge, depending on CPOL and CPHA), without any
oversampling. A setup and a hold time must be respected

Note:The SCLK pin works in conjunction with the TX pin. Thus, the clock is provided only if the transmitter is
enabled (TE=1) and data is being transmitted (the data register USARTx_TDR written). This means that it is
not possible to receive synchronous data without transmitting data.

The LBCL, CPOL and CPHA bits have to be selected when the USART is disabled (UE=0) to ensure that the
clock pulses function correctly.

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8-bit data M=0

Clock CPOLY=0 CPHA=0 *

Clock CPOLY=0 CPHA=1 *

Clock CPOLY=1 CPHA=0 *

Clock CPOLY=1 CPHA=1 *

TX line Start Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7

RX line Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7

Capture strobe

* LBCL controls this clock

Figure 26-10 USART data clock timing diagram(M=0)

9-bit data M=0

Clock CPOLY=0 CPHA=0 *

Clock CPOLY=0 CPHA=1 *

Clock CPOLY=1 CPHA=0 *

Clock CPOLY=1 CPHA=1 *

TX line Start Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit8

RX line Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit8

Capture strobe

* LBCL controls this clock

Figure 26-11 USART data clock timing diagram(M=1)

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26.2.12. Single-wire half-duplex communication

Single-wire half-duplex mode is selected by setting the HDSEL bit in the USARTx_CR3 register. In this
mode, the following bit must be kept cleared:
● CLKEN bit in the USARTx_CR2 register

The USART can be configured to follow a single-wire half-duplex protocol where the TX and RX lines are
internally connected. The selection between half- and full-duplex communication is made with a control bit
HDSEL in USARTx_CR3.

As soon as HDSEL is written to 1:


● The TX and RX lines are internally connected
● The RX pin is no longer used
● The TX pin is always released when no data is transmitted. Thus, it acts as a standard I/O in idle or in
reception. It means that the I/O must be configured so that TX is configured as floating input (or
open-drain with an external pull-up). Apart from this, the communication protocol is similar to normal
USART mode. Any conflicts on the line must be managed by software (by the use of a centralized arbiter,
for instance). In particular, the transmission is never blocked by hardware and continues as soon as
data is written in the data register while the TE bit is set.

26.2.13. Continuous communication using DMA

The USART is capable of performing continuous communication using the DMA. The DMA requests for Rx
buffer and Tx buffer are generated independently.

Transmission using DMA


DMA mode can be enabled for transmission by setting DMAT bit in the USARTx_CR3 register. Data is
loaded from a SRAM area configured using the DMA peripheral to the USARTx_TDR register whenever the
TXE bit is set. To map a DMA channel for USART transmission, use the following procedure (x denotes the
channel number):
1. Write the USARTx_TDR register address in the DMA control register to configure it as the destination of
the transfer. The data is moved to this address from memory after each TXE event.
2. Write the memory address in the DMA control register to configure it as the source of the transfer. The
data is loaded into the USARTx_TDR register from this memory area after each TXE event.
3. Configure the total number of bytes to be transferred to the DMA control register.
4. Configure the channel priority in the DMA register
5. Configure DMA interrupt generation after half/ full transfer as required by the application.
6. Clear the TC flag in the USARTx_ISR register by setting the TCCF bit in the USARTx_ICR register.
7. Activate the channel in the DMA register.

When the number of data transfers programmed in the DMA Controller is reached, the DMA controller
generates an interrupt on the DMA channel interrupt vector.

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In transmission mode, once the DMA has written all the data to be transmitted (the TCIF flag is set in the
DMA_ISR register), the TC flag can be monitored to make sure that the USART communication is complete.
This is required to avoid corrupting the last transmission before disabling the USART or entering Stop mode.
Software must wait until TC=1. The TC flag remains cleared during all data transfers and it is set by
hardware at the end of transmission of the last frame(Figure 26-12)

IDLE

TX line

TXE flag

Ignored by DMA, because


DMA req the transfer is complete

USART_TDR F1 F2 F3

Cleared by software

DMA TCIF

TC flag

Set UE, DMA WaiteTXE=1, and TC is not set TC is not set TC is not set
send 3 data write data to TDR because TXE=0 because TXE=0 because TXE=1

Figure 26-12 Transmission using DMA


Reception using DMA
DMA mode can be enabled for reception by setting the DMAR bit in USARTx_CR3 register. Data is loaded
from the USARTx_RDR register to a SRAM area configured using the DMA peripheral whenever a data byte
is received.

To map a DMA channel for USART reception, use the following procedure:
1. Write the USARTx_RDR register address in the DMA control register to configure it as the source of the
transfer. The data is moved from this address to the memory after each RXNE event.
2. Write the memory address in the DMA control register to configure it as the destination of the transfer.
The data is loaded from USARTx_RDR to this memory area after each RXNE event.
3. Configure the total number of bytes to be transferred to the DMA control register
4. Configure the channel priority in the DMA control register
5. Configure interrupt generation after half/ full transfer as required by the application.
6. Activate the channel in the DMA control register.

When the number of data transfers programmed in the DMA Controller is reached, the DMA controller
generates an interrupt on the DMA channel interrupt vector (Figure 26-13).

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RX line

RXNE flag

DMA req

USART_RDR F1 F2 F3

The DMA transfer is


complete

DMA TCIF
set UE, DMA
Read F1 Read F2 Read F3
receive 3 data

Figure 26-13 Reception using DMA

Error flagging and interrupt generation in multibuffer communication


In multibuffer communication if any error occurs during the transaction the error flag is asserted after the
current byte. An interrupt is generated if the interrupt enable flag is set. For framing error, overrun error and
noise flag which are asserted with RXNE in single byte reception, there is a separate error flag interrupt
enable bit (EIE bit in the USARTx_CR3 register), which, if set, enables an interrupt after the current byte if
any of these errors occur.

26.2.14. Hardware flow control and RS485 Driver Enable

It is possible to control the serial data flow between 2 devices by using the nCTS input and the nRTS
output.The Figure 26-14 shows how to connect 2 devices in this mode:

USART1 USART2

TX RX

TX circuit RX circuit
nCTS nRTS

RX TX

RX circuit nRTS nCTS TX circuit

Figure 26-14 Hardware flow control between 2 USARTs

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Fremont Micro Devices FT32F0xxx8 RM

RTS and CTS flow control can be enabled independently by writing the RTSE and CTSE bits respectively to
1 (in the USARTx_CR3 register).

RTS flow control


If the RTS flow control is enabled (RTSE=1), then nRTS is asserted (tied low) as long as the USART
receiver is ready to receive a new data. When the receive register is full, nRTS is de-asserted, indicating that
the transmission is expected to stop at the end of the current frame. Figure 26-15 shows an example of
communication with RTS flow control enabled.

START START

RX DATA0 STOP IDLE DATA1 STOP

nRTS

DATA0 READ
RXNE DATA1 can send RXNE

Figure 26-15 RTS flow control


CTS flow control
If the CTS flow control is enabled (CTSE=1), then the transmitter checks the nCTS input before transmitting
the next frame. If nCTS is asserted (tied low), then the next data is transmitted (assuming that data is to be
transmitted, in other words, if TXE=0), else the transmission does not occur. When nCTS is de-asserted
during a transmission, the current transmission is completed before the transmitter stops.

When CTSE=1, the CTSIF status bit is automatically set by hardware as soon as the nCTS input toggles. It
indicates when the receiver becomes ready or not ready for communication. An interrupt is generated if the
CTSIE bit in the USARTx_CR3 register is set. Figure 26-16 shows an example of communication with CTS
flow control enabled.

START START

DATA1 STO DATA2 STOP IDLE DATA3


P
TX Write
DATA3

DATA2 empty DATA3 empty

TDR Wait nCTS=0 ，then


send DATA3
nCTS

Figure 26-16 CTS flow control


RS485 Driver Enable
The driver enable feature is enabled by setting bit DEM in the USARTx_CR3 control register. This allows the
user to activate the external transceiver control, through the DE (Driver Enable) signal. The assertion time is
the time between the activation of the DE signal and the beginning of the START bit. It is programmed using
the DEAT [4:0] bit fields in the USARTx_CR1 control register. The de-assertion time is the time between the

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Fremont Micro Devices FT32F0xxx8 RM

end of the last stop bit, in a transmitted message, and the de-activation of the DE signal. It is programmed
using the DEDT [4:0] bit fields in the USARTx_CR1 control register. The polarity of the DE signal can be
configured using the DEP bit in the USARTx_CR3 control register.

26.2.15. Low-power modes

Table 26-7 Effect of low-power modes on the USART


Mode Description
Sleep USART can received data, USART interrupt causes the device to exit Sleep mode
Stop USART is disabled and is not able to wake up the MCU from Stop mode.
Standby The USART is powered down and must be reinitialized when the device has exited from
Standby mode.

26.2.16. Interrupts

Table 26-8 USART interrupt requests


Interrupt event Event flag Enable Control bit
Transmit data register empty TXE TXEIE
CTS interrupt CTSIF CTSIE
Transmission Complete TC TCIE
Receive data register not empty RXNE
RXNEIE
Overrun error detected ORE
Idle line detected IDLE IDLEIE
Parity error PE PEIE
Noise Flag, Overrun error and NF or ORE or FE EIE
Framing Error
Character match CMF CMIE
Receiver timeout RTOF RTOIE

The USART interrupt events are connected to the same interrupt vector (Figure 26.15)
● During transmission: Transmission Complete, ransmit data Register empty.
● During reception: Idle Line detection, Overrun error, Receive data register not empty, Parity error, Noise
Flag, Framing Error, Character match, etc.

These events generate an interrupt if the corresponding Enable Control Bit is set.

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Fremont Micro Devices FT32F0xxx8 RM

TC
TCIE
TXE
TXIE
CTSIF
CTSI
USART
E
interrupt
IDLE
IDLEIE
RXNEIE
RXNE
ORE
RXNEIE
PE
PEIE

FE
NF
ORE EIE

CMF
CMIE
RTOF
RTOIE

Figure 26-17 USART interrupt mapping diagram

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Fremont Micro Devices FT32F0xxx8 RM

26.3. USART register map

31

30
29

28

27

26
25

24

23

22

21

20

19

18
17

16

15

14
13

12

11

10
Address offset Name

7
6

3
2

0
RXNEIE
OVER8

IDLEIE
RTIOE

WAKE

TXEIE
CMIE
DEAT[4:0]

DEDT[4:0]

MME

PEIE

TCIE
PCE
M1

M0

PS

TE
RE

UE
USARTx_CR1
–

–
–

–
0x00

Reset x x x 0x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x 0

MSBFIRST

STOP[1:0]
DATAINV
ABRMOD[1:0]
ADD[7:4]

ADD[3:0]

RTOEN

ABREN

ADDM7
CLKEN
RXINV
TXINV

SWAP

CPHA
CPOL

LBCL
USARTx_CR2

–
–

–
–

–
0x04

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x 0 0 0 0 0 0x x x 0x x x x

ONEBIT
OVRDIS

HDSEL
CTSIE

DMAR
DMAT
DDRE

CTSE

RTSE
DEM
DEP

EIE
USARTx_CR3
–

–
–

–
–

–
0x08

Reset x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0x x x 0x 0

BRR[15:0]
USARTx_BRR
–

–
–

–
–

–
–

–
0x0C

Reset x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RTOR[23:0]
USARTx_RTOR
–

–
–

–
–

0x14

Reset x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RXFRQ

SBKRQ

ABRRQ
MMRQ
USARTx_RQR
–

–
–

–
–

–
–

–
–

–
–

–
–

–
0x18

Reset x x x x x x x x x x x x x x x x x x x x x x x x x x x x 0 0 0 0
CTSIF
BUSY

ABRE

RXNE
SBKF

ABRF

RTOF

IDLE
CMF

ORE
CTS

TXE

PE
TC

NF

FE
USARTx_ISR
–

–
–

–
–

0x1C

Reset x x x x x x x x x x x x x 0 0 0 0 0x x 0 0 0x 1 1 0 0 0 0 0 0
IDLECF

ORECF
RTOCF

CTSCF
CMCF

PECF
TCCF

FECF
NCF
USARTx_ICR
–

–
–

–
–

–
–

0x20

Reset x x x x x x x x x x x x x x 0x x x x x 0x 0x x 0x 0 0 0 0 0
RDR[8:0]

USARTx_RDR
–

–
–

–
–

–
–

–
–

–
–

0x24

Reset x x x x x x x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0
TDR[8:0]

USARTx_TDR
–

–
–

–
–

–
–

–
–

0x28

Reset x x x x x x x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0

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Fremont Micro Devices FT32F0xxx8 RM

26.3.1. Control register 1 (USARTx_CR1)

bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0


31:24 — M1 — RTOIE DEAT[4:3]
type RO-0 RO-0 RO-0 RW RO-0 RW RW
23:16 DEAT[2:0] DEDT[4:0]
type RW RW
15:8 OVER8 CMIE MME M0 WAKE PCE PS PEIE
type RW RW RW RW RW RW RW RW
7:0 TXEIE TCIE RXNEIE IDLEIE TE RE UESM UE
type RW RW RW RW RW RW RW RW

Bit Name Function


31:29 NA Reserved, undefined
28 M1 Word length
This bit, with bit 12 (M0), determines the word length. It is set or cleared by
software.
M[1:0] = 00: 1 Start bit, 8 data bits, n stop bits
M[1:0] = 01: 1 Start bit, 9 data bits, n stop bits
M[1:0] = 10: 1 Start bit, 7 data bits, n stop bits
This bit can only be written when the USART is disabled (UE=0).
27 NA Reserved, undefined
26 RTOIE Receiver timeout interrupt enable
0: Receiver timeout interrupt disabled
1: Receiver timeout interrupt enabled
25:21 DEAT This 5-bit value defines the time between the activation of the DE (Driver
Enable) signal and the beginning of the start bit. It is expressed in sample
time units (1/8 or 1/16 bit duration, depending on the oversampling rate).
20:16 DEDT This 5-bit value defines the time between the end of the last stop bit, in a
transmitted message, and the de-activation of the DE (Driver Enable) signal.
It is expressed in sample time units (1/8 or 1/16 bit duration, depending on
the oversampling rate).
15 OVER8 Oversampling mode
0: Oversampling by 16
1: Oversampling by 8
14 CMIE Character match interrupt enable
0: Character match interrupt disabled
1: Character match interrupt enabled
13 MME Mute mode enable
0: Mute mode disabled
1: Mute mode enabled

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Fremont Micro Devices FT32F0xxx8 RM

12 M0 Word length
This bit determines the word length.
0: 8-bit data
1: 9-bit data
11 WAKE Receiver wakeup method
0: Idle line
1: Address mark
10 PCE Parity control enable
0: Parity control disabled
1: Parity control enabled
9 PS Parity selection
0: Odd parity
1: Even parity
8 PEIE PE interrupt enable
0: PE interrupt disabled
1: PE interrupt enabled
7 TXEIE TXE interrupt enable
0: TXE interrupt disabled
1: TXE interrupt enabled
6 TCIE Transmission complete interrupt enable
0: Transmission complete interrupt disabled
1: Transmission complete interrupt enabled
5 RXNEIE RXNE interrupt enable
0: RXNE interrupt disabled
1: RXNE interrupt enabled
4 IDLEIE IDLE interrupt enable
0: IDLE interrupt disabled
1: IDLE interrupt enabled
3 TE Transmitter enable
0: Transmitter is disabled
1: Transmitter is enabled
2 RE Receiver enable
0: Receiver is disabled
1: Receiver is enabled
1 NA Reserved, undefined
0 UE USART enable
0: USART disabled
1: USART enabled

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Fremont Micro Devices FT32F0xxx8 RM

26.3.2. Control register 2 (USARTx_CR2)

bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0


31:24 ADD[7:0]
type RW
23:16 RTOEN ABRMOD[1:0] ABRE MSBFIRST DATAINV TXINV RXINV
type RW RW RW RW RW RW RW
15:8 SWAP LINEN STOP[1:0] CLKEN CPOL CPHA LBCL
type RW RW RW RW RW RW RW
7:0 — ADDM —
type RO-0 RO-0 RO-0 RW RO-0 RO-0 RO-0 RO-0

Bit Name Function


31:24 ADD Address of the USART node
It can be used for 575ffecti detection during multiprocessor communication
and character detection during normal reception
23 RTOEN Receiver timeout enable
0: Receiver timeout feature disabled.
1: Receiver timeout feature enabled
22:21 ABRMOD Auto baud rate mode
00: Measurement of the start bit is used to detect the baud rate.
01: Falling edge to falling edge measurement.
1x: Reserved
20 ABREN Auto baud rate enable
0: Auto baud rate detection is disabled.
1: Auto baud rate detection is enabled.
19 MSBFIRST Most significant bit first
0: data is transmitted/received with data bit 0 first, following the start bit.
1: data is transmitted/received with the MSB first, following the start bit.
18 DATAINV Binary data inversion, include : parity bit
0: Logical data from the data register are send/received in positive/direct
logic. (1=H, 0=L)
1: Logical data from the data register are send/received in negative/inverse
logic. (1=L, 0=H).
17 TXINV TX pin active level inversion
0: TX pin signal works using the standard logic levels High level is idle
1: TX pin signal values are inverted. Low level is idle
16 RXINV RX pin active level inversion
0: RX pin signal works using the standard logic levels. High level is idle
1: RX pin signal values are inverted. Low level is idle
15 SWAP Swap TX/RX pins

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Fremont Micro Devices FT32F0xxx8 RM

1: The TX and RX pins functions are swapped


0: The TX and RX pins functions are not swapped
14 NA Reserved, undefined
13:12 STOP STOP bits
00: 1 stop bit
01: Reserved
10: 2 stop bits
11: 1.5 stop bits
11 CLKEN Clock enable
0: SCLK pin disabled
1: SCLK pin enabled
10 CPOL Clock polarity
0: Steady low value on SCLK pin outside transmission window
1: Steady high value on SCLK pin outside transmission window
9 CPHA Clock phase
0: The first clock transition is the first data capture edge
1: The second clock transition is the first data capture edge
8 LBCL Last bit clock pulse
0: The clock pulse of the last data bit is not output to the SCLK pin
1: The clock pulse of the last data bit is output to the SCLK pin
7:5 NA Reserved, undefined
4 ADDM 7-bit Address Detection/4-bit Address Detection
0: 4-bit address detection
1: 7-bit address detection (in 8-bit data mode)
3:0 NA Reserved, undefined

26.3.3. Control register 3 (USARTx_CR3)

bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0


31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 DEP DEM DDRE OVRDIS ONEBIT CTSIE CTSE RTSE
type RW RW RW RW RW RW RW RW
7:0 DMAT DMAR — HDSEL — EIE
type RW RW RO-0 RO-0 RW RO-0 RO-0 RW

Bit Name Function


31:16 NA Reserved, undefined
15 DEP Driver enable polarity selection
0: DE signal is active high.

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Fremont Micro Devices FT32F0xxx8 RM

1: DE signal is active low.


14 DEM Driver enable mode
0: DE function is disabled.
1: DE function is enabled.
13 DDRE DMA Disable on Reception Error
0: DMA is not disabled in case of reception error.
1: DMA is disabled following a reception error. The DMA request is masked
until the error flags (parity error, framing error or noise error) are cleared.
12 OVRDIS Overrun Disable
0: Overrun functionality is enabled
1: Overrun functionality is disabled. If new data is received while the RXNE
flag is still set the ORE flag is not set and the new received data overwrites
the previous content of the USARTx_RDR register.
11 ONEBIT One sample bit method enable
0: Three sample bit method
1: One sample bit method
10 CTSIE CTS interrupt enable
0: CTS interrupt is disabled
1: CTS interrupt is enabled
9 CTSE CTS enable
0: CTS hardware flow control disabled
1: CTS mode enabled,
8 RTS RTS enable
0: RTS hardware flow control disabled
1: RTS output enabled
7 DMAT DMA enable transmitter
0: DMA mode is disabled for transmission
1: DMA mode is enabled for transmission
6 DMAR DMA enable receiver
0: DMA mode is disabled for reception
1: DMA mode is enabled for reception
5:4 NA Reserved, undefined
3 HDSEL Half-duplex selection
0: Half duplex mode is not selected
1: Half duplex mode is selected
2:1 NA Reserved, undefined
0 EIE Error interrupt enable
0: Error interrupt is disabled
1: Error interrupt is enabled. Erros include: parity error, framing error and
noise error.

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Fremont Micro Devices FT32F0xxx8 RM

26.3.4. Baud rate register (USARTx_BRR)

bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0


31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 BRR[15:8]
type RW RW RW RW RW RW RW RW
7:0 BRR[7:0]
type RW RW RW RW RW RW RW RW

Bit Name Function


31:16 NA Reserved, undefined
15:0 BRR Baud rate register
BRR[15:4]: Integer of USARTDIV
BRR[3:0]: Demicals of USARTDIV

26.3.5. Receiver timeout register (USARTx_RTOR)

bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0


31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 RTO[24:16]
type RW RW RW RW RW RW RW RW
15:8 RTO[15:8]
type RW RW RW RW RW RW RW RW
7:0 RTO[7:0]
type RW RW RW RW RW RW RW RW

Bit Name Function


31:24 NA Reserved, undefined
23:0 RTO Receiver timeout value, the unit is the length of baud rate clock

26.3.6. Request register (USARTx_RQR)

bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0


31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —

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Fremont Micro Devices FT32F0xxx8 RM

type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0


15:8 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
7:0 — TXFRQ RXFRQ MMRQ SBKRQ ABRRQ
type RO-0 RO-0 RO-0 W-R0 W-R0 W-R0 W-R0 W-R0

Bit Name Function


31:5 NA Reserved, undefined
4 TXFRQ Transmit data flush request
Writing 1 to this bit sets the TXE flag. This allows to discard the transmit data
3 RXFRQ Receive data flush request
Writing 1 to this bit clears the RXNE flag. This allows to discard the received
data
2 MMRQ Mute mode request
Writing 1 to this bit puts the USART in mute mode and sets the RWU flag
1 SBKRQ Send break request
Writing 1 to this bit sets the SBKF flag and request to send a BREAK on the
line, as soon as the transmit machine is available.
0 ABRRQ Auto baud rate request
Writing 1 to this bit resets the ABRF flag in the USARTx_ISR and request an
automatic baud rate measurement on the next received data frame.

26.3.7. Interrupt and status register (USARTx_ISR)

bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0


31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 — RWU SBKF CMF BUSY
type RO-0 RO-0 RO-0 RO-0 RO RO RO RO
15:8 ABRF ABRE — RTOF CTS CTSIF —
type RO RO RO-0 RO-0 RO RO RO RO-0
7:0 TXE TC RXNE IDLE ORE NF FE PE
type RO RO RO RO RO RO RO RO

Bit Name Function


31:18 NA Reserved, undefined
19 RWU Receiver wakeup from Mute mode
0: Receiver in active mode
1: Receiver in mute mode
18 SBKF Send break flag
0: No break character is transmitted

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Fremont Micro Devices FT32F0xxx8 RM

1: Break character will be transmitted, It is automatically reset by hardware


during the stop bit of break transmission.
17 CMF Character match flag
0: No Character match detected
1: Character Match detected (character defined by ADD[7:0] is received)
16 BUSY Busy flag
0: USART is idle (no reception)
1: Reception on going
15 ABRF Auto baud rate flag
1: Baud rate detected
0: No Baud rate detected
14 ABRE Auto baud rate error
0: The baud rate measurement succeed
1: The baud rate measurement failed. It is cleared by software, by writing 1
to the ABRRQ bit in the USARTx_CR3 register.
13:12 NA Reserved, undefined
11 RTOF Receiver timeout
1: Timeout value reached without any data reception
0: Reveiver timeout value not reached
10 CTS CTS flag
0: nCTS line set
1: nCTS line reset
9 CTSIF CTS interrupt flag
0: No change occurred on the nCTS status line
1: This bit is set by hardware when the nCTS input toggles, if the CTSE bit is
set.
8 NA Reserved, undefined
7 TXE Transmit data register empty
0: Transmit data register is empty
1: Transmit data register is not empty (data is transferred to the shift register)
6 TC Transmission complete, It is cleared by software, writing 1 to the TCCF in
the USARTx_ICR register or by a write to the USARTx_TDR register.
0: Transmission is not complete
1: Transmission is complete
5 RXNE Read data register not empty, It is cleared by a read to the USARTx_RDR
register.
0: data is not received
1: Received data is ready to be read.
4 IDLE Idle line detected, It is cleared by software, writing 1 to the IDLECF in
the USARTx_ICR register.
0: No Idle line is detected
1: Idle line is detected
3 ORE Overrun error, This bit is set by hardware when the data currently being

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Fremont Micro Devices FT32F0xxx8 RM

received in the shift register is ready to be transferred into the RDR register
while RXNE=1. It is cleared by a software, writing 1 to the ORECF, in the
USARTx_ICR register.
0: No overrun error
1: Overrun error is detected
2 NF Noise detection flag
0: No noise is detected
1: Noise is detected
1 FE Framing error, It is cleared by software, writing 1 to the FECF bit in the
USARTx_ICR register.
0: No Framing error is detected
1: Framing error or break character is detected
0 PE Parity error
It is cleared by software, writing 1 to the PECF in the USARTx_ICR register.
0: No parity error
1: Parity error

26.3.8. Interrupt flag clear register (USARTx_ICR)

Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0


31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 — CMCF —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 W-R0 RO-0
15:8 — RTOCF — CTSCF LBDCF
type RO-0 RO-0 RO-0 RO-0 W-R0 RO-0 W-R0 W-R0
7:0 — TCCF — IDLECF ORECF NCF FECF PECF
type RO-0 W-R0 RO-0 W-R0 W-R0 W-R0 W-R0 W-R0

Bit Name Function


31:18 NA Reserved, undefined
17 CMCF Character match clear flag
Writing 1 to this bit clears the CMF flag in the USARTx_ISR register.
16:12 NA Reserved, undefined
11 RTOCF Receiver timeout clear flag
Writing 1 to this bit clears the RTOF flag in the USARTx_ISR register.
10 NA Reserved, undefined
9 CTSCF CTS clear flag
Writing 1 to this bit clears the CTSIF flag in the USARTx_ISR register.
8 LBDCF LIN break detection clear flag
Writing 1 to this bit clears the LBDF flag in the USARTx_ISR register.
7 NA Reserved, undefined

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Fremont Micro Devices FT32F0xxx8 RM

6 TCCF Transmission complete clear flag


Writing 1 to this bit clears the TC flag in the USARTx_ISR register
5 NA Reserved, undefined
4 IDLECF Idle line detected clear flag
Writing 1 to this bit clears the IDLE flag in the USARTx_ISR register.
3 ORECF Overrun error clear flag
Writing 1 to this bit clears the ORE flag in the USARTx_ISR register
2 NCF Noise detected clear flag
Writing 1 to this bit clears the NF flag in the USARTx_ISR register
1 FECF Framing error clear flag
Writing 1 to this bit clears the FE flag in the USARTx_ISR register
0 PECF Parity error clear flag
Writing 1 to this bit clears the PE flag in the USARTx_ISR register.

26.3.9. Receive data register (USARTx_RDR)

bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0


31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 — RDR[8]
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO
7:0 RDR[7:0]
type RO

Bit Name Function


31:9 NA Reserved, undefined
8:0 RDR Receive data value

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26.3.10. Transmit data register (USARTx_TDR)

bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0


31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 — TDR[8]
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RW
7:0 TDR[7:0]
type RW

Bit Name Function


31:9 NA Reserved, undefined
8:0 TDR Transmit data value

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27. Serial peripheral interface(SPI)

27.1. Introduction

The SPI interface can be used to communicate with external devices using the SPI protocol. SPI mode is
selectable by software. SPI Motorola mode is selected by default after a device reset.
The serial peripheral interface (SPI) protocol supports half-duplex, full-duplex and simplex synchronous,
serial communication with external devices. The interface can be configured as master and in this case it
provides the communication clock (SCK) to the external slave device. The interface is also capable of
operating in multimaster configuration.

27.2. SPI main features

 Master or slave operation


 Full-duplex synchronous transfers on three lines
 Half-duplex synchronous transfer on two lines (with bidirectional data line)
 Simplex synchronous transfers on two lines (with unidirectional data line)
 4-bit to 16-bit data size selection
 Multimaster mode capability
 8 master mode baud rate prescalers up tofPCLK /2
 Slave mode frequency up tofPCLK /2, configurable max speed.
 NSS management by hardware or software for both master and slave: dynamic change of master/slave
operations
 Programmable clock polarity and phase
 Programmable data order with MSB-first or LSB-first shifting
 Dedicated transmission and reception flags with interrupt capability
 SPI bus busy status flag
 SPI Motorola support
 Hardware CRC feature for reliable communication:
− CRC value can be transmitted as last byte in Tx mode
− Automatic CRC error checking for last received byte
 Master mode fault, overrun flags with interrupt capability
 CRC Error flag
 Two 32-bit embedded Rx and Tx FIFOs with DMA capability
 SPI TI mode support

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27.3. SPI functional description

27.3.1. SPI functional description

The SPI allows synchronous, serial communication between the MCU and external devices. Application
software can manage the communication by polling the status flag or using dedicated SPI interrupt. The
main elements of SPI and their interactions are shown in the following block diagram Figure 27-1.

GPIO

NSS Baud Rate


Logic Generator

Shifter

Tx Shifter Rx Shifter
CRC

Rx Control
Communication
Controller
Tx Control TxFIFO Controller RxFIFO Controller

SPI_TXCRCR
TxFIFO RxFIFO
BUS

APB Interface

INT_CTRL NVIC
Register File

DMA DMA
Controller

Figure 27-1 SPI block diagram

Four I/O pins are dedicated to SPI communication with external devices.
 MISO: Master In / Slave Out data. In the general case, this pin is used to transmit data in slave mode
and receive data in master mode.
 MOSI: Master Out / Slave In data. In the general case, this pin is used to transmit data in master mode
and receive data in slave mode.
 SCK: Serial Clock output pin for SPI masters and input pin for SPI slaves.
 NSS: Slave select pin. Depending on the SPI and NSS settings, this pin can be used to either:
− select an individual slave device for communication
− synchronize the data frame
− detect a conflict between multiple masters

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See Section 24.3.4: Slave select (NSS) pin management for details.
The SPI bus allows the communication between one master device and one or more slave devices. The bus
consists of at least two wires –one for the clock signal and the other for synchronous data transfer. Other
signals can be added depending on the data exchange between SPI nodes and their slave select signal
management.

27.3.2. Communications between one master and one slave

The SPI allows the MCU to communicate using different configurations, depending on the device targeted
and the application requirements. These configurations use 2 or 3 wires (with software NSS management)
or 3 or 4 wires (with hardware NSS management). Communication is always initiated by the master.

Full-duplex communication
By default, the SPI is configured for full-duplex communication. In this configuration, the shift registers of the
master and slave are linked using two unidirectional lines between the MOSI and the MISO pins. During SPI
communication, data is shifted synchronously on the SCK clock edges provided by the master. The master
transmits the data to be sent to the slave via the MOSI line and receives data from the slave via the MISO
line. When the data frame transfer is complete (all the bits are shifted) the information between the master
and slave is exchanged.

MISO MISO
Shift register Shift register

MOSI MOSI

SPI clock SCK SCK


generator

NSS(1) NSS(1)
Vcc Slave
Master

Figure 27-2 Full-duplex single master/ single slave application


1. The NSS pin is configured as an input in this case.

Half-duplex communication
The SPI can communicate in half-duplex mode by setting the BIDIMODE bit in the SPIx_CR1 register. In this
configuration, one single cross connection line is used to link the shift registers of the master and slave
together. During this communication, the data is synchronously shifted between the shift registers on the
SCK clock edge in the transfer direction selected reciprocally by both master and slave with the BDIOE bit in
their SPIx_CR1 registers. In this configuration, the master’s MISO pin and the slave’s MOSI pin are free for
other application uses and act as GPIOs.

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MISO(2) MISO
Shift register Shift register

MOSI MOSI(2)

SPI clock SCK SCK


generator

NSS(1) NSS(1)
Vcc Slave
Master

Figure 27-3 Half-duplex single master/ single slave application


1. The NSS pin is configured as an input in this case
2. In this configuration, the master’s MISO pin and the slave’s MOSI pin can be used as GPIOs.

Simplex communications
The SPI can communicate in simplex mode by setting the SPI in transmit-only or in receive- only using the
RXONLY bit in the SPIx_CR2 register. In this configuration, only one line is used for the transfer between the
shift registers of the master and slave. The remaining MISO and MOSI pins pair is not used for
communication and can be used as standard GPIOs.
 Transmit-only mode (RXONLY=0): The configuration settings are the same as for full-duplex. The
application has to ignore the information captured on the unused input pin. This pin can be used as a
standard GPIO.
 Receive-only mode (RXONLY=1): The application can disable the SPI output function by setting the
RXONLY bit. In slave configuration, the MISO output is disabled and the pin can be used as a GPIO.
The slave continues to receive data from the MOSI pin while its slave select signal is active Received
data events appear depending on the data buffer configuration. In the master configuration, the MOSI
output is disabled and the pin can be used as a GPIO. The clock signal is generated continuously as
long as the SPI is enabled. The only way to stop the clock is to clear the RXONLY bit or the SPE bit and
wait until the incoming pattern from the MISO pin is finished and fills the data buffer structure,
depending on its configuration.

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(2) MISO MISO


Shift register Shift register

MOSI MOSI

SPI clock SCK SCK


generator

NSS(1) NSS(1)
Vcc Slave
Master

Figure 27-4 Simplex single master/single slave application (master in transmit-only/slave in receive-only
mode)
1. The NSS pin is configured as an input in this case.
2. The input information is captured in the shift register and must be ignored in standard transmit only
mode (for example, OVF flag)
3. In this configuration, both the MISO pins can be used as GPIOs.
Note: Any simplex communication can be alternatively replaced by a variant of the half duplex
communication with a constant setting of the transaction direction

27.3.3. Standard multi-slave communication

In a configuration with two or more independent slaves, the master uses GPIO pins to manage the chip
select lines for each slave. The master must select one of the slaves individually by pulling low the GPIO
connected to the slave NSS input. When this is done, a standard master and dedicated slave
communication is established.

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MISO MISO
Shift register Shift register

MOSI MOSI

SPI clock SCK SCK


generator
I/O 1 NSS
Master I/O 2 Slave 1
I/O 3

MISO
Shift register

MOSI

SCK

NSS
Slave 2

MISO
Shift register

MOSI

SCK

NSS
Slave 3

Figure 27-5 Master and three independent slaves


Note: As MISO pins of the slaves are connected together, all slaves must have the GPIO configuration of
their MISO pin set as alternate function open-drain

27.3.4. Slave select (NSS) pin management

In slave mode, the NSS works as a standard “chip select” input and lets the slave communicate with the
master. In master mode, NSS can be used either as output or input. As an input it can prevent multimaster
bus collision, and as an output it can drive a slave select signal of a single slave.
Hardware or software slave select management can be set using the SSM bit in the SPIx_CR1 register:
 Software NSS management (SSM = 1): in this configuration, slave select information is driven internally
by the SSI bit value in register SPIx_CR1. The external NSS pin is free for other application uses.
 Hardware NSS management (SSM = 0): in this case, there are two possible configurations. The
configuration used depends on the NSS output configuration (SSOE bit in register SPIx_CR1).

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− NSS output enable (SSM=0,SSOE = 1): this configuration is only used when the MCU is set as
master. The NSS pin is managed by the hardware. The NSS signal is driven low as soon as the
SPI is enabled in master mode (SPE=1), and is kept low until the SPI is disabled (SPE =0). A pulse
can be generated between continuous communications if NSS pulse mode is activated (NSSP=1).
The SPI cannot work in multimaster configuration with this NSS setting.
− NSS output disable (SSM=0, SSOE = 0): if the microcontroller is acting as the master on the bus,
this configuration allows multimaster capability. If the NSS pin is pulled low in this mode, the SPI
enters master mode fault state and the device is automatically reconfigured in slave mode. In slave
mode, the NSS pin works as a standard “chip select” input and the slave is selected while NSS line
is at low level.

SSI control bit

SSM control bit

NSS Input

NSS GPIO
pin logic

NSS NSS Output


Output
(used in Master mode and NSS
Control HW management only)

SSOE control bit


NSS external
NSS interal logic
logic

Figure 27-6 Hardware/software slave select management

27.3.5. Communication formats

During SPI communication, receive and transmit operations are performed simultaneously. The serial clock
(SCK) synchronizes the shifting and sampling of the information on the data lines. The communication
format depends on the clock phase, the clock polarity and the data frame format. To be able to communicate
together, the master and slaves devices must follow the same communication format.

Clock phase and polarity controls


Four possible timing relationships may be chosen by software, using the CPOL and CPHA bits in the
SPIx_CR1 register. The CPOL (clock polarity) bit controls the idle state value of the clock when no data is
being transferred. This bit affects both master and slave modes. If CPOL is reset, the SCK pin has a
low-level idle state. If CPOL is set, the SCK pin has a high-level idle state.
If the CPHA bit is set, the second edge on the SCK pin captures the first data bit transacted (falling edge if
the CPOL bit is reset, rising edge if the CPOL bit is set). Data are latched on each occurrence of this clock
transition type. If the CPHA bit is reset, the first edge on the SCK pin captures the first data bit transacted

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(falling edge if the CPOL bit is set, rising edge if the CPOL bit is reset). Data are latched on each occurrence
of this clock transition type.
The combination of CPOL (clock polarity) and CPHA (clock phase) bits selects the data capture clock edge.
Figure 27-7 shows an SPI full-duplex transfer with the four combinations of the CPHA and CPOL bits.
Note1: Prior to changing the CPOL/CPHA bits the SPI must be disabled by resetting the SPE bit.
Note2: The idle state of SCK must correspond to the polarity selected in the SPIx_CR1 register (by
pulling up SCK if CPOL=1 or pulling down SCK if CPOL=0).

CPOL=1

CPOL=0

MOSI(1) MSBit LSBit

MISO(1) MSBit LSBit

NSS(to slave)

CPHA=1

CPOL =1

CPOL =0

MOSI (1) MSBit LSBit

MISO (1) MSBit LSBit

NSS (to slave)

CPHA=0

Figure 27-7 Data clock timing diagram


1. The order of data bits depends on LSBFIRST bit setting.

Data frame format


The SPI shift register can be set up to shift out MSB-first or LSB-first, depending on the value of the
LSBFIRST bit. The data frame size is chosen by using the DS bits. It can be set from 4-bit up to 16-bit length
and the setting applies for both transmission and reception. Whatever the selected data frame size, read
access to the FIFO must be aligned with the FRXTH level. When the SPIx_DR register is accessed, data
frames are always right-aligned into either a byte (if the data fits into a byte) or a half-word During
communication, only bits within the data frame are clocked and transferred.

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DS<=8 bits: data is right-aligned on byte DS>8 bits: data is right-aligned on 16 bit
Example: DS=5 bit Example: DS=14 bit

7 54 0 15 14 13 0
xxx Data frame TX xx Data frame TX

7 54 0 15 14 13 0
000 Data frame RX 00 Data frame RX

Figure 27-8 Data alignment when data length is not equal to 8-bit or 16-bit
Note:The minimum data length is 4 bits. If a data length of less than 4 bits is selected, it is forced to an 8-bit
data frame size.

27.3.6. Configuration of SPI

The configuration procedure is almost the same for master and slave. For specific mode setups, follow the
dedicated chapters. When a standard communication is to be initialized, perform these steps:
1. Write proper GPIO registers: Configure GPIO for MOSI, MISO and SCK pins.
2. Write to the SPI_CR1 register:
a) Configure the serial clock baud rate using the BR[2:0] bits (Note: 4).
b) Configure the CPOL and CPHA bits combination to define one of the four relationships between the
data transfer and the serial clock (CPHA must be cleared in NSSP mode). (Note: 2).
c) Select simplex or half-duplex mode by configuring RXONLY or BIDIMODE and BIDIOE (RXONLY
and BIDIMODE can’t be set at the same time).
d) Configure the LSBFIRST bit to define the frame format (Note: 2).
e) Configure the CRCL and CRCEN bits if CRC is needed (while SCK clock signal is at idle state).
f) Configure SSM and SSI (Note: 2 & 3).
g) Configure the MSTR bit (in multimaster NSS configuration, avoid conflict state on NSS if master is
configured to prevent MODF error).
3. Write to SPI_CR2 register:
a) Configure the DS[3:0] bits to select the data length for the transfer.
b) Configure SSOE (Note: 1 & 2 & 3).
c) Set the FRF bit if the TI protocol is required (keep NSSP bit cleared in TI mode).
d) Set the NSSP bit if the NSS pulse mode between two data units is required (keep CHPA and
FRFbits cleared in NSSP mode).
e) Configure the FRXTH bit. The RXFIFO threshold must be aligned to the read access size for the
SPIx_DR register.
f) Initialize LDMA_TX and LDMA_RX bits if DMA is used in packed mode.
4. Write to SPI_CRCPR register: Configure the CRC polynomial if needed.
5. Write proper DMA registers: Configure DMA streams dedicated for SPI Tx and Rx in DMA registers if the
DMA streams are used.
Note:

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(1) Step is not required in slave mode


(2) Step is not required in TI mode.
(3) Step is not required in NSSP mode.
(4) The step is not required in slave mode except slave working at TI mode

27.3.7. Procedure for enabling SPI

It is recommended to enable the SPI slave before the master sends the clock. If not, undesired data
transmission might occur. The data register of the slave must already contain data to be sent before starting
communication with the master (either on the first edge of the communication clock, or before the end of the
ongoing communication if the clock signal is continuous). The SCK signal must be settled at an idle state
level corresponding to the selected polarity before the SPI slave is enabled.
The master at full duplex (or in any transmit-only mode) starts to communicate when the SPI is enabled and
TXFIFO is not empty, or with the next write to TXFIFO.
In any master receive only mode (RXONLY=1 or BIDIMODE=1 & BIDIOE=0), master starts to communicate
and the clock starts running immediately after SPI is enabled.

27.3.8. Data transmission and reception procedures

RXFIFO and TXFIFO


All SPI data transactions pass through the 32-bit embedded FIFOs. This enables the SPI to work in a
continuous flow, and prevents overruns when the data frame size is short. Each direction has its own FIFO
called TXFIFO and RXFIFO.
The handling of FIFOs depends on the data exchange mode (duplex, simplex), data frame format (number
of bits in the frame), access size performed on the FIFO data registers (8-bit or 16-bit), and whether or not
data packing is used when accessing the FIFOs
A read access to the SPIx_DR register returns the oldest value stored in RXFIFO that has not been read yet.
A write access to the SPIx_DR stores the written data in the TXFIFO at the end of a send queue. The read
access must be always aligned with the RXFIFO threshold configured by the FRXTH bit in SPIx_CR2
register. FTLVL[1:0] and FRLVL[1:0] bits indicate the current occupancy level of both FIFOs.
A read access to the SPIx_DR register must be managed by the RXNE event. This event is triggered when
data is stored in RXFIFO and the threshold (defined by FRXTH bit) is reached. When RXNE is cleared,
RXFIFO is considered to be empty. In a similar way, write access of a data frame to be transmitted is
managed by the TXE event. This event is triggered when the TXFIFO level is less than or equal to half of its
capacity. Otherwise TXE is cleared and the TXFIFO is considered as full. In this way, RXFIFO can store up
to four data frames, whereas TXFIFO can only store up to three when the data frame format is not greater
than 8 bits. This difference prevents possible corruption of 3x 8-bit data frames already stored in the TXFIFO
when software tries to write more data in 16-bit mode into TXFIFO. Both TXE and RXNE events can be
polled or handled by interrupts.
Another way to manage the data exchange is to use DMA
If the next data is received when the RXFIFO is full, an overrun event occurs. An overrun event can be
polled or handled by an interrupt.

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The BSY bit being set indicates ongoing transaction of a current data frame. When the clock signal runs
continuously, the BSY flag stays set between data frames at master but becomes low for a minimum
duration of one SPI clock at slave between each data frame transfer..

Sequence handling
A few data frames can be passed at single sequence to complete a message. When transmission is enabled,
a sequence begins and continues while any data is present in the TXFIFO of the master. The clock signal is
provided continuously by the master until TXFIFO becomes empty, then it stops waiting for additional data.
In receive-only modes, half duplex (BIDIMODE=1, BIDIOE=0) or simplex (BIDIMODE=0, RXONLY=1) the
master starts the sequence immediately when both SPI is enabled and receive-only mode is activated. The
clock signal is provided by the master and it does not stop until either SPI or receive-only mode is disabled
by the master. The master receives data frames continuously up to this moment.
While the master can provide all the transactions in continuous mode (SCK signal is continuous) it has to
respect slave capability to handle data flow and its content at anytime. When necessary, the master must
slow down the communication and provide either a slower clock or separate frames or data sessions with
sufficient delays. Be aware there is no underflow error signal for master or slave in SPI mode, and data from
the slave is always transacted and processed by the master even if the slave could not prepare it correctly in
time. It is preferable for the slave to use DMA, especially when data frames are shorter and bus rate is high.
Each sequence must be encased by the NSS pulse in parallel with the multislave system to select just one
of the slaves for communication. In a single slave system it is not necessary to control the slave with NSS,
but it is often better to provide the pulse here too, to synchronize the slave with the beginning of each data
sequence. NSS can be managed by both software and hardware.
When the BSY bit is set it signifies an ongoing data frame transaction. Reading BSY status together with
FTLVL[1:0] to check if a transmission is fully completed, which is necessary before the system enter HALT.
Entering HALT before transmission completed might cause the data damaged. Checking BSY status also
can used for NSS pin management. When the dedicated frame transaction is finished, the RXNE flag is
raised. The last bit is just sampled and the complete data frame is stored in the RXFIFO.

Procedure for disabling the SPI


When SPI is disabled, it is mandatory to follow the disable procedures described in this paragraph. It is
important to do this before the system enters a low-power mode when the peripheral clock is stopped.
Ongoing transactions can be corrupted in this case. In some modes the disable procedure is the only way to
stop continuous communication running.
Master can finish any transaction when it stops providing data for transmission. In this case, the clock stops
after the last data transaction. Special care must be taken in packing mode when an odd number of data
frames are transacted to prevent some dummy byte exchange (refer to Data packing section). Before the
SPI is disabled in these modes, the user must follow standard disable procedure. When the SPI is disabled
at the master transmitter while a frame transaction is ongoing or next data frame is stored in TXFIFO, the
SPI behavior is not guaranteed.
When the master is in any receive only mode, the only way to stop the continuous clock is to disable the
peripheral by SPE=0. This must occur in specific time window within last data frame transaction just
between the sampling time of its first bit and before its last bit transfer starts (in order to receive a complete
number of expected data frames and to prevent any additional “dummy” data reading after the last valid data

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frame). Specific procedure must be followed when disabling SPI in this mode.
Data received but not read remains stored in RXFIFO when the SPI is disabled, and must be processed the
next time the SPI is enabled, before starting a new sequence. To prevent having unread data, ensure that
RXFIFO is empty when disabling the SPI, by using the correct disabling procedure, or by initializing all the
SPI registers with a software reset via the control of a specific register dedicated to peripheral reset (see the
SPIiRST bits in the RCC_APBiRSTR registers).
Standard disable procedure is based on pulling BSY status together with FTLVL[1:0] to check if a
transmission session is fully completed. This check can be done in specific cases, too, when it is necessary
to identify the end of ongoing transactions, for example:
 When NSS signal is managed by software and master has to provide proper end of NSS pulse for slave
 When transactions’ streams from DMA or FIFO are completed while the last data frame or CRC frame
transaction is still ongoing in the peripheral bus.
The correct disable procedure is (except when receive only mode is used):
1. Wait until FTLVL[1:0] = 00 (no more data to transmit).
2. Wait until BSY=0 (the last data frame is processed).
3. Disable the SPI (SPE=0).
4. Read data until FRLVL[1:0] = 00 (read all the received data).
The correct disable procedure for certain receive only modes is:
1. Interrupt the receive flow by disabling SPI (SPE=0) in the specific time window while the last data frame
is ongoing.
2. Wait until BSY=0 (the last data frame is processed).
3. Read data until FRLVL[1:0] = 00 (read all the received data).
Note: If packing mode is used and an odd number of data frames with a format less than or equal to 8 bits
(fitting into one byte) has to be received, FRXTH must be set when FRLVL[1:0] = 01, in order to generate the
RXNE event to read the last odd data frame

Data packing
When the data frame size fits into one byte (less than or equal to 8 bits), data packing is used automatically
when any read or write 16-bit access is performed on the SPIx_DR register. The double data frame pattern
is handled in parallel in this case. At first, the SPI operates using the pattern stored in the LSB of the
accessed word, then with the other half stored in the MSB.
Figure 27-9 provides an example of data packing mode sequence handling. Two data frames are sent after
the single 16-bit access the SPIx_DR register of the transmitter. This sequence can generate just one RXNE
event in the receiver if the RXFIFO threshold is set to 16 bits (FRXTH=0). The receiver then has to access
both data frames by a single 16-bit read of SPIx_DR as a response to this single RXNE event. The RxFIFO
threshold setting and the following read access must be always kept aligned at the receiver side, as data
can be lost if it is not in line.
A specific problem appears if an odd number of such “fit into one byte” data frames must be handled. On the
transmitter side, writing the last data frame of any odd sequence with an 8- bit access to SPIx_DR is enough.
The receiver has to change the Rx_FIFO threshold level for the last data frame received in the odd
sequence of frames in order to generate the RXNE event.

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0x0A 0x0A 0x04 0x0A


0x04 0x0A 0x04 SPI fsm SPI fsm 0x04 0x04 0x0A
& shfit & shfit

16-bit access when write to data register 16-bit access when read from data register
SPI_DR =0x040A when TXE=1 SPI_DR =0x040A when RXNE=1

Figure 27-9 Packing data in FIFO for transmission and reception

Communication using DMA (direct memory addressing)


To operate at its maximum speed and to facilitate the data register read/write process required to avoid
overrun, the SPI features a DMA capability, which implements a simple request/acknowledge protocol.
A DMA access is requested when the TXE or RXNE enable bit in the SPIx_CR2 register is set. Separate
requests must be issued to the Tx and Rx buffers.
 In transmission, a DMA request is issued each time TXE is set to 1. The DMA then writes to the
SPIx_DR register.
 In reception, a DMA request is issued each time RXNE is set to 1. The DMA then reads the SPIx_DR
register.
When the SPI is used only to transmit data, it is possible to enable only the SPI Tx DMA channel. In this
case, the OVR flag is set because the data received is not read. When the SPI is used only to receive data,
it is possible to enable only the SPI Rx DMA channel.
In transmission mode, when the DMA has written all the data to be transmitted (the TCIF flag is set in the
DMA_ISR register), the BSY flag can be monitored to ensure that the SPI communication is complete. This
is required to avoid corrupting the last transmission before disabling the SPI or entering the Stop mode. The
software must first wait until FTLVL[1:0]=00 and then until BSY=0.
When starting communication using DMA, to prevent DMA channel management raising error events, these
steps must be followed in order:
1. Enable DMA Rx buffer in the RXDMAEN bit in the SPI_CR2 register, if DMA Rx is used.
2. Enable DMA streams for Tx and Rx in DMA registers, if the streams are used
3. Enable DMA Tx buffer in the TXDMAEN bit in the SPI_CR2 register, if DMA Tx is used.
4. Enable the SPI by setting the SPE bit.
To close communication it is mandatory to follow these steps in order:
1. Disable DMA streams for Tx and Rx in the DMA registers, if the streams are used.
2. Disable the SPI by following the SPI disable procedure.
3. Disable DMA Tx and Rx buffers by clearing the TXDMAEN and RXDMAEN bits in the SPI_CR2 register,
if DMA Tx and/or DMA Rx are used.

Packing with DMA


If the transfers are managed by DMA (TXDMAEN and RXDMAEN set in the SPIx_CR2 register) packing
mode is enabled/disabled automatically depending on the PSIZE value configured for SPI TX and the SPI
RX DMA channel. If the DMA channel PSIZE value is equal to 16-bit and SPI data size is less than or equal
to 8-bit, then packing mode is enabled. The DMA then automatically manages the write operations to the

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SPIx_DR register.
If data packing mode is used and the number of data to transfer is not a multiple of two, the
LDMA_TX/LDMA_RX bits must be set. The SPI then considers only one data for the transmission or
reception to serve the last DMA transfer

Communication diagrams
Some typical timing schemes are explained in this section. These schemes are valid no matter if the SPI
events are handled by pulling, interrupts or DMA. For simplicity, the LSBFIRST=0, CPOL=0 and CPHA=1
setting is used as a common assumption here. No complete configuration of DMA streams is provided.
The following numbered notes are common for Figure 27-10 and Figure 27-11.
1. The slave starts to control MISO line as NSS is active and SPI is enabled, and is disconnected from the
line when one of them is released. Sufficient time must be provided for the slave to prepare data
dedicated to the master in advance before its transaction starts.
2. At the master, BSY stays active between frames if the communication (clock signal) is continuous. At the
slave, BSY signal always goes down for at least one clock cycle between data frames.
3. The TXE signal is cleared only if TXFIFO is full.
4. The DMA arbitration process starts just after the TXDMAEN bit is set. The TXE interrupt is generated
just after the TXEIE is set. As the TXE signal is at an active level, data transfers to TxFIFO start, until
TxFIFO becomes full or the DMA transfer completes.
5. If all the data to be sent can fit into TxFIFO, the DMA Tx TCIF flag can be raised even before
communication on the SPI bus starts. This flag always rises before the SPI transaction is completed.
6. The CRC value for a package is calculated continuously frame by frame. Continuously frame by frame
in the SPIx_TxCRCR and SPIx_RxCRCR registers. The CRC information is processed after the entire
data package has completed, either automatically by DMA (Tx channel must be set to the number of
data frames to be processed) or by SW (the user must handle CRCNEXT bit during the last data frame
processing).
While the CRC value calculated in SPIx_TxCRCR is simply sent out by transmitter, received CRC
information is loaded into RxFIFO and then compared with the SPIx_RxCRCR register content (CRC
error flag can be raised here if any difference). This is why the user must take care to flush this
information from the FIFO, either by software reading out all the stored content of RxFIFO, or by DMA
when the proper number of data frames is preset for Rx channel (number of data frames + number of
CRC frames) (see the settings at the example assumption).
7. In data packed mode, TxE and RxNE events are paired and each read/write access to the FIFO is 16
bits wide until the number of data frames are even. If the TxFIFO is ¾ full FTLVL status stays at FIFO full
level. That is why the last odd data frame cannot be stored before the TxFIFO becomes ½ full. This
frame is stored into TxFIFO with an 8- bit access either by software or automatically by DMA when
LDMA_TX control is set.
8. To receive the last odd data frame in packed mode, the Rx threshold must be changed to 8-bit when the
last data frame is processed, either by software setting FRXTH=1 or automatically by a DMA internal
signal when LDMA_RX is set.

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Fremont Micro Devices FT32F0xxx8 RM

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
NSS

SCK

BSY
2 2
MOSI MSB DTx1 MSB DTx2 MSB DTx3

SPE

TXE 3 3

Enable Tx/Rx DMA or interrupts

DTx1 DTx2 DTx3 DMA or software control at Tx events

FTLVL 10 11 10 11 10 00

4
MISO DTx1 LSB DTx2 LSB DTx3 LSB

RXN
1
E
DMA or software control at Rx events DTx1 DTx2 DTx3

FRLVL 00 10 00 10 00 10 00

DMA Rx
DMA Tx TICF 5 TICF

Figure 27-10 Master full duplex communication


Assumptions for master full duplex communication example:
 Data size > 8 bit
If DMA is used:
 Number of Tx frames transacted by DMA is set to 3
 Number of Rx frames transacted by DMA is set to 3

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Fremont Micro Devices FT32F0xxx8 RM

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
NSS

SCK

BSY 2

MOSI MSB DTx1 MSB DTx2 MSB DTx3


1
SPE 1

TXE 3 3

4 Enable Tx/Rx DMA or interrupts

DTx1 DTx2 DTx3 DMA or software control at Tx events

FTLVL 10 11 10 11 10 00

MISO DTx1 LSB DTx2 LSB DTx3 LSB

RXNE

DMA or software control at Rx events DTx1 DTx2 DTx3

FRLVL 00 10 00 10 00 10 00

DMA Rx
DMA Tx TICF 5 TICF

Figure 27-11 Slave full duplex communication


Assumptions for slave full duplex communication example:
 Data size > 8 bit
If DMA is used:
 Number of Tx frames transacted by DMA is set to 3
 Number of Rx frames transacted by DMA is set to 3

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Fremont Micro Devices FT32F0xxx8 RM

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
NSS

SCK

BSY 2

MOSI MSB DTx1 MSB DTx2 MSB CRC

SPE

TXE 3

Enable Tx/Rx DMA or interrupts

DTx1 DTx2 DMA or software control at Tx events

FTLVL 10 11 10 00

4
MISO DTx1 LSB DTx2 LSB CRC LSB

1 1
RXNE

DMA or software control at Rx events DTx1 DTx2 DTx3

FRLVL 00 10 00 10 00 10 00

DMA Rx
DMA Tx TICF 5 TICF 6

Figure 27-12 Master full duplex communication with CRC


Assumptions for master full duplex communication with CRC example:
 Data size = 16 bit
 CRC enabled
If DMA is used:
 Number of Tx frames transacted by DMA is set to 2
 Number of Rx frames transacted by DMA is set to 3

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Fremont Micro Devices FT32F0xxx8 RM

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
NSS

SCK

BSY 2
DRx12 DRx34 DRx5
MOSI 5 4 3 2 1 5 4 3 2 1 5 4 3 2 1 5 4 3 2 1 5 4 3 2 1

SPE

TXE 3 3

Enable Tx/Rx DMA or interrupts

DTx12 DTx34 DTx5 DMA or software control at Tx events


7
FTLVL 10 11 10 11 10 01 00

4
MISO 5 4 3 2 1 5 4 3 2 1 5 4 3 2 1 5 4 3 2 1 5 4 3 2 1

1 DRx12 DRx34 DRx5 1


RXNE

DMA or software control at Rx events DTx12 DTx34 FRXTH=1 DTx5


8
FRLVL 00 01 10 00 01 10 00 01 00

DMA Rx
DMA Tx TICF 5 TICF

Figure 27-13 Master full duplex communication in packed mode


Assumptions for master full duplex communication in packed mode example:
 Data size = 5 bit
 Read/write FIFO is performed mostly by 16-bit access
 FRXTH=0
If DMA is used:
 Number of Tx frames to be transacted by DMA is set to 3
 Number of Rx frames to be transacted by DMA is set to 3
 PSIZE for both Tx and Rx DMA channel is set to 16-bit
 LDMA_TX=1 and LDMA_RX=1

27.3.9. SPI status flags

Three status flags are provided for the application to completely monitor the state of the SPI bus.

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Fremont Micro Devices FT32F0xxx8 RM

Tx buffer empty flag(TXE)


The TXE flag is set when transmission TXFIFO has enough space to store data to send. TXE flag is linked
to the TXFIFO level. The flag goes high and stays high until the TXFIFO level is lower or equal to 1/2 of the
FIFO depth. An interrupt can be generated if the TXEIE bit in the SPIx_CR2 register is set. The bit is cleared
automatically when the TXFIFO level becomes greater than 1/2.

Rx buffer not empty (RXNE)


The RXNE flag is set depending on the FRXTH bit value in the SPIx_CR2 register:
 If FRXTH is set, RXNE goes high and stays high until the RXFIFO level is greater or equal to 1/4 (8-bit).
 If FRXTH is cleared, RXNE goes high and stays high until the RXFIFO level is greater than or equal to
1/2 (16-bit).
An interrupt can be generated if the RXNEIE bit in the SPIx_CR2 register is set. The RXNE is cleared by
hardware automatically when the above conditions are no longer true.

Busy flag(BSY)
The BSY flag is set and cleared by hardware (writing to this flag has no effect).
When BSY is set, it indicates that a data transfer is in progress on the SPI (the SPI bus is busy).
The BSY flag can be used in certain modes to detect the end of a transfer so that the software can disable
the SPI or its peripheral clock before entering a HALT mode. This avoids corrupting the last transfer.
The BSY flag is also useful for preventing write collisions in a multimaster system.
The BSY flag is cleared under any one of the following conditions
 When the SPI is correctly disabled
 When a fault is detected in Master mode (MODF bit set to 1)
 In Master mode, when it finishes a data transmission and no new data is ready to be sent
 In Slave mode, when the BSY flag is set to ‘0’ for at least one SPI clock cycle between each data
transfer.
Note: When the next transmission can be handled immediately by the master (e.g. if the master is in
Receive-only mode or its Transmit FIFO is not empty), communication is continuous and the BSY flag
remains set to ‘1’ between transfers on the master side. Although this is not the case with a slave, it is
recommended to use always the TXE and RXNE flags (instead of the BSY flags) to handle data
transmission or reception operations.

27.3.10. SPI error flags

An SPI interrupt is generated if one of the following error flags is set and interrupt is enabled by setting the
ERRIE bit.

Overrun flag(OVR)
An overrun condition occurs when data is received by a master or slave and the RXFIFO has not enough
space to store this received data. This can happen if the software or the DMA did not have enough time to
read the previously received data (stored in the RXFIFO) or when space for data storage is limited. E.g. the
RXFIFO is not available when CRC is enabled in receive only mode so in this case the reception buffer is
limited into a single data frame buffer

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Fremont Micro Devices FT32F0xxx8 RM

When an overrun condition occurs, the newly received value does not overwrite the previous one in the
RXFIFO. The newly received value is discarded and all data transmitted subsequently is lost. Clearing the
OVR bit is done by a read access to the SPI_DR register followed by a read access to the SPI_SR register.

Mode fault(MODF)
Mode fault occurs when the master device has its internal NSS signal (NSS pin in NSS hardware mode, or
SSI bit in NSS software mode) pulled low. This automatically sets the MODF bit. Master mode fault affects
the SPI interface in the following ways:
 The MODF bit is set and an SPI interrupt is generated if the ERRIE bit is set.
 The SPE bit is cleared. This blocks all output from the device and disables the SPI interface.
 The MSTR bit is cleared, thus forcing the device into slave mode.
Use the following software sequence to clear the MODF bit:
1. Make a read or write access to the SPIx_SR register while the MODF bit is set.
2. Then write to the SPIx_CR1 register.
To avoid any multiple slave conflicts in a system comprising several MCUs, the NSS pin must be pulled high
during the MODF bit clearing sequence. The SPE and MSTR bits can be restored to their original state after
this clearing sequence. As a security, hardware does not allow the SPE and MSTR bits to be set while the
MODF bit is set. In a slave device the MODF bit cannot be set except as the result of a previous multimaster
conflict.

CRC error(CRCERR)
This flag is used to verify the validity of the value received when the CRCEN bit in the SPIx_CR1 register is
set. The CRCERR flag in the SPIx_SR register is set if the value received in the shift register does not
match the receiver SPIx_RXCRCR value. The flag is cleared by the software.

TI mode frame format error(FRE)


A TI mode frame format error is detected when an NSS pulse occurs during an ongoing communication
when the SPI is operating in slave mode and configured to conform to the TI mode protocol. When this error
occurs, the FRE flag is set in the SPIx_SR register. The SPI is not disabled when an error occurs, the NSS
pulse is ignored, and the SPI waits for the next NSS pulse before starting a new transfer. The data may be
corrupted since the error detection may result in the loss of two data bytes.
The FRE flag is cleared when SPIx_SR register is read. If the ERRIE bit is set, an interrupt is generated on
the NSS error detection. In this case, the SPI should be disabled because data consistency is no longer
guaranteed and communications should be reinitiated by the master when the slave SPI is enabled again.

27.3.11. NSS pulse mode

This mode is activated by the NSSP bit in the SPIx_CR2 register and it takes effect only if the SPI interface
is configured as Motorola SPI master (FRF=0) with capture on the first edge (SPIx_CR1 CPHA = 0, CPOL
setting is ignored). When activated, an NSS pulse is generated between two consecutive data frame
transfers when NSS stays at high level for the duration of one clock period at least. This mode allows the
slave to latch data. NSSP pulse mode is designed for applications with a single master-slave pair.
Figure 27-14 illustrates NSS pin management when NSSP pulse mode is enabled.

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Fremont Micro Devices FT32F0xxx8 RM

Master continuous transfer(CPOL=1;CPHA=0;NSSP=1)


sample sample sample sample sample sample

NSS

SCK

MOSI MSB LSB MSB LSB

MISO DONTCARE MSB LSB DONTCARE MSB LSB DONTCARE

tSCK tSCK tSCK tSCK tSCK


4-bit to 16-bit 4-bit to 16-bit

Figure 27-14 NSSP pulse generation in Motorola SPI master mode


Note: Similar behavior is encountered when CPOL = 0. In this case the sampling edge is the rising edge of
SCK, and NSS assertion and deassertion refer to this sampling edge.

27.3.12. TI mode

TI protocol in master mode


The SPI interface is compatible with the TI protocol. The FRF bit of the SPIx_CR2 register can be used to
configure the SPI to be compliant with this protocol.
The clock polarity and phase are forced to conform to the TI protocol requirements whatever the values set
in the SPIx_CR1 register. NSS management is also specific to the TI protocol which makes the configuration
of NSS management through the SPIx_CR1 and SPIx_CR2 registers (SSM, SSI, SSOE) impossible in this
case.
In slave mode, the SPI baud rate prescaler is used to control the moment when the MISO pin state changes
to HiZ. Any baud rate can be used, making it possible to determine this moment with optimal flexibility.
However, the baud rate is generally set to the external master clock baud rate. The delay for the MISO
signal to become HiZ (trelease) depends on internal resynchronization and on the baud rate value set in
through the BR[2:0] bits in the SPIx_CR1 register. It is given by the formula:
𝑡𝑏𝑎𝑢𝑑_𝑟𝑎𝑡𝑒 𝑡𝑏𝑎𝑢𝑑𝑟𝑎𝑡𝑒
+ 4 ∗ 𝑡𝑝𝑐𝑙𝑘 < 𝑡𝑟𝑒𝑙𝑒𝑎𝑠𝑒 < + 6 ∗ 𝑡𝑝𝑐𝑙𝑘
2 2
If the slave detects a misplaced NSS pulse during a data frame transaction the TIFRE flag is set.
If the data size is equal to 4-bits or 5-bits, the master in full-duplex mode or transmit-only mode uses a
protocol with one more dummy data bit added after LSB. TI NSS pulse is generated above this dummy bit
clock cycle instead of the LSB in each period.

Rev1.3 604 2024-03-22


Fremont Micro Devices FT32F0xxx8 RM

NSS
g g g
r lin r lin r lin
g g e mp g g e mp g g e mp t RELEASE
tri sa tri sa tri sa
SCK

MOSI DONTCARE MSB LSB MSB LSB

MISO 1or0 MSB LSB MSB LSB

FRAM1 FRAM2

Figure 27-15 TI mode transfer

27.3.13. CRC calculation

Two separate CRC calculators are implemented in order to check the reliability of transmitted and received
data. The SPI offers CRC8 or CRC16 calculation independently of the frame data length, which can be fixed
to 8-bit or 16-bit. For all the other data frame lengths, no CRC is available.

CRC calculation is enabled by setting the CRCEN bit in the SPIx_CR1 register before the SPI is enabled
(SPE = 1). The CRC value is calculated (parallel CRC calculation) using an odd programmable polynomial
on each bit. For transmitter, CRC calculate when the TXFIFO transfer data to shift register. For receiver, the
CRC calculate when the shift register transfer data to RXFIFO. The calculated CRC value is checked
automatically at the end of the data block as well as for transfer managed by CPU or by the DMA. When a
mismatch is detected between the CRC calculated internally on the received data and the CRC sent by the
transmitter, a CRCERR flag is set to indicate a data corruption error. The right procedure for handling the
CRC calculation depends on the SPI configuration and the chosen transfer management.
Note: The polynomial value should only be odd. No even values are supported.

CRC transfer managed by CPU


Communication starts and continues normally until the last data frame has to be sent or received in the
SPIx_DR register. Then CRCNEXT bit has to be set in the SPIx_CR1 register to indicate that the CRC frame
transaction will follow after the transaction of the currently processed data frame. The CRCNEXT bit must be
set before the end of the last data frame transaction. CRC calculation is frozen during CRC transaction
The received CRC is stored in the RXFIFO like a data byte or word. That is why in CRC mode only, the
reception buffer has to be considered as a single 16-bit buffer used to receive only one data frame at a time.
A CRC-format transaction usually takes one more data frame to communicate at the end of data sequence.
However, when setting an 8-bit data frame checked by 16-bit CRC, two more frames are necessary to send
the complete CRC.
When the last CRC data is received, an automatic check is performed comparing the received value and the
value in the SPIx_RXCRC register. Software has to check the CRCERR flag in the SPIx_SR register to
determine if the data transfers were corrupted or not. Software clears the CRCERR flag by writing ‘0’ to it.

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Fremont Micro Devices FT32F0xxx8 RM

After the CRC reception, the CRC value is stored in the RXFIFO and must be read in the SPIx_DR register
in order to clear the RXNE flag.

CRC transfer managed by DMA


When SPI communication is enabled with CRC communication and DMA mode, the transmission and
reception of the CRC at the end of communication is automatic (with the exception of reading CRC data in
receive only mode). The CRCNEXT bit does not have to be handled by the software. The counter for the SPI
transmission DMA channel has to be set to the number of data frames to transmit excluding the CRC frame.
On the receiver side, the received CRC value is handled automatically by DMA at the end of the transaction
but user must take care to flush out received CRC information from RXFIFO as it is always loaded into it. In
full duplex mode, the counter of the reception DMA channel can be set to the number of data frames to
receive including the CRC, which means, for example, in the specific case of an 8-bit data frame checked by
16-bit CRC:
DMARX = Numb_of_data + 2
In receive only mode, the DMA reception channel counter should contain only the amount of data
transferred, excluding the CRC calculation. Then based on the complete transfer from DMA, all the CRC
values must be read back by software from FIFO as it works as a single buffer in this mode.
At the end of the data and CRC transfers, the CRCERR flag in the SPIx_SR register is set if corruption
occurred during the transfer.

Resetting the SPIx_TXCRC and SPIx_RXCRC values


The SPIx_TXCRC and SPIx_RXCRC values are cleared automatically when new data is sampled after a
CRC phase. This allows the use of DMA circular mode (not available in receive-only mode) in order to
transfer data without any interruption, (several data blocks covered by intermediate CRC checking phases).
If the SPI is disabled during a communication the following sequence must be followed
1. Disable the SPI
2. Clear the CRCEN bit
3. Enable the CRCEN bit
4. Enable the SPI
Note: In order to avoid any wrong CRC calculation, the software must enable CRC calculation only when the
clock is stable (in steady state).When the SPI interface is configured as a slave, the NSS internal signal
needs to be kept low between the data phase and the CRC phase.

27.4. SPI interrupts

During SPI communication an interrupts can be generated by the following events:


 Transmit TXFIFO ready to be loaded
 Data received in Receive RXFIFO
 Master mode fault
 Overrun error
 TI frame format error
 CRC protocol error
Interrupts can be enabled and disabled separately.

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Fremont Micro Devices FT32F0xxx8 RM

Table 27-1 SPI interrupt requests


Interrupt event Event flag Enable control bit
Transmit TXFIFO ready to be loaded TXE TXEIE
Data received in RXFIFO RXNE RXNEIE
Master Mode fault event MODF
Overrun error OVR ERRIE
TI frame format error FRE
CRC protocol error CRCERR

27.5. SPI register map

The peripheral registers can be accessed by half-words (16-bit) or words (32-bit). SPI_DR
in addition by can be accessed by 8-bit access.

The following table shows the SPI register map and reset values.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16

BIDIMODE15
BIDIOE 14
CRCEN 13
CRCNEXT12
11

RXONLY 10
Address offset Name

9
8

LSBFIRST7
6
5
4
3
2
1
0
MSTR

CPHA
CPOL
CRCL

SSM

SPE
SSI
SPIx_CR1 BR[2:0]
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–

0x00

Reset x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RXDMAEN
TXDMAEN
LDMA_RX
LDMA_TX

RXNEIE
FRXTH

ERRIE
TXEIE

NSSP
SSOE
FRF
SPIx_CR2 DS[3:0]
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–

0x04

Reset x x x x x x x x x x x x x x x x x 0 0 0 0 1
FRLVL[1:0] 1 1 0 0 0 0 0 0 0 0
FTLVL[1:0]

CRCERR
MODF

RXNE
OVR
BSY
FRE

TXE
SPIx_SR
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–

–
–
0x08

Reset x x x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0x x 1 0

SPIx_DR DR[15:0]
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–

0x0C

Reset x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SPIx_CRCPR CRCPOLY[15:0]
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–

0x10

Reset x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1

SPIx_RXCRCR RXCRC[15:0]
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–

0x14

Reset x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SPIx_TXCRCR TXCRC[15:0]
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–

0x18

Reset x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SSP

SPIx_SSPR
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–

–
–
–
–
–
–
–
–
–
–
–
–
–
–
–

0x300
Reset x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 0

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Fremont Micro Devices FT32F0xxx8 RM

27.5.1. SPI control register 1(SPIx_CR1)

Address offset: 0x00


Reset value: 0x0000
bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 BIDIMODE BIDIOE CRCEN CRCNEXT CRCL RXONLY SSM SSI
type RW RW RW RW RW RW RW RW
7:0 LSBFIRST SPE BR[2:0] MSTR CPOL CPHA
type RW RW RW RW RW RW RW RW

Bit Name Function


31:16 NA Reserved, undefined
15 BIDIMODE Bidirectional data mode enable.
This bit enables half-duplex communication using
common single bidirectional data line. Keep RXONLY bit clear when
bidirectional mode is active.
0:2-line unidirectional data mode selected (Full-duplex)
1: 1-line bidirectional data mode selected (Half-duplex)
14 BIDIOE Output enable in bidirectional mode
This bit combined with the BIDIMODE bit selects the direction of transfer in
bidirectional mode
0: Output disabled (receive-only mode)
1: Output enabled (transmit-only mode)
13 CRCEN Hardware CRC calculation enable
0: CRC calculation disabled
1: CRC calculation Enabled
12 CRCNEXT Transmit CRC next
0: Next transmit value is from Tx buffer
1: Next transmit value is from Tx CRC register
11 CRCL CRC length
This bit is set and cleared by software to select the CRC length.
0: 8-bit CRC length
1: 16-bit CRC length
10 RXONLY Receive only mode enabled.
This bit enables simplex communication using a single unidirectional line to
receive data exclusively. Keep BIDIMODE bit clear when receive only mode
is active.This bit is also useful in a multislave system in which this particular

Rev1.3 608 2024-03-22


Fremont Micro Devices FT32F0xxx8 RM

slave is not accessed, the output from the accessed slave is not corrupted.
0: Full duplex (Transmit and receive)
1: Output disabled (Receive-only mode)
9 SSM Software slave management
When the SSM bit is set, the NSS pin input is replaced with the value from
the SSI bit.
0: Software slave management disabled
1: Software slave management enabled
Note:This bit is not used in SPI TI mode.
8 SSI Internal slave select
This bit has an effect only when the SSM bit is set. The value of this bit is
forced onto the NSS pin and the I/O value of the NSS pin is ignored.
Note:This bit is not used in SPI TI mode
7 LSBFIRST Frame format
0: data is transmitted / received with the MSB first
1: data is transmitted / received with the LSB first
Note:1. This bit should not be changed when communication is ongoing.
2. This bit is not used in SPI TI mode.
6 SPE SPI enable
0: Peripheral disabled
1: Peripheral enabled
Note:When disabling the SPI, follow the procedure described in Procedure
for disabling the SPI
5:3 BR[2:0] Baud rate control
000: 𝑓𝑃𝐶𝐿𝐾 /2
001: 𝑓𝑃𝐶𝐿𝐾 /4
010: 𝑓𝑃𝐶𝐿𝐾 /8
011: 𝑓𝑃𝐶𝐿𝐾 /16
100: 𝑓𝑃𝐶𝐿𝐾 /32
101: 𝑓𝑃𝐶𝐿𝐾 /64
110: 𝑓𝑃𝐶𝐿𝐾 /128
111: 𝑓𝑃𝐶𝐿𝐾 /256
Note:These bits should not be changed when communication is ongoing.
2 MSTR Master selection
0: Slave configuration
1: Master configuration
Note:This bit should not be changed when communication is ongoing.
1 CPOL Clock polarity
0: CK to 0 when idle
1: CK to 1 when idle
Note:1.This bit should not be changed when communication is ongoing.
2.This bit is not used in SPI TI mode.
0 CPHA Clock phase

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Fremont Micro Devices FT32F0xxx8 RM

0: The first clock transition is the first data capture edge


1: The second clock transition is the first data capture edge
Note:1.This bit should not be changed when communication is ongoing.
2.This bit is not used in SPI TI mode.

27.5.2. SPI control register 2(SPIx_CR2)

Address offset: 0x04


Reset value: 0x0700
bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 Reserved LDMA_TX LDMA_RX FRXTH DS[3:0]
type RW RW RW RW RW RW RW RW
7:0 TXEIE RXNEIE ERRIE FRF NSSP SSOE TXDMAEN RXDMAEN
type RW RW RW RW RW RW RW RW

Bit Name Function


31:15 NA Reserved, undefined
14 LDMA_TX Last DMA transfer for transmission
This bit is used in data packing mode, to define if the total number of data to
transmit by DMA is odd or even. It has significance only if the TXDMAEN bit
in the SPIx_CR2 register is set and if packing mode is used (data length =<
8-bit and write access to SPIx_DR is 16-bit wide). It has to be written when
the SPI is disabled (SPE = 0 in the SPIx_CR1 register).
0: Number of data to transfer is even
1: Number of data to transfer is odd
Note: Refer to Procedure for disabling the SPI if the CRCEN bit is set.
13 LDMA_RX Last DMA transfer for reception
This bit is used in data packing mode, to define if the total number of data to
receive by DMA is odd or even. It has significance only if the RXDMAEN bit
in the SPIx_CR2 register is set and if packing mode is used (data length =<
8-bit and write access to SPIx_DR is 16-bit wide). It has to be written when
the SPI is disabled (SPE = 0 in the SPIx_CR1 register).
0: Number of data to transfer is even
1: Number of data to transfer is odd
Note: Refer to Procedure for disabling the SPI if the CRCEN bit is set.
12 FRXTH FIFO reception threshold
This bit is used to set the threshold of the RXFIFO that triggers an RXNE
event

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0: RXNE event is generated if the FIFO level is greater than or equal to 1/2
(16-bit)
1: RXNE event is generated if the FIFO level is greater than or equal to 1/4
(8-bit)
11:8 DS[3:0] Data size
These bits configure the data length for SPI transfers
0000: Not used
0001: Not used
0010: Not used
0011: 4-bit
0100: 5-bit
0101: 6-bit
0110: 7-bit
0111: 8-bit
1000: 9-bit
1001: 10-bit
1010: 11-bit
1011: 12-bit
1100: 13-bit
1101: 14-bit
1110: 15-bit
1111: 16-bit
If software attempts to write one of the “Not used” values, they are forced to
the value “0111”(8-bit).
7 TXEIE Tx buffer empty interrupt enable
0: TXE interrupt masked
1: TXE interrupt not masked. Used to generate an interrupt request when the
TXE flag is set.
6 RXNEIE RX buffer not empty interrupt enable
0: RXNE interrupt masked
1: RXNE interrupt not masked. Used to generate an interrupt request when
the RXNE flag is set.
5 ERRIE Error interrupt enable
This bit controls the generation of an interrupt when an error condition
occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
0: Error interrupt is masked
1: Error interrupt is enabled
4 FRF Frame format
0: SPI Motorola mode
1 SPI TI mode
Note: This bit must be written only when the SPI is disabled (SPE=0).
3 NSSP NSS pulse management
This bit should be set in master to enable NSSP mode. This bit can be set or

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Fremont Micro Devices FT32F0xxx8 RM

cleared in slave.it allow the SPI to generate an NSS pulse between two
consecutive data when doing continuous transfers. In the case of a single
data transfer, it forces the NSS pin high level after the transfer. It has no
meaning if CPHA = ’1’, or FRF = ’1’.
0: No NSS pulse
1: NSS pulse generated
Note: 1. This bit must be written only when the SPI is disabled (SPE=0).
2. This bit is not used in SPI TI mode.
2 SSOE SS output enable
0: SS output is disabled in master mode and the SPI interface can work in
multimaster configuration
1: SS output is enabled in master mode and when the SPI interface is
enabled. The SPI interface cannot work in a multimaster environment.
Note: This bit is not used in SPI TI mode.
1 TXDMAEN Tx buffer DMA enable
When this bit is set, a DMA request is generated whenever the TXE flag is
set.
0: Tx buffer DMA disabled
1: Tx buffer DMA enabled
0 RXDMAEN Rx buffer DMA enable
When this bit is set, a DMA request is generated whenever the RXNE flag is
set.
0: Rx buffer DMA disabled
1: Rx buffer DMA enabled

27.5.3. SPI status register(SPIx_SR)

Address offset: 0x08


Reset value: 0x0002
bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 — FTLVL[1:0] FRLVL[1:0] FRE
type RO-0 RO-0 RO-0 RW RO RO RO RO
7:0 BSY OVR MODF CRCERR — TXE RXNE
type RO RO RO RC_W0 RO-0 RO-0 RO RO

Bit Name Function


31:13 NA Reserved, undefined
12:11 FTLVL[1:0] FIFO Transmission Level

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Fremont Micro Devices FT32F0xxx8 RM

These bits are set and cleared by hardware.


00: FIFO empty
01: 1/4 FIFO
10: 1/2 FIFO
11: FIFO full (considered as FULL when the FIFO threshold is greater than
1/2)
10:9 FRLVL[1:0] FIFO reception level
These bits are set and cleared by hardware.
00:FIFO empty
01:1/4 FIFO
10:1/2 FIFO
11:FIFO full
Note:These bits are not used in SPI receive-only mode while CRC
calculation is enabled.
8 FRE Frame format error
This flag is used for SPI in TI slave mode. This flag is set by hardware and
reset when SPIx_SR is read by software.
0: No frame format error
1: A frame format error occurred
7 BSY Busy flag
0: SPI not busy
1: SPI is busy in communication or Tx buffer is not empty
This flag is set and cleared by hardware.
Note:The BSY flag must be used with caution: refer to Section SPI status
flags and Procedure for disabling the SPI
6 OVR Overrun flag
0: No overrun occurred
1: Overrun occurred
This flag is set by hardware and reset by a software sequence.
5 MODF Mode fault
0: No mode fault occurred
1: Mode fault occurred
This flag is set by hardware and reset by a software sequence. Refer to
Section : Mode fault (MODF) for the software sequence..
4 CRCERR CRC error flag
0: CRC value received matches the SPIx_RXCRCR value
1: CRC value received does not match the SPIx_RXCRCR value
3:2 NA Reserved, undefined
1 TXE Transmit buffer empty
0: Tx buffer not empty
1: Tx buffer empty
0 RXNE Receive buffer not empty
0: Rx buffer empty
1: Rx buffer not empty

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27.5.4. SPI data register(SPIx_DR)

Address offset: 0x0C


Reset value: 0x0000
bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 DR[15:8]
type RW RW RW RW RW RW RW RW
7:0 DR[7:0]
type RW RW RW RW RW RW RW RW

Bit Name Function


31:16 NA Reserved, undefined
15:0 DR[15:0] Data received or to be transmitted
The data register serves as an interface between the Rx and Tx FIFOs.
When the data register is read, RxFIFO is accessed while the write to data
register accesses TxFIFO (See Section: Data transmission and reception
procedures).
Note:Data is always right-aligned. Unused bits are ignored when writing to
the register, and read as zero when the register is read. The Rx threshold
setting must always correspond with the read access currently used.

27.5.5. SPI CRC polynomial register(SPIx_CRCPR)

Address offset: 0x10


Reset value: 0x0007
bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 CRCPOLY[15:8]
type RW RW RW RW RW RW RW RW
7:0 CRCPOLY[7:0]
type RW RW RW RW RW RW RW RW

Bit Name Function


31:16 NA Reserved, undefined

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Fremont Micro Devices FT32F0xxx8 RM

15:0 CRCPOLY[15:0] CRC polynomial register


This register contains the polynomial for the CRC calculation.
The CRC polynomial (0007h) is the reset value of this register. Another
polynomial can be configured as required.
Note: The polynomial value should be odd only. No even value is supported.

27.5.6. SPI Rx CRC register(SPIx_RXCRCR)

Address offset: 0x14


Reset value: 0x0000
bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 RXCRC[15:8]
type RO RO RO RO RO RO RO RO
7:0 RXCRC[7:0]
type RO RO RO RO RO RO RO RO

Bit Name Function


31:16 NA Reserved, undefined
15:0 RXCRC[15:0] Rx CRC register
When CRC calculation is enabled, the RxCRC[15:0] bits contain the
computed CRC value of the subsequently received bytes. This register is
reset when the CRCEN bit in SPIx_CR1 register is written to 1. The CRC is
calculated serially using the polynomial programmed in the SPIx_CRCPR
register.
Only the 8 LSB bits are considered when the data frame format is set to be
8-bit data (CRCL bit in the SPIx_CR1 is cleared). CRC calculation is done
based on any CRC8 standard.
The entire 16-bits of this register are considered when a 16-bit data frame
format is selected (CRCL bit in the SPIx_CR1 register is set). CRC
calculation is done based on any CRC16 standard.

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27.5.7. SPI Tx CRC register(SPIx_TXCRCR)

Address offset: 0x18


Reset value: 0x0000
bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 TXCRC[15:8]
type RO RO RO RO RO RO RO RO
7:0 TXCRC[7:0]
type RO RO RO RO RO RO RO RO

Bit Name Function


31:16 NA Reserved, undefined
15:0 TXCRC[15:0] Tx CRC register
When CRC calculation is enabled, the TxCRC[15:0] bits contain the
computed CRC value of the subsequently transmitted bytes. This register is
reset when the CRCEN bit of SPIx_CR1 is written to 1. The CRC is
calculated serially using the polynomial programmed in the SPIx_CRCPR
register.
Only the 8 LSB bits are considered when the data frame format is set to be
8-bit data (CRCL bit in the SPIx_CR1 is cleared). CRC calculation is done
based on any CRC8 standard.
The entire 16-bits of this register are considered when a 16-bit data frame
format is selected (CRCL bit in the SPIx_CR1 register is set). CRC
calculation is done based on any CRC16 standard.

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27.5.8. SPI slave speed register (SPIx_SSPR)

Address offset: 0x300


Reset value: 0x0000
bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 —
type RO RO RO RO RO RO RO RO
7:0 — SSP
type RO RO RO RO RO RO RO RW

Bit Name Function


31:1 NA Reserved, undefined
0 SSP 0: The max speed of AHB can be pclk/2 in slave mode
1: The max speed of AHB can be pclk/4 in slave mode

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28. Universal serial bus full-speed device


interface(USB)

28.1. Main features

 USB 1.1 support and specification version 2.0 full-speed compliant


 Configurable 7 common endpoints and 1 control endpoint
 Configurable for FIFO sizes of 1KB
 Support isochronous mode, bulk mode, interrupt mode transfer
 Double-buffered bulk transfer, interrupt mode and isochronous endpoint support
 Supports Suspend and Resume Signaling
 USB connect / disconnect capability (controllable embedded pull-up resistor enable)

28.2. Functional description

28.2.1. Block diagram

CPU
Endp;oint Control
interface
EP0 EP1-7 IN Interrupt
control
Control Control
OUT
Common

EP reg.

Combine Endpoints Interrupts


reg.

RAM Cycle control AHB


SIE
controller interface
USB Addr FIFO
Packet
generator decoder
Enc/Dec
Bit Shift
PID CRC Register Cycle
Stuff control 1KB RAM

Figure 28-1 USB peripheral block diagram


The USB peripheral provides an USB-compliant connection between the host PC and the function
implemented by the microcontroller.

Serial Interace Engine (SIE): The SIE handles isochronous mode recognized, bit stuffing/unstuffing, and
CRC generation/checking, PID received and generated. It generates headers for packets to be transmitted
and decodes the headers of received packets.

Endpoint controller: Control each endpoint transfer state and direction.Two controller state machines are

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used: one for control transfers over Endpoint 0, and one for Bulk, Interrupt or isochronous transactions over
Endpoints 1 to 7. Endpoints 1 to 7 only can be IN or OUT endpoint because the USB is half-duplex
619ffective619ng

RAM Controller: The RAM controller provides an interface to a single block of synchronous single-port
RAM which is used to buffer packets between the CPU and USB.

CPU Interface: The CPU Interface allows access to the control/status registers and the FIFOs for each
endpoint, and USB read/write SRAM data through CPU interface It also generates an interrupt to the CPU
when a packet has been successfully transmitted or received, or when the core enters Suspend mode or
resumes from Suspend mode.

28.2.2. USB RAM

1K USB RAM can be configured by the USB controller or AHB bus to be accessed. If the access method
changed when the data is transfer, it might cause data loss. It needs software to ensure the access method
changing not affect the data transfer.

28.2.2.1 Using USB RAM

Each endpoint can transfer data to the master. The data store in the corresponding FIFO block. The sending
data of each endpoint shared the same block with the received data, so sending data and receiving data can
not process at the same time. It need to be ensure whether the endpoint is configured as OUT when the
data is wrote to the buffer block, otherwise it should configured as IN. Each endpoint buffer distributed in
different area of 1kB SRAM as shown below. The INMAXP/OUTMAP register of each endpoint can not
exceed each endpoint maximum value.

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0x000
Endpoint0 64B
0x040
Endpoint1 64B
0x080
Endpoint2 64B
0x0c0
Endpoint3 64B
0x100
Endpoint4 128B
0x180
Endpoint5 128B
0x200
Endpoint6 256B
0x300
Endpoint7 256B
0x400

Figure 28-2 Distribution of Endpoints related memory area

Endpoint 1-7 is double-buffered, the value of IN/OUTMAXP register should be configured less than the half
of the endpoint related memory area. For example, double-buffered will beenabled automatically when the
configured value is less than 32B (Endpoint 1 phsical storage is 64B).

28.2.2.2 AHB access USB RAM

Accessing the USB RAM by AHB is need to set the URAMCTL and no need to set USBEN.
Softawre can read/write USB RAM when it accessed by AHB, like SRAM.
The USB RAM can be accessed by byte (8-bit) but can be not access half words (16-bit) or words (32-bit).

28.2.3. Transfer description

The USB peripheral interfaces with the USB host, detecting token packets, handling data
transmission/reception, and processing handshake packets as required by the USB standard. Packet is the
basic unit of USB transfmission, all data is packed than transfer in the AHB.

Field PID DATA CRC16

Byte
1 0-1024 2
number

Figure 28-3 Packet format

Control transferl
The host send request to the specified device by endpoint 0 incontrol transfer, then the device respond an
ACK

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The OUTPKTRDY of endpoint0 is set when endpoint0 receive a data packet, then CPU read the data packet
from FIFO and operates according to the data of the packet. If endpoint0 need to send data, then should
switch the FIFO direction to IN and write the data to the FIFO, eventually the corresponding INPKTRDY will
be set. The data will be send to the host automatically when the USB controller receive the IN token packets.
The receiver will respond an ACK if it is finish receiving and calibrate correct, otherwise respond a NACK.

When the endpoint0 receive a SETUP packet in idle state, the OUTPKTRDY bit set and enter the
corresponding interrupt if it is enabled, and read the FIFO data in the interrupt, then switch the FIFO
direction (MODE bit in the INCSR register) according to the instruction. Data will not be transfer if SETUP
packet set the address and interface command.

Setup send data format

OUT
INT

INT
INT

INT
Setup IN DATA IN DATA
STATE

Setup receive data format

OUT OUT IN

INT
INT
INT

INT

Setup
DATA DATA STATE

Setup not transfer format

IN
INT

INT

Setup INT:interrupt
STATE

Figure 28-4 Endpoint0 data transfer format

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Fremont Micro Devices FT32F0xxx8 RM

IDLE state

OUTPKTRDY==1？ No

Yes

Read FIFO Return

Decode command

Data transfer after


No Command processing
command?

Yes
Set
SERVICEDOUTPKTRDY
Set and set DATAEND
SERVICEDOUTPKTRDY

Return

IN token？ Yes Data send

No

Return
Data received

Return

Figure 28-5 Endpoint0 data processing flow


Note: No need to configure the INMAXP and OUTMAXP register for The endpoint 0

Bulk transfer
Bulk transfer mode can nonperiodic exchange data with host. Configure FIFO in output mode can write data
to FIFO, then the controller receive IN token and automatically send the FIFO data to the host. After the host
finsh calibrating, it will respond an ACK. Configure FIFO in input mode, then the controller receive OUT
token and automatically receive the FIFO data to the host. After the host finsh calibrating, it will respond an
ACK, otherwise it respond a NACK.

Bulk transfer can enable duble-buffered mode. When the value of INMAXP/OUTMAXP is less than or equal
to the FIFO size, double packet buffering is enabled, two data packets can be buffered in the FIFO. If the

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Fremont Micro Devices FT32F0xxx8 RM

last packet not be read already, the new packet can be received and both packet will not loss. It can also
advanced write two packets to FIFO when it is sending.

As a packet to be sent is loaded into the FIFO, the INPKTRDY bit should be set to inform the controller
write operation is complete. After the AUTOSET bit is set, the loaded data in FIFO is equal to the INMAX,
the INPKTRDY will be set automatically. After reading the FIFO data, the SERVICEDOUTPKTRDY should
be set to clear OUTPKTRDY flag, the OUTPKTRDY will be cleared automatically after the AUTOCLEAR is
enable and finish reading the FIFO data.

Endpoint 1-7 mode configuration:


 Configure INMAXP/OUTMAXP register, set the packet size, which should be equal to the max packet
field of the endpoint;
 Enable the endpoint interrupt control bit in INTRIN1E register;
 Clear ISO bit, enable bulk transfer;
 Clear CLRDATATOG to clear the state of endpoint.

Set SENDSTALL bit can disable the corresponding transfer state, when the software receive the
SENTSTALL flag, the SENTSTALL bit should be cleared. If an endpoint is no need then the SENDSTALL
should be 1. After clear the SENDSTALL bit ,the corresponding endpoint can be enable, and the
CLRDATATOG bit should be set to recover the data toggle state.

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Idle Idle

NO

Write data to FIFO


Valid OUT token？
NO

Set INPKTRDY NO YES

SENDSTALL==1？
Valid IN token？

YES
YES
Valid data(No
timeout)？
YES SENDSTALL==1？

YES
NO

STALL send, YES FIFOF==1？


Send data
INPKTRDYCleared,
SENTSTALL set
NO

Receive ACK STALLSend,


NACK send Data received
SENTSTALL set

INPKTRDY cleared

Interrupt generated
Interrupt generated

Idle
Idle

Data send Data received

Figure 28-6 Endpoint data send and receive flow chart in bulk mode

Interrupt mode
Interrupt mode can periodic exchange data with host, and the operation is similar to the bulk mode. Set
FRCDATATOG bit to force the data sending state to toggle. Whether the host respond an ACK or not, the
transmission will be recognized as succedd.

Isochronous mode (ISO mode)


Isochronous mode can periodic exchange a mass of data with host; The receiver will not respond an ACK. A
certain number of error is acceptable in this mode.

Double packet buffering is enabled in this mode when the INMAXP/OUTMAXP data is not greater than the
half the FIFO size.

After the AUTOSET bit is set, the corresponding endpoint FIFO data reach the configured value of the
INMAX, INPKTRDY will be set automatically. After AUTOCLEAR is set and endpoint receive data,

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Fremont Micro Devices FT32F0xxx8 RM

OUTPKTRDY will be cleared automatically when the CPU read the OUTMAXP.

Isochronous mode configuration:


 Configure INMAXP/OUTMAXP register, set the packet size, which should be equal to the max packet
field of the endpoint;
 Enable the endpoint interrupt control bit in INTRIN1E register;
 Set ISO to enable Isochronous mode.

In Isochronous mode, If FIFO do not have any data (CPU do not have enough time to write data into the
FIFO), UNDERRUN bit is set when a zero length data packet is sent. If FIFO do not have enough space
(CPU do not have enough time to read data from the FIFO), the OVERRUN bit is set . when the OVERRUN
or the UNDERRUN is set ,the software should clear it by increase CPU clock frequency etc. The
OUTPKTRDY bit and the DATAERROR bit will be set in Isochronous mode when the error is received (for
example CRC calibration falied), the software also should clear it.

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Fremont Micro Devices FT32F0xxx8 RM

Idle Idle

NO

Write data to FIFO NO


Valid OUT token?

NO YES

Valid IN token?

YES

Valid data (No


timeout)?
NO INPKTRDY==1？

YES
Yes

0 data send， YES FIFOF==1？


Data send
UNDERRUN set

NO

OVERRUN set Data received

INPKTRDY cleared，
Interrupt generated

OUTPKTRDY set,
interrupt generated

Idle
Idle

Data send Data received

Figure 28-7 Endpoint data send and receive flow in Isochronous mode

28.2.4. Suspend mode

The controller will enter the suspwnd mode when the USB bus keep in idle time exceed than 3ms, and the
SUSPENDE is set. The corresponding interrupt event will be generated if the SUSPENDIE

When the bus detect the resume signal, the controller will exit the suspend mode. Or set the RESUME bit to
force the interface to exit suspend state.

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28.3. USB register map

Offset Register Description

7
6
5
4
3
2
1
0
FADDR[7:0]
USB_FADDR
0x00

Reset 0 0 0 0 0 0 0 0

ISOUPDATE

SUSPENDM
SUSPENDE
RESUME
RESET
USB_POWER
0x01
_
_
_
Reset 0x x x 0 0 0 0
EP7INF
EP6INF

EP5INF
EP4INF
EP3INF
EP2INF
EP1INF
EP0F
USB_INTRIN
0x02

Reset 0 0 0 0 0 0 0 0 General register


EP7OUTF
EP6OUTF

EP5OUTF
EP4OUTF
EP3OUTF
EP2OUTF
EP1OUTF
USB_INTROUT
0x04 _

Reset 0 0 0 0 0 0 0x
SUSPEND
RESUME
RESET

USB_INTRUSB
0x06
SOF
_
_
_
_

Reset x x x x 0 0 0 0
EP7INIE
EP6INIE
EP5INIE
EP4INIE
EP3INE
EP2INE
EP1INE

USB_INTRINE
EP0E

0x07

Reset 1 1 1 1 1 1 1 1

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Fremont Micro Devices FT32F0xxx8 RM

Offset Register Description

EP7OUTIE 7
EP6OUTIE 6
EP5OUTIE 5
EP4OUTIE 4
EP3OUTIE 3
EP2OUTIE 2
EP1OUTIE 1
0
USB_INTROUTE
0x09

_
Reset 1 1 1 1 1 1 1 x

SUSPENDIE
RESUMEIE
RESETIE
USB_INTRUSBE
0x0b

SOFIE
_
_
_
_
Reset x x x x 0 1 1 0

USB_FRAM1 FRAME[7:0]
0x0c

Reset 0 0 0 0 0 0 0 0 General register


FRAME[10:8]

USB_FRAM2
0x0d
_
_
_
_
_

Reset x x x x x 0 0 0
INDEX[2:0]

USB_INDEX
0x0e
_
_
_
_
_

Reset x x x x x 0 0 0
PDEN
PUEN

USB_PDCTRL
0x0f
_
_
_
_
_
_

Reset x x x x x x 0 0

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Fremont Micro Devices FT32F0xxx8 RM

0
Offset Register Description

INMAXP[7:0]
0x10 USB_INMAXP

Reset 0 0 0 0 0 0 0 0

SOUTPKTRDY
SSETUPEND

OUTPKTRDY
SENDSTALL

SENTSTALL
SETUPEND

INPKTRDY
DATAEND
0x11 USB_CSR0 (Endpoint0)

Reset 0 0 0 0 0 0 0 0
CLRDATATOG

SENDSTALL
SENTSTALL

UNDERRUN
FLUSHFIFO

INPKTRDY
0x11 USB_INCSR1 (Endpoint1-7)

FIFONE
Reset 0 0 0 0 0 0 0 0
FRCDATATOG
AUTOSET

_
0x12 USB_INCSR2
MODE
ISO

Endpoint register(configure INDEX


Reset 0 0 1 x 0 x x x register first before access
endpoint register)
OUTMAXP[7:0]

0x13 USB_OUTMAXP

Reset 0 0 0 0 0 0 0 0
CLRDATATOG

DATAERROR

OUTPKTRDY
SENDSTALL
SENTSTALL

FLUSHFIFO

OVERRUN

0x14 USB_OUTCSR1
FIFOF

Reset 0 0 0 0 0 0 0 0
AUTOCLEAR

0x15 USB_OUTCSR2
ISO

Reset 0 0x x x x x x

0x16 USB_OUTCOUNTER OUTCOUNTER[7:0]

Reset 0 0 0 0 0 0 0 0

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Fremont Micro Devices FT32F0xxx8 RM

7
6
5
4
3
2
1

0
Offset Register Description

FIFO0[7:0]
0x20 USB_FIFO0

Reset x x x x x x x x

FIFO1[7:0]
0x24 USB_FIFO1

Reset x x x x x x x x

FIFO2[7:0]
0x28 USB_FIFO2

Reset x x x x x x x x

FIFO3[7:0]
0x2c USB_FIFO3

Reset x x x x x x x x
Data register
FIFO4[7:0]

0x30 USB_FIFO4

Reset x x x x x x x x
FIFO5[7:0]

0x34 USB_FIFO5

Reset x x x x x x x x
FIFO6[7:0]

0x38 USB_FIFO6

Reset x x x x x x x x
FIFO7[7:0]

0x3c USB_FIFO7

Reset x x x x x x x x

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Fremont Micro Devices FT32F0xxx8 RM

28.3.1. USB_FADDR

Bit 7 6 5 4 3 2 1 0
7:0 UPDATE FADDR[6:0]
Type RO RW

Bit Name Function


7 UPDATE Set when FADDR is written. Cleared when the new address takes effect (at
the end of the current transfer).
6:0 FADDR The function address.

28.3.2. USB_POWER

Bit 7 6 5 4 3 2 1 0
7:0 ISOUPDATE — RESET RESUME SUSPENDM SUSPENDE
Type RW RO-0 RO-0 RO-0 RO RW RO RW

Bit Name Function


7 ISOUPDATE 1: After INPKTRDY is set,wait for an SOF token in Isochronous mode before
sending the packet, If an IN token is received before an SOF token, then a
zero length data packet will be sent.
0: After INPKTRDY is set, no need to wait for the SOF token, data packet will
be sent if an IN token is received
6:4 NA Reserved
3 RESET 1: Reset signaling is present on the USB bus
0: Reset signaling is not present on the USB bus
2 RESUME 1: Resume signaling when the function is in Suspend mode. The CPU
should clear this bit after 10 ms (a maximum of 15 ms) to end Resume
0: Not resume when the function is in Suspend mode
1 SUSPENDM Cleared when the CPU reads the USB_INTRUSB, or sets the RESUME bit
of this register.
1: Suspend mode is entered
0: Suspend mode is not entered
0 SUSPENDE Set by the CPU to enable entry into Suspend mode when Suspend signaling
is received on the bus.
1: Enable entry into Suspend mode when Suspend signaling is received on
the bus
0: Not allow to entry into Suspend mode when Suspend signaling is received
on the bus

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Fremont Micro Devices FT32F0xxx8 RM

28.3.3. USB_INTRIN

Bit 7 6 5 4 3 2 1 0
7:0 EP7INF EP6INF EP5INF EP4INF EP3INF EP2INF EP1INF EP0F
Type RO RO RO RO RO RO RO RO

Bit Name Function


7 EP7INF IN Endpoint 7 interrupt.
1: Interrupt generated in IN mode
0: No interrupt generated in IN mode
6 EP6INF IN Endpoint 6 interrupt.
1: Interrupt generated in IN mode
0: No interrupt generated in IN mode
5 EP5INF IN Endpoint 5 interrupt.
1: Interrupt generated in IN mode
0: No interrupt generated in IN mode
4 EP4INF IN Endpoint 4 interrupt.
1: Interrupt generated in IN mode
0: No interrupt generated in IN mode
3 EP3INF IN Endpoint 3 interrupt.
1: Interrupt generated in IN mode
0: No interrupt generated in IN mode
2 EP2INF IN Endpoint 2 interrupt.
1: Interrupt generated in IN mode
0: No interrupt generated in IN mode
1 EP1INF IN Endpoint 1 interrupt.
1: Interrupt generated in IN mode
0: No interrupt generated in IN mode
0 EP0F Endpoint 0 interrupt.
1: Interrupt generated
0: No interrupt generated

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Fremont Micro Devices FT32F0xxx8 RM

28.3.4. USB_INTROUT

Bit 7 6 5 4 3 2 1 0
7:0 EP7OUTF EP6OUTF EP5OUTF EP4OUTF EP3OUTF EP2OUTF EP1OUTF —
Type RO RO RO RO RO RO RO RO-0

Bit Name Function


7 EP7OUTF OUT Endpoint 7 interrupt.
1: Interrupt generated in OUT mode
0: No interrupt generated in OUT mode
6 EP6OUTF OUT Endpoint 6 interrupt.
1: Interrupt generated in OUT mode
0: No interrupt generated in OUT mode
5 EP5OUTF OUT Endpoint 5 interrupt.
1: Interrupt generated in OUT mode
0: No interrupt generated in OUT mode
4 EP4OUTF OUT Endpoint 4 interrupt.
1: Interrupt generated in OUT mode
0: No interrupt generated in OUT mode
3 EP3OUTF OUT Endpoint 3 interrupt.
1: Interrupt generated in OUT mode
0: No interrupt generated in OUT mode
2 EP2OUTF OUT Endpoint 2 interrupt.
1: Interrupt generated in OUT mode
0: No interrupt generated in OUT mode
1 EP1OUTF OUT Endpoint 1 interrupt.
1: Interrupt generated in OUT mode
0: No interrupt generated in OUT mode
0 NA Reserved

28.3.5. USB_INTRUSB

Bit 7 6 5 4 3 2 1 0
7:0 — SOF RESET RESUME SUSPEND
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0

Bit Name Function


7:4 NA Reserved
3 SOF Set at the start of each frame, Cleared by read USB_INTRUSB
1: A start of each frame detected

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Fremont Micro Devices FT32F0xxx8 RM

0: No start of each frame detected


2 RESET Cleared by read USB_INTRUSB
1: Reset signaling is detected on the bus
0: No Reset signaling is detected on the bus
1 RESUME Cleared by read USB_INTRUSB
1: Resume signaling is detected on the bus in Suspend mode
0: No resume signaling is detected on the bus in Suspend mode
0 SUSPEND Cleared by read USB_INTRUSB
1: Suspend signaling is detected on the bus
0: No suspend signaling is detected on the bus

28.3.6. USB_INTRINE

Bit 7 6 5 4 3 2 1 0
7:0 EP7INE EP6INE EP5INE EP4INE EP3INE EP2INE EP1INE EP0IE
Type RW RW RW RW RW RW RW RW

Bit Name Function


7 EP7INE IN Endpoint 7 interrupt. Enable
1: IN Endpoint 7 Interrupt enabled
0: IN Endpoint 7 Interrupt disabled
6 EP6INE IN Endpoint 6 interrupt. Enable
1: IN Endpoint 6 Interrupt enabled
0: IN Endpoint 6 Interrupt disabled
5 EP5INE IN Endpoint 5 interrupt. Enable
1: IN Endpoint 5 Interrupt enabled
0: IN Endpoint 5 Interrupt disabled
4 EP4INE IN Endpoint 4 interrupt. Enable
1: IN Endpoint 4 Interrupt enabled
0: IN Endpoint 4 Interrupt disabled
3 EP3INE IN Endpoint 3 interrupt. Enable
1: IN Endpoint 3 Interrupt enabled
0: IN Endpoint 3 Interrupt disabled
2 EP2INE IN Endpoint 2 interrupt. Enable
1: IN Endpoint 2 Interrupt enabled
0: IN Endpoint 2 Interrupt disabled
1 EP1INE IN Endpoint 1 interrupt. Enable
1: IN Endpoint 1 Interrupt enabled
0: IN Endpoint 1 Interrupt disabled
0 EP0E Endpoint 0 interrupt. Enable
1: Endpoint 0 Interrupt enabled
0: Endpoint 0 Interrupt disabled

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Fremont Micro Devices FT32F0xxx8 RM

28.3.7. USB_INTROUTE

Bit 7 6 5 4 3 2 1 0
7:0 EP7OUTE EP6OUTE EP5OUTE EP4OUTE EP3OUTE EP2OUTE EP1OUTE —
Type RW RW RW RW RW RW RW RO-0

Bit Name Function


7 EP7OUTE OUT Endpoint 7 interrupt. Enable
1: OUT Endpoint 7 Interrupt enabled
0: OUT Endpoint 7 Interrupt disabled
6 EP6OUTE OUT Endpoint 6 interrupt. Enable
1: OUT Endpoint 6 Interrupt enabled
0: OUT Endpoint 6 Interrupt disabled
5 EP5OUTE OUT Endpoint 5 interrupt. Enable
1: OUT Endpoint 5 Interrupt enabled
0: OUT Endpoint 5 Interrupt disabled
4 EP4OUTE OUT Endpoint 4 interrupt. Enable
1: OUT Endpoint 4 Interrupt enabled
0: OUT Endpoint 4 Interrupt disabled
3 EP3OUTE OUT Endpoint 3 interrupt. Enable
1: OUT Endpoint 3 Interrupt enabled
0: OUT Endpoint 3 Interrupt disabled
2 EP2OUTE OUT Endpoint 2 interrupt. Enable
1: OUT Endpoint 2 Interrupt enabled
0: OUT Endpoint 2 Interrupt disabled
1 EP1OUTE OUT Endpoint 1 interrupt. Enable
1: OUT Endpoint 1 Interrupt enabled
0: OUT Endpoint 1 Interrupt disabled
0 NA Reserved

28.3.8. USB_INTRUSBE

Bit 7 6 5 4 3 2 1 0
7:0 — SOFIE RESETIE RESUMEIE SUSPENDIE
Type RO-0 RO-0 RO-0 RO-0 RW RW RW RW

Bit Name Function


7:4 NA Reserved
3 SOFIE 1: A start of each frame interrupt enabled
0: A start of each frame interrupt disabled
2 RESETIE 1: Reset signal interrupt enabled

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Fremont Micro Devices FT32F0xxx8 RM

0: Reset signal interrupt disabled


1 RESUMEIE 1: Resume signal interrupt enabled
0: Resume signal interrupt disabled
0 SUSPENDIE 1: Suspend signal interrupt enabled
0: Suspend signal interrupt disabled

28.3.9. USB_FRAM1

Bit 7 6 5 4 3 2 1 0
7:0 FRAM1[7:0]
Type RO RO RO RO RO RO RO RO

Bit Name Function


7:0 FRAM1 The lower 8 bits of the last received frame number.

28.3.10. USB_FRAM2

Bit 7 6 5 4 3 2 1 0
7:0 — FRAM2[2:0]
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO

Bit Name Function


7:3 NA Reserved
2:0 FRAM2 The upper 3 bits of the last received frame number.

28.3.11. USB_INDEX

Bit 7 6 5 4 3 2 1 0
7:0 — INDEX[3:0]
Type RO-0 RO-0 RO-0 RO-0 RW

Bit Name Function


7:4 NA Reserved
3:0 INDEX Selected Endpoint, Endpoint0 is selected when the INDEX=0

28.3.12. USB_PDCTRL

Bit 7 6 5 4 3 2 1 0
7:0 — PDEN PUEN
Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RW RW

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Fremont Micro Devices FT32F0xxx8 RM

Bit Name Function


7:2 NA Reserved
1 PDEN pull-down register in DM line
1: Pull-down register in DM line enabled
0: Pull-down register in DM line disabled
0 PUEN pull-up register in DP line
1: Pull-up register in DP line enabled
0: Pull-up register in DP line disabled

28.3.13. USB_CSR0

Bit 7 6 5 4 3 2 1 0
7:0 SSETUPE SOUTPKT SENDSTAL SETUPEN DATAEND SENTSTAL INPKTR OUTPKT
ND RDY L D L DY RDY
Type W1 W1 W1 RO W1 RC_W0 RS RO

Bit Name Function


7 SSETUPEND 1: Writes a 1 to this bit to clear the SETUPEND
0: Not clear the SETUPEND
6 SOUTPKTRDY 1: Writes a 1 to this bit to clear the OUTPKTRDY
0: Not clear the OUTPKTRDY
5 SENDSTALL The STALL handshake will be transmitted and then this bit will be cleared
automatically.
1: The CPU writes a 1 to this bit to terminate the current transaction
0: Not terminate the current transaction
4 SETUPEND This bit will be set when a control transaction ends before the DATAEND bit
has been set. An interrupt will be generated and the FIFO flushed at this
time
1: Receive SETUP token
0: Not receive SETUP token
3 DATAEND 1: Sending the last data packet or receiving the last data packet. Setting
INPKTRDY and DATAEND for a zero length data
0: Not transmitting the last data packet

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Fremont Micro Devices FT32F0xxx8 RM

2 SENTSTALL 1: A STALL handshake is transmitted


0: Clear the SENTSTALL bit
1 INPKTRDY The CPU sets this bit after loading a data packet into the FIFO. It is cleared
automatically when the data packet has been transmitted.
1: Data packet is loaded into the FIFO
0: Data packet is not ready
0 OUTPKTRDY This bit is set when a data packet has been received. The CPU clears this
bit by setting the SOUTPKTRDY

28.3.14. USB_OUTCOUNTER

Bit 7 6 5 4 3 2 1 0
7:0 OUTCOUNTER1[7:0]
Type RO RO RO RO RO RO RO RO

Bit Name Function


7:0 OUTCOUNTER The last received data in the corresponding endpoint

28.3.15. USB_INMAXP

Bit 7 6 5 4 3 2 1 0

7:0 INMAXP[7:0]

Type RW RW RW RW RW RW RW RW

Bit Name Function


7:0 INMAXP Maximum Packet Size/transaction in units of 8 bytes (IN 638ffectiv), for
example packet size is 8 bytes if INMAXP=1The value cannot configured
exceed the size of FIFO
Note: The packet size of endpoint 0 is 64 bytes and this register is read as
8’h0 when the endpoint is 0.

28.3.16. USB_INCSR1

Bit 7 6 5 4 3 2 1 0
7:0 — CLRDAT SENTSTALL SENDSTALL FLUSHFIFO OVERRUN FIFONE INPKTRDY
ATOG
Type RO-0 W1 RC_W0 RW W1 RC_W0 RC_W0 RS

Bit Name Function


7 NA Reserved
6 CLRDATATOG The CPU writes a 1 to this bit to reset the endpoint IN data toggle to 0.

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Fremont Micro Devices FT32F0xxx8 RM

1: reset the endpoint data


0: Not reset the endpoint data
5 SENTSTALL 1: A STALL handshake is transmitted
0: Clear this bit
4 SENDSTALL This bit has no effect if the IN endpoint is in ISO mode.
1: Issue a STALL handshake to an IN token
0: Terminate the stall condition
3 FLUSHFIFO 1: Flush the next packet to be transmitted from the endpoint IN FIFO.
0: Do not operate on FIFO data
2 UNDERRUN 1: In ISO mode, a zero length data packet is sent. In Bulk mode, a NAK is
returned in.
0: Clear this bit
1 FIFONE 1: At least 1 packet in the IN FIFO
0: IN FIFO is empty
0 INPKTRDY 1: Loading a data packet into the FIFO. It is cleared automatically when a
data packet has been transmitted
0: Data is not ready

28.3.17. USB_INCSR2

Bit 7 6 5 4 3 2 1 0
7:0 AUTOSET ISO MODE — FRCDATATOG —
Type RW RW RW RO-0 RW RO-0 RO-0 RO-0

Bit Name Function


7 AUTOSET INPKTRDY will be automatically set when INMAXP is loaded into the IN
FIFO
1: INPKTRDY automatically set enabled
0: INPKTRDY disabled
6 ISO 1: Isochronous mode (IN endpoint) enabled
0: Bulk/Interrupt mode (IN endpoint) enabled
5 MODE 1: Eenable the endpoint direction as IN
0: Enable the endpoint direction as OUT
4 NA Reserved
3 FRCDATATOG 1: Force the endpoint IN data toggle to switch regardless of whether an
ACK was received
0: Endpoint IN data normal toggle
2:0 NA Reserved

Rev1.3 639 2024-03-22


Fremont Micro Devices FT32F0xxx8 RM

28.3.18. USB_OUTMAXP

Bit 7 6 5 4 3 2 1 0
7:0 OUTMAXP[7:0]
Type RW RW RW RW RW RW RW RW

Bit Name Function


7:0 OUTMAXP Maximum Packet Size/transaction in units of 8 bytes (OUT endpoint), for
example packet size is 8 bytes if INMAXP=1The value cannot configured
exceed the size of FIFO

28.3.19. USB_OUTCSR1

Bit 7 6 5 4 3 2 1 0
7:0 CLRDAT SENTSTAL SENDSTAL FLUSHFIF DATAERRO OVERRU FIFOF OUTPKTR
ATOG L L O R N DY
Type W1 RC_W0 RW W1 RO RC_W0 RO RC_W0

Bit Name Function


7 CLRDATATOG 1: Reset the endpoint data toggle to 0.
0: Not reset the endpoint data
6 SENTSTALL 1: A STALL handshake is transmitted
0: Clear this bit
5 SENDSTALL 1: Issue a STALL handshake
0: Not issue a STALL handshake
4 FLUSHFIFO 1: Flush the next packet to be read from the endpoint OUT FIFO
0: Not flush the endpoint OUT FIFO
3 DATAERROR This bit is only valid in ISO mode
1: The data packet has a CRC or bit-stuff error
0: No error occurs in data transmission
2 OVERRUN This bit is only valid in ISO mode
1: An OUT packet cannot be loaded into the OUT FIFO
0: Clear this bit
1 FIFOF 1: No more packets can be loaded into the OUT FIFO
0: Packets can be loaded into the OUT FIFO
0 OUTPKTRDY 1: The OUT FIFO has data packet
0: The OUT FIFO do not have data packet

Rev1.3 640 2024-03-22


Fremont Micro Devices FT32F0xxx8 RM

28.3.20. USB_OUTCSR2

Bit 7 6 5 4 3 2 1 0
7:0 AUTOCLEAR ISO —
Type RW RW RO-0 RO-0 RO-0 RO-0 RO-0 RO-0

Bit Name Function


7 AUTOCLEAR 1: The OUTPKTRDY will be automatically cleared when a packet of
OUTMAXP bytes has been unloaded from the OUT FIFO.
0: The OUTPKTRDY will not be automatically cleared
6 ISO 1: Isochronous mode (OUT endpoint) enabled
0: Bulk/Interrupt mode (OUT endpoint) enabled
5:0 NA Reserved

28.3.21. USB_FIFO0

Bit 7 6 5 4 3 2 1 0
7:0 FIFO0[7:0]
Type RW

Bit Name Function


7:0 FIFO0 Endpoint0 data register. Writing these bis loads data into the IN FIFO for
the endpoint0. Reading these bits from the OUT FIFO for the endpoint0.

28.3.22. USB_FIFO1

Bit 7 6 5 4 3 2 1 0
7:0 FIFO1[7:0]
Type RW

Bit Name Function


7:0 FIFO1 Endpoint1 data register. Writing these bis loads data into the IN FIFO for
the endpoint1. Reading these bits from the OUT FIFO for the endpoint1.

28.3.23. USB_FIFO2

Bit 7 6 5 4 3 2 1 0
7:0 FIFO2[7:0]
Type RW

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Fremont Micro Devices FT32F0xxx8 RM

Bit Name Function


7:0 FIFO2 Endpoint2 data register. Writing these bis loads data into the IN FIFO for
the endpoint2. Reading these bits from the OUT FIFO for the endpoint2.

28.3.24. USB_FIFO3

Bit 7 6 5 4 3 2 1 0
7:0 FIFO3[7:0]
Type RW

Bit Name Function


7:0 FIFO3 Endpoint3 data register. Writing these bis loads data into the IN FIFO for
the endpoint3. Reading these bits from the OUT FIFO for the endpoint3.

28.3.25. USB_FIFO4

Bit 7 6 5 4 3 2 1 0
7:0 FIFO4[7:0]
Type RW

Bit Name Function


7:0 FIFO4 Endpoint4 data register. Writing these bis loads data into the IN FIFO for
the endpoint4. Reading these bits from the OUT FIFO for the endpoint4.

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Fremont Micro Devices FT32F0xxx8 RM

28.3.26. USB_FIFO5

Bit 7 6 5 4 3 2 1 0
7:0 FIFO5[7:0]
Type RW

Bit Name Function


7:0 FIFO5 Endpoint5 data register. Writing these bis loads data into the IN FIFO for
the endpoint5. Reading these bits from the OUT FIFO for the endpoint5.

28.3.27. USB_FIFO6

Bit 7 6 5 4 3 2 1 0
7:0 FIFO6[7:0]
Type RW

Bit Name Function


7:0 FIFO6 Endpoint6 data register. Writing these bis loads data into the IN FIFO for
the endpoint6. Reading these bits from the OUT FIFO for the endpoint6.

28.3.28. USB_FIFO7

Bit 7 6 5 4 3 2 1 0
7:0 FIFO7[7:0]
Type RW

Bit Name Function


7:0 FIFO7 Endpoint7 data register. Writing these bis loads data into the IN FIFO for
the endpoint7. Reading these bits from the OUT FIFO for the endpoint7.

Rev1.3 643 2024-03-22


Fremont Micro Devices FT32F0xxx8 RM

29. Touch sensing controller(TSC)

29.1. Introduction

The touch sensing controller provides a simple solution for adding capacitive sensing functionality to any
application. Capacitive sensing technology is able to detect finger presence near an electrode which is
protected from direct touch by a dielectric. The capacitive variation introduced by the finger (or any
conductive object) is measured using a proven implementation based on a surface charge transfer
acquisition principle.

29.2. TSC main features

The touch sensing controller has the following main features:


 Proven and robust surface charge transfer acquisition principle
 Supports up to 24 capacitive sensing channels
 Full hardware management of the charge transfer acquisition sequence
 Programmable charge transfer frequency

29.3. TSC functional description

29.3.1. Surface charge transfer acquisition overview

The surface charge transfer acquisition is a proven, robust and efficient way to measure a capacitance. It
uses a minimum number of external components to operate with a single ended electrode type. This
acquisition is designed around an analog I/O group which is composed of four GPIOs

Rev1.3 644 2024-03-22


Fremont Micro Devices FT32F0xxx8 RM

KEY0 KEY1 KEY2 KEY3 CAP


Electrod Electrod Electrod Electrod
0 1 2 3
Cx0 Cx1 Cx2 Cx3
Cs

drv_TK1 drv_TK2 drv_TK3 drv_TK4

Gx_KEY_EN0 Gx_KEY_EN1 Gx_KEY_EN2 Gx_KEY_EN3 Gx_CAP_EN


COMP
VDD

VDD
VLDO Gx_LDO_MOD_SEL

00 FLOAT
Gx_VDD_EN Gx_VLDO_EN
01 VLDO
10 VDD
11 GND

Gx_GND_EN

Figure 29-1 Touch sensing block diagram


The surface charge transfer acquisition principle consists of charging an electrode capacitance and
transferring a part of the accumulated charge into a sampling capacitor. This sequence is repeated until the
voltage reaches a given threshold. The number of charge transfers required to reach the threshold is a direct
representation of the size of the electrode capacitance.

29.3.2. Charge transfer acquisition sequence

The pulse low state of positive PWM and pulse high state of negative PWM stage is charging.
The pulse high state of positive PWM and pulse low state of negative PWM stage is charge transfers to the
sampling capacitor.
A dead time is inserted between the pulse high and low states to ensure an optimum charge transfer
acquisition sequence, the Charge transfer acquisition sequence diagram as shown below:

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Fremont Micro Devices FT32F0xxx8 RM

Charge deadtime transfer

touch_ldo_en

vldo_en

LDO pwm mode


KEY pwm mode
cap_en

key_en

Charge deadtime transfer

touch_ldo_en

vldo_en
LDO always on
KEY pwm mode

cap_en

key_en

Charge deadtime transfer

touch_ldo_en

LDO pwm mode vldo_en


KEY always on

cap_en

key_en

Charge deadtime transfer

touch_ldo_en

vldo_en
LDO always on
KEY always on
cap_en

key_en

Figure 29-2 Charge transfer acquisition sequence


Sampling capacitor voltage variation as shown below:

Rev1.3 646 2024-03-22


Fremont Micro Devices FT32F0xxx8 RM

Vcs

VDD

Threshold=VIH

0 TIME

Figure 29-3 Sampling capacitor voltage variation

29.3.3. Frequency hopping

Frequency hopping allows to generate a variation of the charge transfer frequency. This is done to improve
the robustness of the charge transfer acquisition in noisy environments and also to reduce the induced
emission. Enable/disable by configure FHSS_MODE. This mode is control the PWM generated by TIM17
and make the period and duty cycle changing continuously, the timing as shown below:

arr arr+1 arr+2 arr+3 arr+4 arr+5 arr+6 arr arr+1


ccr ccr+1 ccr+1 ccr+2 ccr+2 ccr+3 ccr+3 ccr ccr+1
charge charge charge charge charge charge charge charge charge
+0 +1 +1 +2 +2 +3 +3 +0 +1
vldo_en

cap_en

key_en
transfer transfer transfer transfer transfer transfer transfer transfer
+0 +0 +1 +1 +2 +2 +3 +0

Figure 29-4 Frequency hopping timing

29.3.4. TSC operating mode

Software mode
Configure TSC register to change the TSC LDO mode to control the charge-discharge process, the
procedure as shown below:,
1. Using the comparator to detect the voltage of sampling capacitor; one of the comparator input connect
to the sampling capacitor corresponding I/O, the other input connect to the output of DAC;
2. Initialize the TSC charging; Enable sampling capacitor and touchkey, set MOD_SEL=11, select GND
discharge mode to initialize the TSC discharging;

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Fremont Micro Devices FT32F0xxx8 RM

3. Enter deadtime, Disable sampling capacitor and touchkey and set MOD_SEL=00 to float touchkey.;
4. Charge the touchkey ; Enables touchkey and set MOD_SEL=01 to select VLDO voltage tocharge the
touchkey;
5. Enter deadtime again;
6. Sampling the transfer charge; Enable sampling capacitor and touchkey, the charge of touchkey will
transfer to the sampling capacitor.
7. Repeat the procedure 3~6 until the voltage of the sampling capacitor is exceed the threshold.

Hardware mode
Hardware PWM mode need to opeartewith TIM17 and the TIM17 should provide 2 complementary PWM
output with inserted deadtime. PWM waveform correspond to charge transfer sampling:
 Positive PWM output pulse low and negative PWM output pulse high correspond to the charging of the
charge transfer sampling;
 Positive PWM output pulse low and negative PWM output pulse low(deadtime) correspond to the
deadtime of the charge transfer sampling;
 Positive PWM output pulse high and negative PWM output pulse low correspond to the transfer of the
charge transfer sampling;
The procedure of the hardware PWM mode as shown below:
1. Using the comparator to detect the voltage of sampling capacitor; one of the comparator input connect
to the sampling capacitor corresponding I/O, the other input connect to the output of DAC;
2. Initialize the TSC charging; Enable sampling capacitor and touchkey, set MOD_SEL=11, select GND
discharge mode to initialize the TSC discharging;
3. Configure TSC as hardware mode (); Enable sampling capacitor and touchkey before set PWM_EN=1;
4. Configure TIM17 to generate the required PWM output

29.3.5. Capacitive sensing GPIOs

The table below provides an overview of the capacitive sensing GPIOs.


Table 29-1 Capacitive sensing GPIOs (VerA~C)
Group Capacitive sensing name Pin name
TSC_G1_CAP PA4
TSC_G1_IO1 PA0
TSC_G1_IO2 PA1
TSC_G1_IO3 PA2
1 TSC_G1_IO4 PA3
TSC_G1_IO5 PA5
TSC_G1_IO6 PA6
TSC_G1_IO7 PA7
TSC_G1_IO8 PB1
TSC_G2_CAP PB12
2 TSC_G2_IO1 PB0
TSC_G2_IO2 PB2

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Fremont Micro Devices FT32F0xxx8 RM

Group Capacitive sensing name Pin name


TSC_G2_IO3 PB10
TSC_G2_IO4 PB11
TSC_G2_IO5 PB13
TSC_G2_IO6 PB14
TSC_G2_IO7 PB15
TSC_G2_IO8 PA8
TSC_G3_CAP PA13
TSC_G3_IO1 PA9
TSC_G3_IO2 PA10
TSC_G3_IO3 PA11
3 TSC_G3_IO4 PA12
TSC_G3_IO5 PA14
TSC_G3_IO6 PA15
TSC_G3_IO7 PB3
TSC_G3_IO8 PB4

Table 29-2 Capacitive sensing GPIOs (≥VerD)


Group Capacitive sensing name Pin name
TSC_G1_CAP PB12
TSC_IO1 PA0
TSC_IO2 PA1
TSC_IO3 PA2
TSC_IO4 PA3
TSC_IO5 PA5
TSC_IO6 PA6
TSC_IO7 PA7
TSC_IO8 PB1
TSC_IO9 PB0
TSC_IO10 PB2
1
TSC_IO11 PB10
TSC_IO12 PB11
TSC_IO13 PB13
TSC_IO14 PB14
TSC_IO15 PB15
TSC_IO16 PA8
TSC_IO17 PA9
TSC_IO18 PA10
TSC_IO19 PA11
TSC_IO20 PA12
TSC_IO21 PA14

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Fremont Micro Devices FT32F0xxx8 RM

Group Capacitive sensing name Pin name


TSC_IO22 PA15
TSC_IO23 PB3
TSC_IO24 PB4

29.3.6. TSC low power mode

Table 29-3 lowpower mode status of TSC


Mode Description
SLEEP TSC can operate in hardware PWM mode
STOP TSC register cannot be accessed and PWM stop
STANDBY TSC stop operating until MCU exit STOP/STANDBY mode

29.4. TSC register map


31
30
29
28
27

G3_CAP_EN 26
G2_CAP_EN 25
G1_CAP_EN 24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
Offset Register

9
8
7
6
5
4
3
2
1
0
LDO_MODE

TSC_CR G3_KEY_EN[7:0] G2_KEY_EN[7:0] G1_KEY_EN[7:0]


–
–
–

0x00

Reset X X X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HW_MOD_SEL

G3_PWM_SEL

G2_PWM_SEL

G1_PWM_SEL
G3_PWM_EN

G2_PWM_EN

G1_PWM_EN
G3_CG_MOD

G2_CG_MOD

G1_CG_MOD
MOD_SEL

MOD_SEL

MOD_SEL
G3_LDO_

G2_LDO_

G1_LDO_
TSC_CFGR
–
–
–
–
–
–
–

–
–
–

–
–
–

–
–
–
0x04

Reset X X X X X X X X X X X 0 0 0 0 0 X X X 0 0 0 0 0 X X X 0 0 0 0 0

29.4.1. TSC_CR

Address offset: 0x00


Reset value: 0x0000
Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 — LDO_PWR_SEL[1:0] G3_CAP_EN G2_CAP_EN G1_CAP_EN

Type RO-0 RO-0 RO-0 RW RW RW RW RW


23:16 G3_KEY_EN[7:0]
Type RW RW RW RW RW RW RW RW
15:8 G2_KEY_EN[7:0]
Type RW RW RW RW RW RW RW RW
7:0 G1_KEY_EN[7:0]
Type RW RW RW RW RW RW RW RW

Bit Name Function


31:29 NA Reserved

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Fremont Micro Devices FT32F0xxx8 RM

28:27 LDO_MODE[1:0] VLDO charging voltage level


Three channel share one level selction. These bits valid only if VLOD
charging mode is selected (Gx_LDO_MOD_SEL = 01), otherwise no effect
00: 2V
01: 2V
10: 3V
11: 4V
26 G3_CAP_EN Group3 sampling capacitor enable
0: G3 sampling capacitor disabled
1: G3 sampling capacitor enabled
25 G2_CAP_EN Group2 sampling capacitor enable
0: G2 sampling capacitor disabled
1: G2 sampling capacitor enabled
24 G1_CAP_EN Group1 sampling capacitor enable
0: G1 sampling capacitor disabled
1: G1 sampling capacitor enabled
23:16 G3_KEY_EN[7:0] Group3 toucheyx enable
0: Group3 toucheyx disabled
1: Group3 toucheyx enabled
15:8 G2_KEY_EN[7:0] Group2 toucheyx enable
0: Group2 toucheyx disabled
1: Group2 toucheyx enabled
7:0 G1_KEY_EN[7:0] Group1 toucheyx enable
0: Group1 toucheyx disabled
1: Group1 toucheyx enabled

29.4.2. TSC_CFGR

Address offset: 0x04


Reset value: 0x0000
Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 — HW_MOD_SEL

Type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RW


23:16 — G3_LDO_MOD_SEL G3_CG_MOD G3_PWM_SEL G3_PWM_EN

Type RO-0 RO-0 RO-0 RW RW RW RW RW


15:8 — G2_LDO_MOD_SEL G2_CG_MOD G2_PWM_SEL G2_PWM_EN

Type RO-0 RO-0 RO-0 RW RW RW RW RW


7:0 — G1_LDO_MOD_SEL G1_CG_MOD G1_PWM_SEL G1_PWM_EN

Type RO-0 RO-0 RO-0 RW RW RW RW RW

Bit Name Function


31:25 NA Reserved

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24 HW_MOD_SEL Hardwre PWM control model selection


This bit is valid when Gx_PWM_EN=1
0: PWM control GPIO to charge-discharge
1: PWM control LDO to charge-discharge
23:21 NA Reserved
20:19 G3_LDO_MOD_SEL Group3 charge-discharge mode selection. Refer to
G1_LDO_MOD_SEL
18 G3_CG_MOD G3 charge transfer direction G3. Refer to G1_CG_MOD.
17 G3_PWM_SEL G3 PWM source
This bit is valid when G3_PWM_EN=1
0: TIM17 ch1 as G3 PWM source
1: TIM1 ch3 as G3 PWM source
16 G3_PWM_EN Group3 hardware mode enables. Refer to G1_PWM_EN.
15:13 NA Reserved
12:11 G2_LDO_MOD_SEL Group2 charge-discharge mode selection. Refer to
G1_LDO_MOD_SEL
10 G2_CG_MOD G2 charge transfer direction. Refer to G1_CG_MOD.
9 G2_PWM_SEL G2 PWM source
This bit is valid when G2_PWM_EN=1
0: TIM16 ch1 as G2 PWM source
1: TIM1 ch2 as G2 PWM source
8 G2_PWM_EN Group2 hardware mode enables. Refer to G1_PWM_EN.
7:5 NA Reserved
4:3 G1_LDO_MOD_SEL Group1 charge-discharge mode selection
00: Floating, LDO not charge/discharge
01: VLDO charging mode, Select VLDO of LDO to charge the touchkey
10: VDD charging mode, Select VDD of LDO to charge the touchkey
11: GND discharge mode, Select GND of LDO to discharge the
touchkey
2 G1_CG_MOD G1 charge transfer direction
0: The sampling capacitor is charge transfers to the touch sensing
channel
1: The touch sensing channel is charge transfers to the sampling
capacitor
1 G1_PWM_SEL G1 PWM source
This bit is valid when G1_PWM_EN=1
0: TIM15 ch1 as G1 PWM source
1: TIM1 ch1 as G1 PWM source
0 G1_PWM_EN Group1 hardware mode enable
User should configure the TSC register to charge/discharge touchkey
when this bit is 0, Timer should be configured to generate PWM to
charge /discharge touchkey when this bit is set .
0: Hardware mode disabled
1: Hardware mode enabled

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30. Debug support(Debug)

30.1. Overview

The FT32F0xxx8 devices are built around a Cortex®-M0 core which contains hardware extensions for
advanced debugging features. The debug extensions allow the core to be stopped either on a given
instruction fetch (breakpoint) or data access (watchpoint). When stopped, the core’s internal state and the
system’s external state may be examined. Once examination is complete, the core and the system may be
restored and program execution resumed.
The debug features are used by the debugger host when connecting to and debugging the FT32F0xxx8
Support:
 Serial wire

FT32F0xxx8 MCU debug support

Cortex-M0 debug support

Bus matrix
System
interface

Cortex-M0
Core

Debug AP

}
SWDIO

SWCLK
SW-DP
Debug AP
Bridge DBGMCU

NVIC

DWT

BPU

Figure 30-1 Block diagram of debug support


CPU core provides integrated on-chip debug support. It is comprised of:
 SW-DP: Serial wire
 BPU: Break point unit
 DWT: Data watchpoint trigger
 Flexible debug pinout assignment

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 MCU debug box (support for low-power modes), control over peripheral clocks

30.1.1. Reference ARM documentation

 ARM® Cortex®-M0 Technical Reference Manual (TRM) It is available from:


http://infocenter.arm.com
 ARM Debug Interface V5
 ARM CoreSight Design Kit revision r1p1 Technical Reference Manual

30.2. Function description

30.2.1. Pinout and debug port pins

FT32F0xxx8 MCUs are available in various packages with different numbers of available pins.

30.2.2. SWD port pins

Two pins of FT32F0xxx8 are used as outputs for the SW-DP as general purpose I/Os. These pins are
available on all packages.
Table 30-1 port pins
SW debug port
SWJ-DP pin name Pin assignment
Type Debug assignment
Serial Wire Data
SWDIO input/output PA13
Input/Output
SWCLK input Serial Wire Clock PA14

30.2.3. Internal pull-up & pull-down on SWD pins

Once the SW I/O is released by the user software, the GPIO controller takes control of these pins, it is
necessary to ensure those pins are not configured in floating mode. The reset states of the GPIO control
registers put the I/Os in the equivalent states:
 SWDIO: input pull-up
 SWCLK: input pull-down
Those I/Os can be configured as normal GPIOs by software.

30.2.4. ID codes and locking mechanism

There are several ID codes inside the FT32F0xxx8

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30.2.5. MCU device ID code

The FT32F0xxx8 products integrate an MCU ID code. This ID identifies the MCU part number and the die
revision. This code is accessible by the software debug port (two pins) or by the user software.

DBGMCU_IDCODE: Only 32-bit access supported. Read-only

30.2.6. SWD protocol introduction

This synchronous serial protocol uses two pins:


SWCLK: clock from host to target
SWDIO: bidirectional

The protocol allows two banks of registers (DPACC registers and APACC registers) to be read and written
to.
Bits are transferred LSB-first on the wire.

For SWDIO bidirectional management, the line must be pulled-up on the board (100 kΩ recommended)

Each time the direction of SWDIO changes in the protocol, a turnaround time is inserted where the line is not
driven by the host nor the target. By default, this turnaround time is one bit time, however this can be
adjusted by configuring the SWCLK frequency.

30.2.7. SWD protocol sequence

Each sequence consist of three phases:


1. Packet request (8 bits) transmitted by the host
2. Acknowledge response (3 bits) transmitted by the target
3. Data transfer phase (33 bits) transmitted by the host or the target
Bit Name Description
0 Start Must be “1”
1 ApnDP 0: DP Access
1: AP Access
2 RnW 0: Write Request
1: Read Request
4:3 A(3:2) Address field of the DP or AP registers
5 Parity Single bit parity of preceding bits
6 Stop 0
7 Park Not driven by the host. Must be read as
“1” by the target because of the pull-up

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Refer to the CPU for a detailed description of DPACC and APACC registers.

The packet request is always followed by the turnaround time (default 1 bit) where neither the host nor target
drive the line.
Bit Name Description
0..2 ACK 001: FAULT
010: WAIT
100: OK

The ACK Response must be followed by a turnaround time only if it is a READ transaction or if a WAIT or
FAULT acknowledge has been received.
Bit Name Description
0..31 WDATA/RDATA Write or Read data
32 Parity Single parity of the 32 data bits
The DATA transfer must be followed by a turnaround time only if it is a READ transaction.

30.2.8. SW-DP state machine (reset, idle states, ID code)

The State Machine of the SW-DP has an internal ID code which identifies the SW-DP. It follows the JEP-106
standard.
Note:Note that the SW-DP state machine is inactive until the target reads this ID code.
The SW-DP state machine is in RESET STATE either after power-on reset, or after the line is high for more
than 50 cycles.
The SW-DP state machine is in IDLE STATE if the line is low for at least two cycles after RESET state.
After RESET state, it is mandatory to first enter into an IDLE state AND to perform a READ access of the
DP-SW ID CODE register. Otherwise, the target will issue a FAULT acknowledge response on another
transactions.

30.2.9. DP and AP read/write accesses

Read accesses to the DP are not posted: the target response can be immediate (if ACK=OK) or can be
delayed (if ACK=WAIT).
Read accesses to the AP are posted. This means that the result of the access is returned on the next
transfer. If the next access to be done is NOT an AP access, then the DP-RDBUFF register must be read to
obtain the result.
The READOK flag of the DP-CTRL/STAT register is updated on every AP read access or RDBUFF read
request to know if the AP read access was successful.
The SW-DP implements a write buffer (for both DP or AP writes), that enables it to accept a write operation
even when other transactions are still outstanding. If the write buffer is full, the target acknowledge response
is “WAIT”. With the exception of IDCODE read or CTRL/STAT read or ABORT write which are accepted
even if the write buffer is full.

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Because of the asynchronous clock domains SWCLK and HCLK, two extra SWCLK cycles are needed after
a write transaction (after the parity bit) to make the write effective internally. These cycles should be applied
while driving the line low (IDLE state),This is particularly important when writing the CTRL/STAT for a
power-up request. If the next transaction (requiring a power-up) occurs immediately, it will fail.

30.2.10. SW-DP registers

Access to these registers are initiated when ApnDP=0


CTRLSEL bit
A[3:2] R/W of SELECT Register Notes
register
The idcode is set to:
00 Read IDCODE
0x1BA01477(identifies the SW-DP)
00 Write ABORT
request a system or debug power-up;
configure the transfer operation for AP
accesses;
DP-CTRL/
01 Read/Write 0 control the pushed compare and pushed
STAT
verify operations.
Read some status flags (overrun,
power-up acknowledges)
Purpose is to configure the physical serial
WIRE
01 Read/Write 1 port protocol (like the duration of the
CONTROL
turnaround time)
Enables recovery of the read data from a
READ
10 Read corrupted debugger transfer, without
RESEND
repeating the original AP transfer.
The purpose is to select the current
10 Write SELECT access port and the active 4-words
register window
This read buffer is useful because AP
accesses are posted (the result of a read
AP request is available on the next AP
READ
11 Read/Write transaction). This read buffer captures
BUFFER
data from the AP, presented as the result
of a previous read, without initiating a new
transaction

30.2.11. SW-AP registers

Access to these registers are initiated when ApnDP=1


There are many AP Registers addressed as the combination of:

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1. The shifted value A[3:2]


2. The current value of the DP SELECT register.
Address A[3:2] Description
0x00 00 Reserved
DP CTRL/STAT register. Used to:
– Request a system or debug power-up
0x04 01 – Configure the transfer operation for AP accesses
–Control the pushed compare and pushed verify operations.
–Read some status flags (overrun, power-up acknowledges)
DP SELECT register: Used to select the current access port
and the active 4-words register window.
– [31:24]: APSEL: select the current AP
0x08 10 – [23:8]: reserved
– [7:4]: APBANKSEL: elect the active 4-words register window
on the current AP
– [3:0]: reserved
DP RDBUFF register: Used to allow the debugger to get the
0x0C 11 final result after a sequence of operations (without requesting
new JTAG-DP operation)

30.2.12. Core Debug registers

Core debug is accessed through the core debug registers. The Debug Fault Status Register (DFSR,
address is 0xE000ED30, each bit cleared by writing 1) provides status information about the state of the
debug event and the reason of core halted. When core is halted by debug event the corresponding bit will be
set.
Address Register Description
Debug Halting Control and Status Register(DHCSR) User can
0xE000EDF0 DHCSR enable core debug halt and step the processor by configuring
DHCSR register
Debug Core Register Selector Register(DCRSR) User can
read/write core register by configuring DCRSR when core is
0xE000EDF4 DCRSR
halted. This selects the processor register to transfer data to or
from.
Debug Core Register Data Register(DCRDR) This holds data
0xE000EDF8 DCRDR for reading and writing registers to and from the core register
selected by the DCRSR (Selector) register.
Debug Exception and Monitor Control Register(DEMCR) is
0xE000EDFC DEMCR used for interrupt control in debug mode or DWT module
enabled.

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30.2.13. MCU debug component (DBGMCU)

The MCU debug component helps the debugger provide support for:
 Low-power modes
 Clock control for timers, watchdog during a breakpoint

30.2.14. Debug support for low-power modes

To enter low-power mode, the instruction WFI or WFE must be executed. The MCU implements several
low-power modes which can either deactivate the CPU clock or reduce the power of the CPU. The core
does not allow FCLK or HCLK to be turned off during a debug session. As these are required for the
debugger connection, during a debug, they must remain active. The MCU integrates special means to allow
the user to debug software in low-power modes.

For this, the debugger host must first set some debug configuration registers to change the low-power mode
behavior:
In Sleep mode: the DBG_SLEEP bit must be previously set by the debugger. This provides the same
frequency as FCLK (configured by software) for HCLK in Sleep mode.

In Stop mode, the DBG_STOP bit must be previously set by the debugger. This enables the internal RC
oscillator clock to feed FCLK and HCLK in Stop mode.

30.2.14.1 Debug support for timers, watchdog

During a breakpoint, it is necessary to choose how the counter of timers and watchdog should behave:
 They can continue to count inside a breakpoint. This is usually required when a PWM is controlling a
motor, for example.
 They can stop to count inside a breakpoint. This is required for watchdog purposes.

30.2.14.2 Debug MCU configuration register (DBGMCU_CR)

This register allows the configuration of the MCU under DEBUG. This concerns:
 Low-power mode support
 Timer and Watchdog support
DBGMCU_CR register is mapped to AHB bus, Base address: 0x40013404.
It is asynchronously reset by the PORESET (and not the system reset). It can be written by the debugger
under system reset.
If the debugger host does not support these features, it is still possible for the user software to write to these
registers.

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30.3. Core Debug register map

Core Debug registers Base address: 0xe000ed00.


Address offset Name

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DWTTRAP
VCATCH

HALTED
EXTERNAL

BKPT
DFSR
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
0x30

Reset x x x x x x x x x x x x x x x x x x x x x x x x x x x 0 0 0 0 0
DBGKEY[15:0]

C_MASKINTS
ST_RETIRE_ST

C_DEBUGEN
S_RESET_ST

S_LOCKUP

C_STEP
C_HALT
S_READY
S_SLEEP
S_HALT
0xF0 DHCSR

_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_

_
_
_
_
Reset x x x x x x 1 0 x x x x 0 0 0 0 x x x x x x x x x x x x 0 0 0 0

REGWnR

REGSEL

[4:0]
DCRSR
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_

_
_
_
_
_
_
_
_
_
_
_
0xF4

Reset x x x x x x x x x x x x x x x 0 x x x x x x x x x x x 0 0 0 0 0

DCRDR DBGTMP[31:0]
0xF8

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

VC_CORERESET
VC_HARDERR
DWTENA

DEMCR
_
_
_
_
_
_
_

_
_
_
_
_
_
_
_
_
_
_
_
_

_
_
_
_
_
_
_
_
_
0xFC

Reset x x x x x x x 0 x x x x x x x x x x x x x 0 x x x x x x x x x 0

30.3.1. DFSR

Address offset: 0x30


Reset value: 0x0000 0000

bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0


31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
7:0 — EXTERNAL VCATCH DWTTRAP BKPT HALTED
type RO-0 RO-0 RO-0 RW RW RW RW RW

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Bit Name Function


31:5 NA Reserved
4 EXTERNAL EDBGRQ is set (always read as 0, no external debug request)
3 VCATCH Vector catch occured
2 DWTTRAP Data watchpoint matched
1 BKPT Breakpoint matched
0 HALTED Debug halted or Single step

30.3.2. DHCSR

Address offset: 0xF0


Reset value: 0x0000 0000

bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0


31:24 DBGKEY[15:8]
— S_RESET S_RETIRE
_ST _ST
type RW RW RW RW RW RW RW RW
23:16 DBGKEY[7:0]
— S_LOCKUP S_SLEEP S_HALT S_READY
type RW RW RW RW RW RW RW RW
15:8 Reserved
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
7:0 — C_MASKI C_STEP C_HALT C_DEBUG
NTS EN
type RO-0 RO-0 RO-0 RO-0 RW RW RW RW

Bit Name Function


31:26,23: NA Reserved
20,15:4
31:16 DBGKEY Debug Key: Most significant 16 bits must be 0xA05F in write operation,
otherwise write operation will be ignored
25 S_RESET_ST Reset status flag, this bit is set when core is reset or in the reset phase,
cleared by reading this bit.
24 S_RETIRE_ST Instruction finfished flag, cleared by reading this bit.
19 S_LOCKUP Core lockup status flag, clear by halting core
18 S_SLEEP Core sleep flag
17 S_HALT Core halt flag
16 S_READY Handshake flag, this bit is set when core finish reading/writing register
3 C_MASKINTS Interrupt mask bit, 661ffective only when debug is enabled

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Fremont Micro Devices FT32F0xxx8 RM

2 C_STEP Single step control bit, 662ffective only when debug is enabled
1 C_HALT Core halted control bit, 662ffective only when debug is enabled
0 C_DEBUGEN Debug enable bit, debug is enabled when C_DEBUGEN is set
Note : DHCSR[31 :16 must be ] 0xA05F in write operation ;
DHCSR[31 :26] are reserved and DHCSR[25 :16] are correspoding status flag in read operation.

30.3.3. DCRSR

Address offset: 0xF4


Reset value: 0x0000 0000

bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0


31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 — REGWnR
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 W
15:8 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
7:0 — REGSEL[4:0]
type RO-0 RO-0 RO-0 WO WO WO WO WO

Bit Name Function


31:17,15: NA Reserved
5
16 REGWnR Core register read/write. 1:Write; 0:read
4:0 REGSEL Core register select
REGSEL:
5’b00000:R0;
5’b00001:R1;
…
5’b01100:R12;
5’b01101:current SP;
5’b01110:LR;
5’b01111:DebugReternAddrese (The address of executed Instruction when
debug is exited)
5’b10000:xPSR;
5’b10001:MSP;
5’b10010:PSP;
5’b10100:CONTROL(DCRDR[25:24]),PRIMASK(DCRDR[0])

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Fremont Micro Devices FT32F0xxx8 RM

30.3.4. DCRDR

Address offset: 0xF8


Reset value:0x0000 0000

bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0


31:24 DBGTMP[31:24]
type RW RW RW RW RW RW RW RW
23:16 DBGTMP[23:16]
type RW RW RW RW RW RW RW RW
15:8 DBGTMP[15:8]
type RW RW RW RW RW RW RW RW
7:0 DBGTMP[7:0]
type RW RW RW RW RW RW RW RW

Bit Name Function


31:0 DBGTMP Core register transmit data

30.3.5. DEMCR

Address offset: 0xFC


Reset value: 0x0000 0000

bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0


31:24 — DWTENA
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RW
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 — VC_HARD —
ERR
type RO-0 RO-0 RO-0 RO-0 RO-0 RW RO-0 RO-0
7:0 — VC_CORE
RESET
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RW

Bit Name Function


31:25 NA Reserved
24 DWTENA DWT enable bit
23:11 NA Reserved
10 VC_HARDERR HardFault interrupt enter error
9:1 NA Reserved
0 VC_CORERESET System reset before core is halted

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Fremont Micro Devices FT32F0xxx8 RM

30.4. MCU Debug register map

Base address: 0x40015800

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
Offset Register

9
8
7
6
5
4
3
2
1
0
IDCODE REV_ID[15:0] DEV_ID[11:0]

_
_
_
_
0x00

Reset 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 1 0 0 1 0 0 0

DBG_STANDBY
DBG_STOP
DBGMCU_CR
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_

_
0x04

Reset x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 0 0 x
DBG_I2C1_SMBUS_TIMEOUT

DBG_WWDG_STOP

DBG_TIM14_STOP
DBG_IWDG_STOP

DBG_TIM7_STOP
DBG_TIM6_STOP

DBG_TIM3_STOP
DBG_RTC_STOP
DBGMCU_APB1
_
_
_
_
_
_
_
_
_
_

_
_
_
_
_
_
_
_

_
_

_
_

_
0x08 _FZ

Reset x x x x x x x x x x 0 x x x x x x x x 0 0 0 x 0 x x 0 0 x x 0 x
DBG_TIM17_STOP
DBG_TIM16_STOP
DBG_TIM15_STOP

DBG_TIM1_STOP

DBGMCU_APB2
_
_
_
_
_
_
_
_
_
_
_
_
_

_
_
_
_

_
_
_
_
_
_
_
_
_
_
0x0C _FZ _

Reset x x x x x x x x x x x x x 0 0 0 x x x x 0 x x x x x x x x x x x

30.4.1. DBGMCU_IDCODE

Address offset: 0x00


Only 32-bit access are supported. Only read.

Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0


31:24 VERSION[3:0] PARTNO[15:12]
type RO RO RO RO RO RO RO RO

Rev1.3 664 2024-03-22


Fremont Micro Devices FT32F0xxx8 RM

23:16 PARTNO[11:4]
type RO RO RO RO RO RO RO RO
15:8 PARTNO[3:0] DESIGNER[11:8]
type RO RO RO RO RO RO RO RO
7:0 DESIGNER[7:1] —
type RO RO RO RO RO RO RO RO-1

Bit Name Function


31:16 VERSION ECO revision
15:12 PARTNO DP part number, SW-DP: 0xBB11
11:1 DESIGNER Designer ID, ARM default value: 0x23B
0 NA Reserved

30.4.2. Debug MCU configuration register (DBGMCU_CR)

Address offset: 0x04


Reset value: 0x0000 0000

bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0


31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
7:0 — DBG_ DBG_ —
STANDBY STOP
type RO-0 RO-0 RO-0 RO-0 RO-0 RW RW RO-0

Bit Name Function


31:24,23: NA Reserved
16,
15:8,7:3,
0
2 DBG_STANDBY Debug Standby mode
0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
From software point of view, exiting from Standby is identical than
fetching reset vector (except a few status bit indicated that the MCU is
resuming from Standby)
1: (FCLK=On, HCLK=On) In this case, the digital part is not
unpowered and FCLK and HCLK are provided by the internal RC
oscillator which remains active. In addition, the MCU

Rev1.3 665 2024-03-22


Fremont Micro Devices FT32F0xxx8 RM

generate a system reset during Standby mode so that exiting from


Standby is identical than fetching from reset
1 DBG_STOP Debug Stop mode
0: (FCLK=Off, HCLK=Off) In STOP mode, the clock controller disables
all clocks (including HCLK and FCLK). When exiting from STOP mode,
the clock configuration is identical to the one after RESET (CPU
clocked by the 8 MHz internal RC oscillator (HSI)). Consequently, the
software must reprogram the clock controller to enable the PLL, the
Xtal, etc.
1: (FCLK=On, HCLK=On) In this case, when entering STOP mode,
FCLK and HCLK are provided by the internal RC oscillator which
remains active in STOP mode. When exiting STOP mode, the software
must reprogram the clock controller to enable the PLL, the Xtal, etc. (in
the same way it would do in case of DBG_STOP=0)

30.4.3. Debug MCU APB1 freeze register(DBGMCU_APB1_FZ)

Address offset: 0x08


Reset value: 0x0000 0000

bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0


31:24 Reserved
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 — DBG_ —
I2C1_
SMBUS_
TIMEOUT
type RO-0 RO-0 RW RO-0 RO-0 RO-0 RO-0 RO-0
15:8 — DBG_ DBG_ DBG_ — DBG_
IWDG_ WWDG_ RTC_ TIM14_
STOP STOP STOP STOP
type RO-0 RO-0 RO-0 RW RW RW RO-0 RW
7:0 — DBG_ DBG_ — DBG_ —
TIM7_ TIM6_ TIM3_
STOP STOP STOP
type RO-0 RO-0 RW RW RO-0 RO-0 RW RO-0

Bit Name Function


31:22, NA Reserved
20:13,
9,7:6,3:2,
0

Rev1.3 666 2024-03-22


Fremont Micro Devices FT32F0xxx8 RM

21 DBG_I2C1_SMBUS_TI SMBUS timeout mode stopped when core is halted


MEOUT 0: Same behavior as in normal mode
1: The SMBUS timeout is frozen
12 DBG_IWDG_STOP Debug independent watchdog stopped when core is halted
0: The independent watchdog counter clock continues even if the core
is halted
1: The independent watchdog counter clock is stopped when the core
is halted
11 DBG_WWDG_STOP Debug window watchdog stopped when core is halted
0: The window watchdog counter clock continues even if the core is
halted
1: The window watchdog counter clock is stopped when the core is
halted
10 DBG_RTC_STOP Debug RTC stopped when core is halted
0: The clock of the RTC counter is fed even if the core is halted
1: The clock of the RTC counter is stopped when the core is halted
8 DBG_TIM14_STOP TIM14 counter stopped when core is halted
0: The counter clock of TIM14 is fed even if the core is halted
1: The counter clock of TIM14 is stopped when the core is halted
5 DBG_TIM7_STOP TIM7 counter stopped when core is halted.
0: The counter clock of TIM7 is fed even if the core is halted
1: The counter clock of TIM7 is stopped when the core is halted
4 DBG_TIM6_STOP TIM6 counter stopped when core is halted
0: The counter clock of TIM6 is fed even if the core is halted
1: The counter clock of TIM6 is stopped when the core is halted
1 DBG_TIM3_STOP TIM3 counter stopped when core is halted
0: The counter clock of TIM3 is fed even if the core is halted
1: The counter clock of TIM3 is stopped when the core is halted

Rev1.3 667 2024-03-22


Fremont Micro Devices FT32F0xxx8 RM

30.4.4. Debug MCU APB2 freeze register (DBGMCU_APB2_FZ)

Address offset: 0x0C


Reset value: 0x0000 0000

bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0


31:24 Reserved
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 — DBG_ DBG_ DBG_
TIM17_ TIM16_ TIM15_
STOP STOP STOP
type RO-0 RO-0 RO-0 RO-0 RO-0 RW RW RW
15:8 — DBG_ —
TIM1_
STOP
type RO-0 RO-0 RO-0 RO-0 RW RO-0 RO-0 RO-0
7:0 Reserved
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0

Bit Name Function


31:19, NA Reserved
15:12,
10:0
18 DBG_TIM17_STOP TIM17 counter stopped when core is halted
0: The counter clock of TIM17 is fed even if the core is halted
1: The counter clock of TIM17 is stopped when the core is halted
17 DBG_TIM16_STOP TIM16 counter stopped when core is halted
0: The counter clock of TIM16 is fed even if the core is halted
1: The counter clock of TIM16 is stopped when the core is halted
16 DBG_TIM15_STOP TIM15 counter stopped when core is halted
0: The counter clock of TIM15 is fed even if the core is halted
1: The counter clock of TIM15 is stopped when the core is halted
11 DBG_TIM1_STOP TIM1 counter stopped when core is halted
0: The counter clock of TIM 1 is fed even if the core is halted
1: The counter clock of TIM 1 is stopped when the core is halted

Rev1.3 668 2024-03-22


Fremont Micro Devices FT32F0xxx8 RM

31. Device electronic signature

31.1. Overview

The device electronic signature is stored in the System memory area of the Flash memory module, and can
be read using the debug interface or by the CPU. It contains factory-programmed identification and
calibration data that allow the user firmware or other external devices to automatically match to the
characteristics of the FT32F0xxx8 microcontroller.

31.2. Unique device ID register (96 bits)

The unique device identifier is ideally suited:


 for use as serial numbers (for example USB string serial numbers or other end applications)
 for use as part of the security keys in order to increase the security of code in Flash memory while using
and combining this unique ID with software cryptographic primitives and protocols before programming
the internal Flash memory
 to activate secure boot processes, etc.
The 96-bit unique device identifier provides a reference number which is unique for any FT32F0xxx8 device.
These bits cannot be altered by the user.
Base address: 0x1FFFF7AC

Address offset: 0x00


Read only, which is factory-programmed
bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 UID[31:24]
type RO RO RO RO RO RO RO RO
23:16 UID[23:16]
type RO RO RO RO RO RO RO RO
15:8 UID[15:8]
type RO RO RO RO RO RO RO RO
7:0 UID[7:0]
type RO RO RO RO RO RO RO RO

Address offset: 0x04


Read only, which is factory-programmed
bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 UID[63:56]
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 UID[55:48]
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0

Rev1.3 669 2024-03-22


Fremont Micro Devices FT32F0xxx8 RM

15:8 UID[47:40]
type RO RO RO RO RO RO RO RO
7:0 UID[39:32]
type RO RO RO RO RO RO RO RO

Address offset: 0x08


Read only, which is factory-programmed
bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 UID[95:88]
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 UID[87:80]
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 UID[79:72]
type RO RO RO RO RO RO RO RO
7:0 UID[71:64]
type RO RO RO RO RO RO RO RO

Rev1.3 670 2024-03-22


Fremont Micro Devices FT32F0xxx8 RM

31.3. Flash size register map

Base address: 0x1FFFF7CC

Address offset Name

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Flash_size _ Flash_size[15:0]
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
0x00

Reset x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

31.3.1. FLASH_SIZE

Address offset: 0x00


Reset value:0x0000 0000
bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
23:16 —
type RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0 RO-0
15:8 FLASH_SIZE[15:8]
type RO RO RO RO RO RO RO RO
7:0 FLASH_SIZE[7:0]
type RO RO RO RO RO RO RO RO

Bit Name Function


31:16 NA Reserved
15:0 FLASH_SIZE This bitfield indicates the size of the device Flash memory expressed
in Kbytes.
As an example, 0x40 corresponds to 64 Kbytes.

Rev1.3 671 2024-03-22


Fremont Micro Devices FT32F0xxx8 RM

Revision History
Date Revision Description
2022-06-23 1.0 Preliminary version
2022-10-20 1.1 Correct some clerical errors
Add introduction page
Add note for turning off the HSI14 clock in the low-power mode
Correct the description of HSEDRVEN in RCC_HSECFG register
Delete the description of FLASH factory configuration
Modify the operational amplifier description
2023-01-16 1.2 Add memory address information of TS_CAL1、TS_CAL2 and VREFINT_CAL
2024-03-22 1.3 Correct some clerical errors
Update Table 3-3 Access status versus protection level and execution modes
Correct the description of HSEDRVEN in RCC_HSECFG register
Add capacitive sensing GPIOs information for ≥VerD chips

Rev1.3 672 2024-03-22

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