Far as DRAM state, the separation kernel keeps the state of one process separate from another. Harder to do with a cache without defeating the performance-enhancing purpose of a cache.
"in fact DRAM effectively has an SRAM on-chip "cache" keeping the current active row per bank."
Had no idea. That could be a problem. See why we systems people defaulted on physical separation during most of the Moore's Law advances? Never know what hardware issue will pop up.
"in fact DRAM effectively has an SRAM on-chip "cache" keeping the current active row per bank."
Had no idea. That could be a problem. See why we systems people defaulted on physical separation during most of the Moore's Law advances? Never know what hardware issue will pop up.