That doesnt make sense to me. On haswell/skylake ports 0 and 1 do most of the ve... | Hacker News

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jnordwick on April 15, 2018 | parent | context | favorite | on: Is sorted using SIMD instructions

That doesnt make sense to me. On haswell/skylake ports 0 and 1 do most of the vector lifting. I don't think cores share any of the vector hardware.

Or are you trying to make some claim about hyperthreading?

alfanick on April 15, 2018 [–]

I simply may be wrong :) There is other AVX related thing [0] - CPU is underclocked in Turbo when AVX is used.

[0]: https://www.anandtech.com/show/11544/intel-skylake-ep-vs-amd...

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