It's current manifestation is very much a 'good enough' solution. I just wanted a scheme for simple all-to-all connectivity to map the serial ports to, and the only traffic it carries at the moment is either terminal traffic or disk data from the SD card, so it's not even close to being taxed. The obvious improvements are to add deep buffers to hide the latency of credit return, crank up the clock and to make the bus wider. This board could probably handle a 200-bit wide bus at 100 MHz+ speeds with no problems. Computer architecture is a fun hobby =)