The TL;DR is that the accelerometer is integrated so that it's in the "always on" untrusted ___domain, so to access it from the main FPGA "SoC" you have to go through the system controller FPGA ("EC" as we call it). The idea is for it to be available in power down states for anti-tamper, hence the extra layer of complication.
The accelerometer is the LSM6DS3, I'll refer you directly to the manufacturer's website: https://www.st.com/en/mems-and-sensors/lsm6ds3.html
You can find out more about how it's integrated at https://github.com/betrusted-io/betrusted-hardware/blob/mast... (note: this is a "DVT" schematic, bugs were found, they are currently being fixed, but they aren't related to the accelerometer).
The TL;DR is that the accelerometer is integrated so that it's in the "always on" untrusted ___domain, so to access it from the main FPGA "SoC" you have to go through the system controller FPGA ("EC" as we call it). The idea is for it to be available in power down states for anti-tamper, hence the extra layer of complication.
Talking to it requires a call to the EC via the "COM" bus (https://github.com/betrusted-io/betrusted-soc/blob/master/fw...). The EC driver itself is based on the C-native library provided by STM and translated into Rust bindings. It's a little gross: https://github.com/betrusted-io/betrusted-ec/blob/master/sw/...
Hope that helps.