Besides being able to pack more transistors into a given area, a smaller transistor has less gate capacitance (to first order). This means it can switch faster (smaller RC time constant) and less energy is expended in switching. Thus, going from generation to generation, the overall energy expenditure of a chip can be kept within a reasonable range despite adding many more transistors. You also may have heard of a "die shrink", where an existing design gets shrunk to the next technology node, using less power and clocking faster.

Shrinking isn't always a walk in the park though. Some nodes ago subthreshold leakage became a big problem until they figured out how to solve it.