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6510's clock is driven from the VICII. So the 100mhz would be paused half the time while the VICII did its thing.



Actually the bigger problem with this design on a second read through is that it tries to mirror the ROM and RAM into a 64K on-chip RAM. That won't work on the C64 because of the bank switching and the fact the VICII can access memory everywhere. You'd have to change it to use the on-chip RAM as a smarter cache.

If you were to disable the use of the on-chip RAM it'd be stalled far more than half the time, as it'd be unable to fetch instructions fast enough.




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