This was already an issue on the Commodore 128, which had a 2 MHz "fast" mode but you had to manually engage it, and doing so would turn off the VIC-II. Good for doing large calculations or working in 80 column text mode, but useless for games etc.
Yeah I suppose one could use a CPU similar to this 100mhz FPGA one and just have it do ~50 cycles worth of activity every time the VIC-II yielded control to it. Then it'd be idle for 50 cycles, etc. And then have a "fast" mode like you're talking about to do 100 cycles in a clock.
Memory and peripheral access would be seriously wait-stated though. 50 cycles of action doesn't do you much good if memory is slow. Especially when you consider that programs for the 65xx made heavy use of zero page / direct page as an extra bank of pseudo-registers.
So you'd end up implementing some kind of cache, or memory mirroring, or just moving the whole of RAM in the FPGA... and then you start to wonder why you didn't just do the whole thing in FPGA as a C64 SoC.
I thought that the faster 6502-clone should have its own 64kb RAM and only let writes end up on original RAM. So only writes should be slowed down to the original 6510 free slot.
All reads could be from fast RAM.
Then we have hardware registers and external DMA, those have to be handled specially.
