Where to start. Multiple pins supplying power to a die isn't done because they can't clonk a pair of big connectors in the middle. The resistance within the die would cause different ground levels and voltage drops if supplied at only one physical ___location. The PCB has much more space for "thick" copper traces (complete ground plane) and buffer caps to supply a stable voltage across the entire die.

Second, CPUs have a dedicated 12V rail on the MB since quite some time. It's plugged in right near the voltage regulators of the CPU.

Third, a GPU die also has multiple power rails and distribution over the die as CPUs. Given the insane power requirements and transistor count, they likely have even more. The same is true for other power hungry ICs, for example high-speed DSPs, FPGAs, image sensors and so on.

Fourth, PCI/PCIe can't carry hundredths of watts, it would not be cost effective to kit out PCs with heavy duty connectors and thick main board traces just because one or two slots may one day be used for a space heater. Thus another dedicated rail from the PSU.

There are some interesting reasons for that.

When a lot of transistors in an integrated circuit all switch at the same time, it can cause the chip's power and ground voltage levels to shift, relative to the circuit board's power and ground levels. The size of the difference depends on the inductance between the chip and board, i.e. the inductance of the chip's power and ground pins. Inductance can be minimized by connecting a lot of inductors in parallel. Lots of small pins are better than a few big ones.

If the inductance is too high and the chip's power voltage falls below its ground voltage, this will randomize every storage element on the chip. The rule of thumb is that a third of the pins need to be power or ground.

You're implying it could be done if whatever load distribution and power condition that's done outside of the chip, which consists of a lot of analog components to help manage rapid changes in power consumption, could be somehow packaged inside the chip.

So, in rough terms, the internals of a large-scale chip are not one big integrated circuit, but a large number of smaller modules that are massively interconnected, then?

That rule of thumb seems to apply to only a particular class of chips. Wouldn't the number of pins be somehow proportional to the power draw, as at higher currents induction would become a more severe problem? It's just usually the case that more power-hungry chips have more pins, as the 2011 socket is for Intel's flagship CPUs, the 1155 ones more commodity-oriented.

With the power voltage dropping below ground, that unless you had a floating ground, that'd be implying reverse flow of current, negative voltage, right? Or are you talking about a non-zero voltage ground? I'm not sure what the presumption is in real-world CPU design.

> That rule of thumb seems to apply to only a particular class of chips. Wouldn't the number of pins be somehow proportional to the power draw, as at higher currents induction would become a more severe problem?

I think it depends on the chip's speed. The problem is with rapid changes in current. Of course, higher currents can also have higher fluctuations.

> With the power voltage dropping below ground, that unless you had a floating ground, that'd be implying reverse flow of current, negative voltage, right? Or are you talking about a non-zero voltage ground?

Suppose the board's ground rail is 0 V and the power rail is at 12 V. The chip's ground voltage might bounce up to 9 and its power down to 8. It does cause reverse currents and other bad effects.

Ah, so the ground gets pulled up and the power driven down.

Thanks. This makes a lot more sense. I never thought Intel was doing something for no reason, but the reasoning wasn't obvious.

The vast majority of power efficiency losses are in the copper interconnects within the chip, not the copper pins.

Oh also, if you want fewer power pins, get ready for more heat and way more expensive CPUs. The pins are placed to be as cost effective and efficient as possible to power the individual chip modules (many of which will operate at different voltages). Also, it's way cheaper to convert power on the motherboard than within an already incredibly constrained CPU package.

Edit: "vast majority" as far as power and other connections to the board go, the transistors create way more heat than the interconnects.

It's sorta like plugging your PC into the wall plug next to it, and plugging your toaster into the wall plug in your kitchen...Yea, it would be easier to daisy-chain surge protectors from 1 outlet, but that's so messy. Like interior design layout, like circuit design layout?

And (I think) the copper circuits are so close that quantum leaps can occur -- electrons can just decide to jump from one piece of copper to another, straight through silicon or anything else, simply because the copper is so close. This means a VCC line can be giving charge to an unpowered neighboring circuit or memory cell without magnetically affecting it.

Chips have multiple power pins for signal integrity issues. You want the power source close to where it is being used, particularly for IO pads. Even chips with low power requirements will have multiple power pins.